Historique des commits

Auteur SHA1 Message Date
  Sylvain Munaut 1cdde8f8ea projects/boot_stub: Add target to easily build bootloader il y a 4 ans
  Sylvain Munaut 8b0bebfde2 projects/riscv_usb: Add custom vendor commands in DFU firmware il y a 5 ans
  Sylvain Munaut acbdbcccd3 projects/riscv_usb: Add Makefile target to program app via DFU il y a 5 ans
  Sylvain Munaut a3065f1629 projects/riscv_usb: Import DFU firmware il y a 5 ans
  Sylvain Munaut 92c03a9355 projects/riscv_usb: Update Makefile with new bootcode targets il y a 5 ans
  Sylvain Munaut f69146d035 projects/riscv_usb: Update fw/ gitignore il y a 5 ans
  Sylvain Munaut 8cc8acfb36 projects/riscv_usb: Complete overhaul of the USB stack il y a 5 ans
  Sylvain Munaut 0eec262a74 projects/riscv_usb: Add nano.specs in the CFLAGS il y a 5 ans
  Sylvain Munaut cb358304ff projects/riscv_usb: Adapt to allow 64k/128k of SPRAM il y a 5 ans
  Sylvain Munaut c80f0a9f67 cores/mem_cache: Improvement on the memory simulator il y a 4 ans
  Sylvain Munaut 3bd5ca1a5f cores/mem_cache: Initial import of iCE40 memory cache il y a 5 ans
  Sylvain Munaut 7c7e120a84 projects: Update constraints for bitsy v0 and v1 il y a 4 ans
  Sylvain Munaut c1483f3018 projects/riscv_usb: Update BOARD define for C source to match verilog one il y a 4 ans
  Sylvain Munaut c138c61984 cores/e1: Add option to use an external LIU instead of the iCE40 as PHY il y a 5 ans
  Sylvain Munaut f147c005db cores/e1: Minor synth improvement on CRC core il y a 5 ans
  Sylvain Munaut 21300d8cfe cores/e1: Fix CRC error marker in BD out fifo il y a 5 ans
  Sylvain Munaut f8b05c3630 cores/e1: Still generate TS0 pattern in case of underruns. il y a 5 ans
  Sylvain Munaut e51318fa05 cores/e1: Export tick for TX and RX path il y a 5 ans
  Sylvain Munaut 96e0348be9 cores/e1: Import register level documentation il y a 5 ans
  Sylvain Munaut effdabf3cd cores/e1: Import E1 core il y a 5 ans
  Sylvain Munaut 12891bcfc7 projects/memtest: Add missing PCF file for icebreaker il y a 4 ans
  Sylvain Munaut 3e030f46ee cores/qspi_master: Prevent yosys from using a bram for 16-element ROM il y a 4 ans
  Sylvain Munaut 5c5570cd71 cores/qspi_master: Fix port type 'reg' vs 'wire' for phy_io_i il y a 4 ans
  Sylvain Munaut 786919b165 build: Remove the -relut yosys option il y a 4 ans
  Sylvain Munaut 2a099c3c7e projects: Typo in the FTDI helper python code il y a 4 ans
  Sylvain Munaut 543fbcd58f cores/hyperram: Remove nextpnr place script il y a 4 ans
  Sylvain Munaut 4cb8155dc1 projects/memtest: Import memory tester project il y a 4 ans
  Sylvain Munaut 5554f72a7d cores/hyperram: Initial import of HyperRAM controller il y a 5 ans
  Sylvain Munaut 356169ba87 cores/qspi_master: Initial import of QSPI master controller il y a 4 ans
  Sylvain Munaut 890eddb66d cores/video: Add new HDMI 4x PHY using new ice40 serdes blocks il y a 4 ans