Commit History

Author SHA1 Message Date
  Sylvain Munaut f147c005db cores/e1: Minor synth improvement on CRC core 5 years ago
  Sylvain Munaut 21300d8cfe cores/e1: Fix CRC error marker in BD out fifo 5 years ago
  Sylvain Munaut f8b05c3630 cores/e1: Still generate TS0 pattern in case of underruns. 5 years ago
  Sylvain Munaut e51318fa05 cores/e1: Export tick for TX and RX path 5 years ago
  Sylvain Munaut 96e0348be9 cores/e1: Import register level documentation 5 years ago
  Sylvain Munaut effdabf3cd cores/e1: Import E1 core 5 years ago
  Sylvain Munaut 12891bcfc7 projects/memtest: Add missing PCF file for icebreaker 4 years ago
  Sylvain Munaut 3e030f46ee cores/qspi_master: Prevent yosys from using a bram for 16-element ROM 4 years ago
  Sylvain Munaut 5c5570cd71 cores/qspi_master: Fix port type 'reg' vs 'wire' for phy_io_i 4 years ago
  Sylvain Munaut 786919b165 build: Remove the -relut yosys option 4 years ago
  Sylvain Munaut 2a099c3c7e projects: Typo in the FTDI helper python code 4 years ago
  Sylvain Munaut 543fbcd58f cores/hyperram: Remove nextpnr place script 4 years ago
  Sylvain Munaut 4cb8155dc1 projects/memtest: Import memory tester project 4 years ago
  Sylvain Munaut 5554f72a7d cores/hyperram: Initial import of HyperRAM controller 4 years ago
  Sylvain Munaut 356169ba87 cores/qspi_master: Initial import of QSPI master controller 4 years ago
  Sylvain Munaut 890eddb66d cores/video: Add new HDMI 4x PHY using new ice40 serdes blocks 4 years ago
  Sylvain Munaut caf64670e2 cores/ice40: Add support for SERDES sync signal local buffer 4 years ago
  Sylvain Munaut 1827bf2ea3 cores/ice40: Add the ice40 4x SERDES cores 4 years ago
  Sylvain Munaut f8d8427821 cores/ice40: Import architecture specific utility cores 4 years ago
  Sylvain Munaut 60215a80e3 build: Disable some of the iverilog warnings 4 years ago
  Sylvain Munaut 5699d72cdc misc: Fix vim modeline in header to be at the top 4 years ago
  Sylvain Munaut f9707a2ae5 cores/usb: Minor documentation syntax fixes in markdown 4 years ago
  Sylvain Munaut c9a5068c7d projects/riscv_usb: Cleanup some unused wires 5 years ago
  Sylvain Munaut f560755b26 projects/riscv_usb: Add support for the user button 5 years ago
  Sylvain Munaut 779f6ae324 projects/riscv_usb: Minor syntax fixes for iverilog 5 years ago
  Sylvain Munaut ab62a9762e projects/boot_stub: Add a re-arm delay between selection button presses 5 years ago
  Sylvain Munaut e1790c8ed2 projects/boot_stub: Import a multi-boot stub bitstream 5 years ago
  Sylvain Munaut 3666c9f720 cores/usb: Add value init to decoded symbol in RX path (for sim only) 4 years ago
  Sylvain Munaut fc989e8582 cores/usb: Capture CEL state at transaction start 5 years ago
  Sylvain Munaut 6e61f6f19c cores/usb: Improve CRC implementation/synthesis 5 years ago