 Jakub Duchniewicz
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21cf6ac2bb
More outlining.
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15 hodín pred |
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Jakub Duchniewicz
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762321e7b8
Port most register management code.
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17 hodín pred |
 Krzysztof Skrzynecki
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2ba5998af1
freq increase voodoo
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17 hodín pred |
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Jakub Duchniewicz
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827f19c8b2
Distinguish between two kinds of mailboxes RTL2SW and SW2RTL.
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1 deň pred |
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Jakub Duchniewicz
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30e995fcc2
Add timer expiring in SW.
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4 dní pred |
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Jakub Duchniewicz
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a09fa0b998
Add Button mailbox. Start implementing SW btn handling logic.
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4 dní pred |
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Krzysztof Skrzynecki
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a310b26df0
add initial version of button logic + dummy usage
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5 dní pred |
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Jakub Duchniewicz
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98f63f9b8c
Cleanup WB addressing.
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1 týždeň pred |
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Jakub Duchniewicz
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816e22617b
Adapt SW to RTL changes.
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1 týždeň pred |
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Jakub Duchniewicz
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254d9836e4
Fix mailbox by introducing intermediate buffer for storing and saving.
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1 týždeň pred |
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Krzysztof Skrzynecki
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773483ddac
faster clocks for synthesis (not changing actual freq)
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1 týždeň pred |
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Krzysztof Skrzynecki
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dc69ed9423
replace 3 signal with temporary and incomplete (but fast) version
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1 týždeň pred |
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Krzysztof Skrzynecki
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a1e67cfd04
remove USB from deps
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2 týždňov pred |
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Jakub Duchniewicz
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6fdb3ab5aa
Fix erroneous word addressing and bring back byte addressing of mailbox. Registers now work.
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2 týždňov pred |
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Jakub Duchniewicz
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b7d87eaa5a
Fix bridging logic. Hangups are gone. Wrong offset in register map still persits.
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2 týždňov pred |
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Jakub Duchniewicz
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03fbd5a395
Approach fixing the overlapped mailbox registers with code and bootloader.
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2 týždňov pred |
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Jakub Duchniewicz
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561a0dfbd0
Add ability to flash LEDs over Wishbone on RTL side.
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3 týždňov pred |
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Jakub Duchniewicz
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20b5151657
Increase the internal registers to 32 bits for WB compatibility.
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3 týždňov pred |
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Jakub Duchniewicz
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2c6636d5b7
Reduce WB_N to 7 as for 8 it stopped instantiating CPU.
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3 týždňov pred |
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Jakub Duchniewicz
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ea6ad5f013
Flatten the mailbox registers.
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3 týždňov pred |
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Jakub Duchniewicz
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c44a5464d7
Add mailbox for RTL/SW communication.
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3 týždňov pred |
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Jakub Duchniewicz
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bab520e2fd
Add patches to submodules.
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3 týždňov pred |
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Jakub Duchniewicz
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bc60e00b90
Port 3signal code and integrate to the top module.
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3 týždňov pred |
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Jakub Duchniewicz
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888981826f
Transition to riscv_usb as base for out project.
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3 týždňov pred |
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Jakub Duchniewicz
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c86d575958
Add hardcoded LEDs and buttons.
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3 týždňov pred |
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Krzysztof Skrzynecki
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f780f6be9f
add led example
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1 mesiac pred |
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Jakub Duchniewicz
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043437ff45
Add binaries for KS.
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1 mesiac pred |
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Jakub Duchniewicz
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9d5c85cf64
My changes for debug UART and removing specs=nano.
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1 mesiac pred |
 Sylvain Munaut
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d2fa005012
projects/usb_amr/sw: Import a small python3 test class for DLM interface
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1 rok pred |
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Sylvain Munaut
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a61abc34fe
projects/usb_amr/fw: Init MC97 from the start
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1 rok pred |
