 Sylvain Munaut
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60215a80e3
build: Disable some of the iverilog warnings
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4 years ago |
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Sylvain Munaut
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4812ab7b22
build: Add explicit include directory for the rtl/ & sim/ dir of each core
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6 years ago |
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Sylvain Munaut
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66218b042e
build: Use the 'library' mode of iverilog for non-top-level files
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6 years ago |
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Sylvain Munaut
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b90e522d72
build: Allow 'simulation sources' in cores and projects
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6 years ago |
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Sylvain Munaut
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74fb15fae5
build: Fix dependency loop cause by phony targets
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6 years ago |
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Sylvain Munaut
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e2c6a58101
Initial import of the structure and build system
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6 years ago |
