 Sylvain Munaut
|
668a2e3606
build: Update build logic to prepare for split and out-of-tree build
|
4 years ago |
|
Sylvain Munaut
|
7e3d71c421
build: Use "relative" path for the include of all the deps
|
4 years ago |
|
Sylvain Munaut
|
acbdbcccd3
projects/riscv_usb: Add Makefile target to program app via DFU
|
5 years ago |
|
Sylvain Munaut
|
786919b165
build: Remove the -relut yosys option
|
4 years ago |
|
Sylvain Munaut
|
60215a80e3
build: Disable some of the iverilog warnings
|
4 years ago |
|
Sylvain Munaut
|
f33e481214
build: When creating verilog define for board name, replace - with _
|
5 years ago |
 Tobias Müller
|
ab0c2b9772
build: Use IVERILOG variable when building simulation
|
5 years ago |
|
Sylvain Munaut
|
015dea82ef
build: Define symbol matching the board config being built
|
6 years ago |
|
Sylvain Munaut
|
7d9adc485f
build: Update HeAP placer option name to the final merged version
|
6 years ago |
|
Sylvain Munaut
|
67dd460953
build: Add option to use the nea HeAP placer
|
6 years ago |
|
Sylvain Munaut
|
4812ab7b22
build: Add explicit include directory for the rtl/ & sim/ dir of each core
|
6 years ago |
|
Sylvain Munaut
|
66218b042e
build: Use the 'library' mode of iverilog for non-top-level files
|
6 years ago |
|
Sylvain Munaut
|
b90e522d72
build: Allow 'simulation sources' in cores and projects
|
6 years ago |
|
Sylvain Munaut
|
74fb15fae5
build: Fix dependency loop cause by phony targets
|
6 years ago |
|
Sylvain Munaut
|
e2c6a58101
Initial import of the structure and build system
|
6 years ago |
