Historique des commits

Auteur SHA1 Message Date
  Sylvain Munaut 67143eeaae projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0 il y a 4 ans
  Sylvain Munaut cb358304ff projects/riscv_usb: Adapt to allow 64k/128k of SPRAM il y a 5 ans
  Sylvain Munaut 779f6ae324 projects/riscv_usb: Minor syntax fixes for iverilog il y a 5 ans
  Sylvain Munaut b9622164c0 projects/riscv_usb: Add optional register stages in PicoRV -> WB bridge il y a 5 ans
  Sylvain Munaut 6f6311c8fb projects/riscv_usb: Add support for write mask to WB bus il y a 5 ans
  Sylvain Munaut 9cf400b9ad projects/riscv_usb: Import RISCV + USB prototype il y a 6 ans