Commit History

Autor SHA1 Mensaxe Data
  Sylvain Munaut 67143eeaae projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0 %!s(int64=4) %!d(string=hai) anos
  Sylvain Munaut cb358304ff projects/riscv_usb: Adapt to allow 64k/128k of SPRAM %!s(int64=5) %!d(string=hai) anos
  Sylvain Munaut 779f6ae324 projects/riscv_usb: Minor syntax fixes for iverilog %!s(int64=5) %!d(string=hai) anos
  Sylvain Munaut b9622164c0 projects/riscv_usb: Add optional register stages in PicoRV -> WB bridge %!s(int64=5) %!d(string=hai) anos
  Sylvain Munaut 6f6311c8fb projects/riscv_usb: Add support for write mask to WB bus %!s(int64=5) %!d(string=hai) anos
  Sylvain Munaut 9cf400b9ad projects/riscv_usb: Import RISCV + USB prototype %!s(int64=6) %!d(string=hai) anos