 Sylvain Munaut
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67143eeaae
projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0
|
il y a 4 ans |
|
Sylvain Munaut
|
4f3b887149
Update all no2xxx submodules and adapt as needed to new APIs
|
il y a 4 ans |
|
Sylvain Munaut
|
64cb6025b0
projects/riscv_usb: Update no2usb core and adapt to new API
|
il y a 4 ans |
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Sylvain Munaut
|
3038fcadf6
projects/riscv_usb: Remove some board support
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il y a 4 ans |
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Sylvain Munaut
|
1a0f4858e8
projects/riscv_usb: Remove all DFU bootloader code
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il y a 4 ans |
|
Sylvain Munaut
|
cef5cb69fa
projects/riscv_usb: Add support for e1tracer,ice1usb,icepick boards
|
il y a 4 ans |
|
Sylvain Munaut
|
cb358304ff
projects/riscv_usb: Adapt to allow 64k/128k of SPRAM
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il y a 5 ans |
|
Sylvain Munaut
|
c9a5068c7d
projects/riscv_usb: Cleanup some unused wires
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il y a 5 ans |
|
Sylvain Munaut
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f560755b26
projects/riscv_usb: Add support for the user button
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il y a 5 ans |
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Sylvain Munaut
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779f6ae324
projects/riscv_usb: Minor syntax fixes for iverilog
|
il y a 5 ans |
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Sylvain Munaut
|
a63af0df5f
projects/riscv_usb: Fix bus access to WARMBOOT
|
il y a 5 ans |
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Sylvain Munaut
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4fe4a453e8
projects/riscv_usb: Add WARMBOOT support
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il y a 5 ans |
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Sylvain Munaut
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6f6311c8fb
projects/riscv_usb: Add support for write mask to WB bus
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il y a 5 ans |
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Sylvain Munaut
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19946330f7
cores/usb: Add brief documentation for the microcode op codes
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il y a 5 ans |
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Sylvain Munaut
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9cf400b9ad
projects/riscv_usb: Import RISCV + USB prototype
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il y a 6 ans |
