jduchniewicz/doom_riscv

作者	SHA1 备注	提交日期
Sylvain Munaut	4812ab7b22 build: Add explicit include directory for the rtl/ & sim/ dir of each core	6 年之前
Sylvain Munaut	66218b042e build: Use the 'library' mode of iverilog for non-top-level files	6 年之前
Sylvain Munaut	b90e522d72 build: Allow 'simulation sources' in cores and projects	6 年之前
Sylvain Munaut	74fb15fae5 build: Fix dependency loop cause by phony targets	6 年之前
Sylvain Munaut	e2c6a58101 Initial import of the structure and build system	6 年之前