Cronologia Commit

Autore SHA1 Messaggio Data
  Jakub Duchniewicz 762321e7b8 Port most register management code. 18 ore fa
  Krzysztof Skrzynecki 2ba5998af1 freq increase voodoo 18 ore fa
  Jakub Duchniewicz 827f19c8b2 Distinguish between two kinds of mailboxes RTL2SW and SW2RTL. 1 giorno fa
  Jakub Duchniewicz 30e995fcc2 Add timer expiring in SW. 4 giorni fa
  Jakub Duchniewicz a09fa0b998 Add Button mailbox. Start implementing SW btn handling logic. 4 giorni fa
  Krzysztof Skrzynecki a310b26df0 add initial version of button logic + dummy usage 5 giorni fa
  Jakub Duchniewicz 98f63f9b8c Cleanup WB addressing. 1 settimana fa
  Jakub Duchniewicz 816e22617b Adapt SW to RTL changes. 1 settimana fa
  Jakub Duchniewicz 254d9836e4 Fix mailbox by introducing intermediate buffer for storing and saving. 1 settimana fa
  Krzysztof Skrzynecki 773483ddac faster clocks for synthesis (not changing actual freq) 1 settimana fa
  Krzysztof Skrzynecki dc69ed9423 replace 3 signal with temporary and incomplete (but fast) version 1 settimana fa
  Krzysztof Skrzynecki a1e67cfd04 remove USB from deps 2 settimane fa
  Jakub Duchniewicz 6fdb3ab5aa Fix erroneous word addressing and bring back byte addressing of mailbox. Registers now work. 2 settimane fa
  Jakub Duchniewicz b7d87eaa5a Fix bridging logic. Hangups are gone. Wrong offset in register map still persits. 2 settimane fa
  Jakub Duchniewicz 03fbd5a395 Approach fixing the overlapped mailbox registers with code and bootloader. 2 settimane fa
  Jakub Duchniewicz 561a0dfbd0 Add ability to flash LEDs over Wishbone on RTL side. 3 settimane fa
  Jakub Duchniewicz 20b5151657 Increase the internal registers to 32 bits for WB compatibility. 3 settimane fa
  Jakub Duchniewicz 2c6636d5b7 Reduce WB_N to 7 as for 8 it stopped instantiating CPU. 3 settimane fa
  Jakub Duchniewicz ea6ad5f013 Flatten the mailbox registers. 3 settimane fa
  Jakub Duchniewicz c44a5464d7 Add mailbox for RTL/SW communication. 3 settimane fa
  Jakub Duchniewicz bab520e2fd Add patches to submodules. 3 settimane fa
  Jakub Duchniewicz bc60e00b90 Port 3signal code and integrate to the top module. 3 settimane fa
  Jakub Duchniewicz 888981826f Transition to riscv_usb as base for out project. 3 settimane fa
  Jakub Duchniewicz c86d575958 Add hardcoded LEDs and buttons. 3 settimane fa
  Krzysztof Skrzynecki f780f6be9f add led example 1 mese fa
  Jakub Duchniewicz 043437ff45 Add binaries for KS. 1 mese fa
  Jakub Duchniewicz 9d5c85cf64 My changes for debug UART and removing specs=nano. 1 mese fa
  Sylvain Munaut d2fa005012 projects/usb_amr/sw: Import a small python3 test class for DLM interface 1 anno fa
  Sylvain Munaut a61abc34fe projects/usb_amr/fw: Init MC97 from the start 1 anno fa
  Sylvain Munaut fccbc539d7 projects/usb_amr/fw: Add an option to manually generate test ring 1 anno fa