 Sylvain Munaut
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fc12f0de48
projects/riscv_usb: Move the USB stuff to a separate module
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пре 4 година |
|
Sylvain Munaut
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2364fe15f4
projects/riscv_usb: Make use of ice40_spi_wb and ice40_rgb_wb
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пре 4 година |
|
Sylvain Munaut
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3c3ec85df7
projects/riscv_usb: Reformat UART peripheral instance
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пре 4 година |
|
Sylvain Munaut
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15e1fb5516
projects/riscv_usb: Isolate CPU / Bridge / Memory into sub module
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пре 4 година |
|
Sylvain Munaut
|
6480c5c26b
projects/riscv_usb: Rename bridge to soc_picorv32_bridge + WS fixes
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пре 4 година |
|
Sylvain Munaut
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67143eeaae
projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0
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пре 4 година |
|
Sylvain Munaut
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4f3b887149
Update all no2xxx submodules and adapt as needed to new APIs
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пре 4 година |
|
Sylvain Munaut
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64cb6025b0
projects/riscv_usb: Update no2usb core and adapt to new API
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пре 4 година |
|
Sylvain Munaut
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3038fcadf6
projects/riscv_usb: Remove some board support
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пре 4 година |
|
Sylvain Munaut
|
1a0f4858e8
projects/riscv_usb: Remove all DFU bootloader code
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пре 4 година |
|
Sylvain Munaut
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cef5cb69fa
projects/riscv_usb: Add support for e1tracer,ice1usb,icepick boards
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пре 4 година |
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Sylvain Munaut
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cb358304ff
projects/riscv_usb: Adapt to allow 64k/128k of SPRAM
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пре 4 година |
|
Sylvain Munaut
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c9a5068c7d
projects/riscv_usb: Cleanup some unused wires
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пре 5 година |
|
Sylvain Munaut
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f560755b26
projects/riscv_usb: Add support for the user button
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пре 5 година |
|
Sylvain Munaut
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779f6ae324
projects/riscv_usb: Minor syntax fixes for iverilog
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пре 5 година |
|
Sylvain Munaut
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a63af0df5f
projects/riscv_usb: Fix bus access to WARMBOOT
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пре 5 година |
|
Sylvain Munaut
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4fe4a453e8
projects/riscv_usb: Add WARMBOOT support
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пре 5 година |
|
Sylvain Munaut
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6f6311c8fb
projects/riscv_usb: Add support for write mask to WB bus
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пре 5 година |
|
Sylvain Munaut
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19946330f7
cores/usb: Add brief documentation for the microcode op codes
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пре 5 година |
|
Sylvain Munaut
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9cf400b9ad
projects/riscv_usb: Import RISCV + USB prototype
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пре 5 година |
