 Krzysztof Skrzynecki
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a1e67cfd04
remove USB from deps
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2 weeks ago |
 Jakub Duchniewicz
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6fdb3ab5aa
Fix erroneous word addressing and bring back byte addressing of mailbox. Registers now work.
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2 weeks ago |
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Jakub Duchniewicz
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b7d87eaa5a
Fix bridging logic. Hangups are gone. Wrong offset in register map still persits.
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2 weeks ago |
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Jakub Duchniewicz
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03fbd5a395
Approach fixing the overlapped mailbox registers with code and bootloader.
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2 weeks ago |
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Jakub Duchniewicz
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561a0dfbd0
Add ability to flash LEDs over Wishbone on RTL side.
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3 weeks ago |
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Jakub Duchniewicz
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2c6636d5b7
Reduce WB_N to 7 as for 8 it stopped instantiating CPU.
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3 weeks ago |
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Jakub Duchniewicz
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ea6ad5f013
Flatten the mailbox registers.
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3 weeks ago |
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Jakub Duchniewicz
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c44a5464d7
Add mailbox for RTL/SW communication.
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3 weeks ago |
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Jakub Duchniewicz
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bc60e00b90
Port 3signal code and integrate to the top module.
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3 weeks ago |
 Sylvain Munaut
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fc12f0de48
projects/riscv_usb: Move the USB stuff to a separate module
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4 years ago |
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Sylvain Munaut
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2364fe15f4
projects/riscv_usb: Make use of ice40_spi_wb and ice40_rgb_wb
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4 years ago |
|
Sylvain Munaut
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3c3ec85df7
projects/riscv_usb: Reformat UART peripheral instance
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4 years ago |
|
Sylvain Munaut
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15e1fb5516
projects/riscv_usb: Isolate CPU / Bridge / Memory into sub module
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4 years ago |
|
Sylvain Munaut
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6480c5c26b
projects/riscv_usb: Rename bridge to soc_picorv32_bridge + WS fixes
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4 years ago |
|
Sylvain Munaut
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67143eeaae
projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0
|
4 years ago |
|
Sylvain Munaut
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4f3b887149
Update all no2xxx submodules and adapt as needed to new APIs
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4 years ago |
|
Sylvain Munaut
|
64cb6025b0
projects/riscv_usb: Update no2usb core and adapt to new API
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4 years ago |
|
Sylvain Munaut
|
3038fcadf6
projects/riscv_usb: Remove some board support
|
4 years ago |
|
Sylvain Munaut
|
1a0f4858e8
projects/riscv_usb: Remove all DFU bootloader code
|
4 years ago |
|
Sylvain Munaut
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cef5cb69fa
projects/riscv_usb: Add support for e1tracer,ice1usb,icepick boards
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4 years ago |
|
Sylvain Munaut
|
cb358304ff
projects/riscv_usb: Adapt to allow 64k/128k of SPRAM
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4 years ago |
|
Sylvain Munaut
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c9a5068c7d
projects/riscv_usb: Cleanup some unused wires
|
5 years ago |
|
Sylvain Munaut
|
f560755b26
projects/riscv_usb: Add support for the user button
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5 years ago |
|
Sylvain Munaut
|
779f6ae324
projects/riscv_usb: Minor syntax fixes for iverilog
|
5 years ago |
|
Sylvain Munaut
|
a63af0df5f
projects/riscv_usb: Fix bus access to WARMBOOT
|
5 years ago |
|
Sylvain Munaut
|
4fe4a453e8
projects/riscv_usb: Add WARMBOOT support
|
5 years ago |
|
Sylvain Munaut
|
6f6311c8fb
projects/riscv_usb: Add support for write mask to WB bus
|
5 years ago |
|
Sylvain Munaut
|
19946330f7
cores/usb: Add brief documentation for the microcode op codes
|
5 years ago |
|
Sylvain Munaut
|
9cf400b9ad
projects/riscv_usb: Import RISCV + USB prototype
|
5 years ago |
