 Krzysztof Skrzynecki
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a310b26df0
add initial version of button logic + dummy usage
|
hai 6 días |
 Jakub Duchniewicz
|
98f63f9b8c
Cleanup WB addressing.
|
hai 1 semana |
|
Jakub Duchniewicz
|
816e22617b
Adapt SW to RTL changes.
|
hai 1 semana |
|
Krzysztof Skrzynecki
|
dc69ed9423
replace 3 signal with temporary and incomplete (but fast) version
|
hai 1 semana |
|
Krzysztof Skrzynecki
|
a1e67cfd04
remove USB from deps
|
hai 2 semanas |
|
Jakub Duchniewicz
|
6fdb3ab5aa
Fix erroneous word addressing and bring back byte addressing of mailbox. Registers now work.
|
hai 2 semanas |
|
Jakub Duchniewicz
|
b7d87eaa5a
Fix bridging logic. Hangups are gone. Wrong offset in register map still persits.
|
hai 2 semanas |
|
Jakub Duchniewicz
|
03fbd5a395
Approach fixing the overlapped mailbox registers with code and bootloader.
|
hai 2 semanas |
|
Jakub Duchniewicz
|
561a0dfbd0
Add ability to flash LEDs over Wishbone on RTL side.
|
hai 3 semanas |
|
Jakub Duchniewicz
|
2c6636d5b7
Reduce WB_N to 7 as for 8 it stopped instantiating CPU.
|
hai 3 semanas |
|
Jakub Duchniewicz
|
ea6ad5f013
Flatten the mailbox registers.
|
hai 3 semanas |
|
Jakub Duchniewicz
|
c44a5464d7
Add mailbox for RTL/SW communication.
|
hai 3 semanas |
|
Jakub Duchniewicz
|
bc60e00b90
Port 3signal code and integrate to the top module.
|
hai 3 semanas |
 Sylvain Munaut
|
fc12f0de48
projects/riscv_usb: Move the USB stuff to a separate module
|
%!s(int64=4) %!d(string=hai) anos |
|
Sylvain Munaut
|
2364fe15f4
projects/riscv_usb: Make use of ice40_spi_wb and ice40_rgb_wb
|
%!s(int64=4) %!d(string=hai) anos |
|
Sylvain Munaut
|
3c3ec85df7
projects/riscv_usb: Reformat UART peripheral instance
|
%!s(int64=4) %!d(string=hai) anos |
|
Sylvain Munaut
|
15e1fb5516
projects/riscv_usb: Isolate CPU / Bridge / Memory into sub module
|
%!s(int64=4) %!d(string=hai) anos |
|
Sylvain Munaut
|
6480c5c26b
projects/riscv_usb: Rename bridge to soc_picorv32_bridge + WS fixes
|
%!s(int64=4) %!d(string=hai) anos |
|
Sylvain Munaut
|
67143eeaae
projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0
|
%!s(int64=4) %!d(string=hai) anos |
|
Sylvain Munaut
|
4f3b887149
Update all no2xxx submodules and adapt as needed to new APIs
|
%!s(int64=4) %!d(string=hai) anos |
|
Sylvain Munaut
|
64cb6025b0
projects/riscv_usb: Update no2usb core and adapt to new API
|
%!s(int64=4) %!d(string=hai) anos |
|
Sylvain Munaut
|
3038fcadf6
projects/riscv_usb: Remove some board support
|
%!s(int64=4) %!d(string=hai) anos |
|
Sylvain Munaut
|
1a0f4858e8
projects/riscv_usb: Remove all DFU bootloader code
|
%!s(int64=4) %!d(string=hai) anos |
|
Sylvain Munaut
|
cef5cb69fa
projects/riscv_usb: Add support for e1tracer,ice1usb,icepick boards
|
%!s(int64=4) %!d(string=hai) anos |
|
Sylvain Munaut
|
cb358304ff
projects/riscv_usb: Adapt to allow 64k/128k of SPRAM
|
%!s(int64=4) %!d(string=hai) anos |
|
Sylvain Munaut
|
c9a5068c7d
projects/riscv_usb: Cleanup some unused wires
|
%!s(int64=5) %!d(string=hai) anos |
|
Sylvain Munaut
|
f560755b26
projects/riscv_usb: Add support for the user button
|
%!s(int64=5) %!d(string=hai) anos |
|
Sylvain Munaut
|
779f6ae324
projects/riscv_usb: Minor syntax fixes for iverilog
|
%!s(int64=5) %!d(string=hai) anos |
|
Sylvain Munaut
|
a63af0df5f
projects/riscv_usb: Fix bus access to WARMBOOT
|
%!s(int64=5) %!d(string=hai) anos |
|
Sylvain Munaut
|
4fe4a453e8
projects/riscv_usb: Add WARMBOOT support
|
%!s(int64=5) %!d(string=hai) anos |
