 Sylvain Munaut
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1d57cbe16f
projects/boot_stub: Add support for special Vio feature of some board
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4 years ago |
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Sylvain Munaut
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4aafd09833
projects/boot_stub: Add support for a few other boards
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4 years ago |
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Sylvain Munaut
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c22180302c
projects/boot_stub: Make a lot of things optional / board dependent
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4 years ago |
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Sylvain Munaut
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8027676f21
projects/boot_stub: Use HF_OSC as clock source
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4 years ago |
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Sylvain Munaut
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1cdde8f8ea
projects/boot_stub: Add target to easily build bootloader
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4 years ago |
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Sylvain Munaut
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8b0bebfde2
projects/riscv_usb: Add custom vendor commands in DFU firmware
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5 years ago |
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Sylvain Munaut
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acbdbcccd3
projects/riscv_usb: Add Makefile target to program app via DFU
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5 years ago |
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Sylvain Munaut
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a3065f1629
projects/riscv_usb: Import DFU firmware
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5 years ago |
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Sylvain Munaut
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92c03a9355
projects/riscv_usb: Update Makefile with new bootcode targets
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5 years ago |
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Sylvain Munaut
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f69146d035
projects/riscv_usb: Update fw/ gitignore
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5 years ago |
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Sylvain Munaut
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8cc8acfb36
projects/riscv_usb: Complete overhaul of the USB stack
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5 years ago |
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Sylvain Munaut
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0eec262a74
projects/riscv_usb: Add nano.specs in the CFLAGS
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4 years ago |
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Sylvain Munaut
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cb358304ff
projects/riscv_usb: Adapt to allow 64k/128k of SPRAM
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4 years ago |
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Sylvain Munaut
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c80f0a9f67
cores/mem_cache: Improvement on the memory simulator
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4 years ago |
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Sylvain Munaut
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3bd5ca1a5f
cores/mem_cache: Initial import of iCE40 memory cache
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4 years ago |
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Sylvain Munaut
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7c7e120a84
projects: Update constraints for bitsy v0 and v1
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4 years ago |
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Sylvain Munaut
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c1483f3018
projects/riscv_usb: Update BOARD define for C source to match verilog one
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4 years ago |
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Sylvain Munaut
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c138c61984
cores/e1: Add option to use an external LIU instead of the iCE40 as PHY
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5 years ago |
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Sylvain Munaut
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f147c005db
cores/e1: Minor synth improvement on CRC core
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5 years ago |
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Sylvain Munaut
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21300d8cfe
cores/e1: Fix CRC error marker in BD out fifo
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5 years ago |
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Sylvain Munaut
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f8b05c3630
cores/e1: Still generate TS0 pattern in case of underruns.
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5 years ago |
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Sylvain Munaut
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e51318fa05
cores/e1: Export tick for TX and RX path
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5 years ago |
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Sylvain Munaut
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96e0348be9
cores/e1: Import register level documentation
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5 years ago |
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Sylvain Munaut
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effdabf3cd
cores/e1: Import E1 core
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5 years ago |
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Sylvain Munaut
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12891bcfc7
projects/memtest: Add missing PCF file for icebreaker
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4 years ago |
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Sylvain Munaut
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3e030f46ee
cores/qspi_master: Prevent yosys from using a bram for 16-element ROM
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4 years ago |
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Sylvain Munaut
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5c5570cd71
cores/qspi_master: Fix port type 'reg' vs 'wire' for phy_io_i
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4 years ago |
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Sylvain Munaut
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786919b165
build: Remove the -relut yosys option
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4 years ago |
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Sylvain Munaut
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2a099c3c7e
projects: Typo in the FTDI helper python code
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4 years ago |
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Sylvain Munaut
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543fbcd58f
cores/hyperram: Remove nextpnr place script
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4 years ago |
