 Sylvain Munaut
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acbdbcccd3
projects/riscv_usb: Add Makefile target to program app via DFU
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%!s(int64=5) %!d(string=hai) anos |
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Sylvain Munaut
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786919b165
build: Remove the -relut yosys option
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%!s(int64=4) %!d(string=hai) anos |
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Sylvain Munaut
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60215a80e3
build: Disable some of the iverilog warnings
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%!s(int64=4) %!d(string=hai) anos |
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Sylvain Munaut
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f33e481214
build: When creating verilog define for board name, replace - with _
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%!s(int64=5) %!d(string=hai) anos |
 Tobias Müller
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ab0c2b9772
build: Use IVERILOG variable when building simulation
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%!s(int64=5) %!d(string=hai) anos |
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Sylvain Munaut
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015dea82ef
build: Define symbol matching the board config being built
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%!s(int64=6) %!d(string=hai) anos |
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Sylvain Munaut
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7d9adc485f
build: Update HeAP placer option name to the final merged version
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%!s(int64=6) %!d(string=hai) anos |
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Sylvain Munaut
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67dd460953
build: Add option to use the nea HeAP placer
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%!s(int64=6) %!d(string=hai) anos |
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Sylvain Munaut
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4812ab7b22
build: Add explicit include directory for the rtl/ & sim/ dir of each core
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%!s(int64=6) %!d(string=hai) anos |
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Sylvain Munaut
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66218b042e
build: Use the 'library' mode of iverilog for non-top-level files
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%!s(int64=6) %!d(string=hai) anos |
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Sylvain Munaut
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b90e522d72
build: Allow 'simulation sources' in cores and projects
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%!s(int64=6) %!d(string=hai) anos |
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Sylvain Munaut
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74fb15fae5
build: Fix dependency loop cause by phony targets
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%!s(int64=6) %!d(string=hai) anos |
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Sylvain Munaut
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e2c6a58101
Initial import of the structure and build system
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%!s(int64=6) %!d(string=hai) anos |
