 Jakub Duchniewicz
|
bc60e00b90
Port 3signal code and integrate to the top module.
|
3 hete |
 Sylvain Munaut
|
fc12f0de48
projects/riscv_usb: Move the USB stuff to a separate module
|
4 éve |
|
Sylvain Munaut
|
2364fe15f4
projects/riscv_usb: Make use of ice40_spi_wb and ice40_rgb_wb
|
4 éve |
|
Sylvain Munaut
|
3c3ec85df7
projects/riscv_usb: Reformat UART peripheral instance
|
4 éve |
|
Sylvain Munaut
|
15e1fb5516
projects/riscv_usb: Isolate CPU / Bridge / Memory into sub module
|
4 éve |
|
Sylvain Munaut
|
6480c5c26b
projects/riscv_usb: Rename bridge to soc_picorv32_bridge + WS fixes
|
4 éve |
|
Sylvain Munaut
|
67143eeaae
projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0
|
4 éve |
|
Sylvain Munaut
|
4f3b887149
Update all no2xxx submodules and adapt as needed to new APIs
|
4 éve |
|
Sylvain Munaut
|
64cb6025b0
projects/riscv_usb: Update no2usb core and adapt to new API
|
4 éve |
|
Sylvain Munaut
|
3038fcadf6
projects/riscv_usb: Remove some board support
|
4 éve |
|
Sylvain Munaut
|
1a0f4858e8
projects/riscv_usb: Remove all DFU bootloader code
|
4 éve |
|
Sylvain Munaut
|
cef5cb69fa
projects/riscv_usb: Add support for e1tracer,ice1usb,icepick boards
|
4 éve |
|
Sylvain Munaut
|
cb358304ff
projects/riscv_usb: Adapt to allow 64k/128k of SPRAM
|
4 éve |
|
Sylvain Munaut
|
c9a5068c7d
projects/riscv_usb: Cleanup some unused wires
|
5 éve |
|
Sylvain Munaut
|
f560755b26
projects/riscv_usb: Add support for the user button
|
5 éve |
|
Sylvain Munaut
|
779f6ae324
projects/riscv_usb: Minor syntax fixes for iverilog
|
5 éve |
|
Sylvain Munaut
|
a63af0df5f
projects/riscv_usb: Fix bus access to WARMBOOT
|
5 éve |
|
Sylvain Munaut
|
4fe4a453e8
projects/riscv_usb: Add WARMBOOT support
|
5 éve |
|
Sylvain Munaut
|
6f6311c8fb
projects/riscv_usb: Add support for write mask to WB bus
|
5 éve |
|
Sylvain Munaut
|
19946330f7
cores/usb: Add brief documentation for the microcode op codes
|
5 éve |
|
Sylvain Munaut
|
9cf400b9ad
projects/riscv_usb: Import RISCV + USB prototype
|
5 éve |
