 Sylvain Munaut
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d48b63777c
projects/riscv_usb: Add missing () in constant init
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il y a 5 ans |
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Sylvain Munaut
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9e815d5bb4
projects/riscv_usb: Fixup command prompt
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il y a 5 ans |
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Sylvain Munaut
|
b9622164c0
projects/riscv_usb: Add optional register stages in PicoRV -> WB bridge
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il y a 5 ans |
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Sylvain Munaut
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6f6311c8fb
projects/riscv_usb: Add support for write mask to WB bus
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il y a 5 ans |
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Sylvain Munaut
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b8f69663c9
cores/usb: Fix microcode when waiting for a BCI Ack
|
il y a 5 ans |
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Sylvain Munaut
|
fe836cb2d0
cores/usb: Remove register in the CSR read data path
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il y a 5 ans |
|
Sylvain Munaut
|
bda118d74b
projects/riscv_usb: Major firmware rework/refactoring
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il y a 5 ans |
|
Sylvain Munaut
|
f6d2bbabfd
projects/riscv_usb: Fix UART divisor off-by-one
|
il y a 5 ans |
|
Sylvain Munaut
|
3fd3e6bec1
projects/riscv_usb: Improve firmware size by turning on LTO
|
il y a 5 ans |
|
Sylvain Munaut
|
d65510a81d
cores/usb: Output a Start-Of-Frame strobe
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il y a 5 ans |
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Sylvain Munaut
|
af7a3a57d6
cores/usb: Rework CSR mapping and way events are reported
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il y a 5 ans |
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Sylvain Munaut
|
644f89fb59
cores/usb: Minor cosmetic fix in documentation
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il y a 5 ans |
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Sylvain Munaut
|
b3c22011be
cores/usb: Remove the bus MSB matching
|
il y a 5 ans |
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Sylvain Munaut
|
19946330f7
cores/usb: Add brief documentation for the microcode op codes
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il y a 5 ans |
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Sylvain Munaut
|
5e7d05e3e7
cores/misc: Fix uart_wb handling of full fifo
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il y a 5 ans |
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Sylvain Munaut
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57373928b0
cores/misc: Import simple PDM core (pulse density modulation)
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il y a 5 ans |
|
Sylvain Munaut
|
015dea82ef
build: Define symbol matching the board config being built
|
il y a 6 ans |
|
Sylvain Munaut
|
9cf400b9ad
projects/riscv_usb: Import RISCV + USB prototype
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il y a 6 ans |
|
Sylvain Munaut
|
6b8188125c
cores/usb: Add debug option to the microcode compiler
|
il y a 6 ans |
|
Sylvain Munaut
|
5b63e8251c
cores/usb: Remove debug output
|
il y a 6 ans |
|
Sylvain Munaut
|
12d9e46ab0
cores/usb: Add Control Endpoint Lockout feature
|
il y a 6 ans |
|
Sylvain Munaut
|
5229fb7590
cores/usb: Add special buffer descriptor mode for control endpoint
|
il y a 6 ans |
|
Sylvain Munaut
|
ea06e6878b
cores/usb: Fix RX bit stuffing implementation
|
il y a 6 ans |
|
Sylvain Munaut
|
aff3b98e7a
cores/usb: Import current state of the USB core
|
il y a 6 ans |
|
Sylvain Munaut
|
2e0e25b76f
cores/misc: Add cross-clock wishbone interface
|
il y a 6 ans |
|
Sylvain Munaut
|
6067f61535
cores/misc: Add cross-clock strobe
|
il y a 6 ans |
|
Sylvain Munaut
|
22c3e9a4ee
cores/misc: Add UART with wishbone & FIFO
|
il y a 6 ans |
|
Sylvain Munaut
|
2ed6b32cf4
cores/misc: Add simple UART TX/RX cores
|
il y a 6 ans |
|
Sylvain Munaut
|
9e01a6a390
cores/video: Change the color lookup algo for direct mode
|
il y a 6 ans |
|
Sylvain Munaut
|
68ac87f6c4
Update the vim modeline to be closer to top of file
|
il y a 6 ans |
