Commit History

Author SHA1 Message Date
  Sylvain Munaut d16c23f949 cores/usb: Wait for TX complete before BD writeback in Isochronous IN 5 years ago
  Sylvain Munaut 0fb0de1636 cores/usb: Use proper JEQ mnemonic instead of JMP for conditional jumps 5 years ago
  Sylvain Munaut 96819677e9 projects/riscv_usb: Add rgb led color shuffle depending on board wiring 5 years ago
  Sylvain Munaut 8328f7f506 projects/riscv_usb: Add #define for board model during fw build 5 years ago
  Sylvain Munaut 48a989cc74 project/riscv_usb: Minor whitespace fixes 5 years ago
  Sylvain Munaut 66a84a317a projects/riscv_usb: Improve and add flash write support to the SPI driver 5 years ago
  Sylvain Munaut 6b77ba5809 projects/riscv_usb: Add better functions to access unique ID from flash 5 years ago
  Sylvain Munaut 315d7d170e projects/riscv_usb: Add support for the icebreaker-bitsy 5 years ago
  Sylvain Munaut f2a7d4b740 projects/riscv_usb: Update icebreaker PCF 5 years ago
  Sylvain Munaut 4fe4a453e8 projects/riscv_usb: Add WARMBOOT support 5 years ago
  Sylvain Munaut 8dce3431d4 cores/usb: Fix microcode for BCI OUT 5 years ago
  Sylvain Munaut 6c70dda8cb cores/usb: Minor typo fixes 5 years ago
  Sylvain Munaut defc053b38 cores/usb: Add address matching capability 5 years ago
  Sylvain Munaut 82324620f8 cores/usb: Documentation formatting fixes 5 years ago
  Sylvain Munaut ce0866d6f6 cores/usb: Expose Bus Reset/Suspend & SoF to the soft core 5 years ago
  Sylvain Munaut 7a644d54f3 cores/usb: Update tx testbench for bitstuffing border cases 5 years ago
  Sylvain Munaut a8ca29653c cores/usb: Fix bitstuffing in TX path for border line case 5 years ago
  Sylvain Munaut 8d8eee979f projects/riscv_usb: Add driver for the SPI IP 5 years ago
  Sylvain Munaut 594fd1d74e projects/riscv_usb: Add driver for the LED driver IP 5 years ago
  Sylvain Munaut d48b63777c projects/riscv_usb: Add missing () in constant init 5 years ago
  Sylvain Munaut 9e815d5bb4 projects/riscv_usb: Fixup command prompt 5 years ago
  Sylvain Munaut b9622164c0 projects/riscv_usb: Add optional register stages in PicoRV -> WB bridge 5 years ago
  Sylvain Munaut 6f6311c8fb projects/riscv_usb: Add support for write mask to WB bus 5 years ago
  Sylvain Munaut b8f69663c9 cores/usb: Fix microcode when waiting for a BCI Ack 5 years ago
  Sylvain Munaut fe836cb2d0 cores/usb: Remove register in the CSR read data path 5 years ago
  Sylvain Munaut bda118d74b projects/riscv_usb: Major firmware rework/refactoring 5 years ago
  Sylvain Munaut f6d2bbabfd projects/riscv_usb: Fix UART divisor off-by-one 5 years ago
  Sylvain Munaut 3fd3e6bec1 projects/riscv_usb: Improve firmware size by turning on LTO 5 years ago
  Sylvain Munaut d65510a81d cores/usb: Output a Start-Of-Frame strobe 5 years ago
  Sylvain Munaut af7a3a57d6 cores/usb: Rework CSR mapping and way events are reported 5 years ago