 Jakub Duchniewicz
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827f19c8b2
Distinguish between two kinds of mailboxes RTL2SW and SW2RTL.
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1 giorno fa |
 Krzysztof Skrzynecki
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a310b26df0
add initial version of button logic + dummy usage
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5 giorni fa |
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Krzysztof Skrzynecki
|
a1e67cfd04
remove USB from deps
|
2 settimane fa |
|
Jakub Duchniewicz
|
c44a5464d7
Add mailbox for RTL/SW communication.
|
3 settimane fa |
|
Jakub Duchniewicz
|
bc60e00b90
Port 3signal code and integrate to the top module.
|
3 settimane fa |
 Sylvain Munaut
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fc12f0de48
projects/riscv_usb: Move the USB stuff to a separate module
|
4 anni fa |
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Sylvain Munaut
|
15e1fb5516
projects/riscv_usb: Isolate CPU / Bridge / Memory into sub module
|
4 anni fa |
|
Sylvain Munaut
|
6480c5c26b
projects/riscv_usb: Rename bridge to soc_picorv32_bridge + WS fixes
|
4 anni fa |
|
Sylvain Munaut
|
345435957f
projects/riscv_usb: Add iCE40 specific implementation of register file
|
4 anni fa |
|
Sylvain Munaut
|
1a0f4858e8
projects/riscv_usb: Remove all DFU bootloader code
|
4 anni fa |
|
Sylvain Munaut
|
e3c30a06d3
cores/ice40: Rename 'ice40' to 'no2ice40' to prepare split
|
4 anni fa |
|
Sylvain Munaut
|
1289f6eefc
cores/misc: Rename 'misc' to 'no2misc' to prepare split
|
4 anni fa |
|
Sylvain Munaut
|
a6add64749
cores/usb: Rename core from 'usb' to 'no2usb'
|
4 anni fa |
|
Sylvain Munaut
|
92c03a9355
projects/riscv_usb: Update Makefile with new bootcode targets
|
5 anni fa |
|
Sylvain Munaut
|
cb358304ff
projects/riscv_usb: Adapt to allow 64k/128k of SPRAM
|
4 anni fa |
|
Sylvain Munaut
|
f560755b26
projects/riscv_usb: Add support for the user button
|
5 anni fa |
|
Sylvain Munaut
|
9cf400b9ad
projects/riscv_usb: Import RISCV + USB prototype
|
5 anni fa |
