projects/riscv_usb/fw/Makefile

@@ -19,6 +19,7 @@ HEADERS_common=\
 	mini-printf.h \
 	spi.h \
 	utils.h \
+	registers.h \
 	$(HEADERS_no2usb)
 
 SOURCES_common=\
@@ -28,6 +29,7 @@ SOURCES_common=\
 	mini-printf.c  \
 	spi.c \
 	utils.c \
+	registers.c \
 	$(SOURCES_no2usb)
 
 HEADERS_app=\

projects/riscv_usb/fw/config.h

@@ -28,3 +28,4 @@
 #define LED_BASE	0x83000000
 #define USB_CORE_BASE	0x84000000
 #define USB_DATA_BASE	0x85000000
+#define MAILBOX_BASE 0x86000000

projects/riscv_usb/fw/fw_app.c

@@ -32,6 +32,7 @@
 #include <no2usb/usb.h>
 #include <no2usb/usb_dfu_rt.h>
 #include "utils.h"
+#include "registers.h"
 
 
 extern const struct usb_stack_descriptors app_stack_desc;
@@ -49,6 +50,9 @@ serial_no_init()
 	flash_unique_id(buf);
 	printf("Flash Unique ID    : %s\n", hexstr(buf, 8, true));
 
+    // Print Mailbox contents just to be sure */
+    printf("Mailbox period1: %d\n", mailbox_regs->regs.period1);
+
 	/* Overwrite descriptor string */
 		/* In theory in rodata ... but nothing is ro here */
 	id = hexstr(buf, 8, false);
@@ -57,6 +61,27 @@ serial_no_init()
 		desc[2 + (i << 1)] = id[i];
 }
 
+static void write_period1()
+{
+    printf("Writing period1 0x1\n");
+    mailbox_regs->regs.period1 = 0x1;
+    printf("Done writing\n");
+}
+
+static void write_period1_2()
+{
+    printf("Writing period1 0x2\n");
+    mailbox_regs->regs.period1 = 0x2;
+    printf("Done writing\n");
+}
+
+static void clear_period1()
+{
+    printf("Clearing period1 current val: %d\n", mailbox_regs->regs.period1);
+    mailbox_regs->regs.period1 = 0x0;
+    printf("Done clearing\n");
+}
+
 static void
 boot_dfu(void)
 {
@@ -128,6 +153,15 @@ void main()
 			case 'd':
 				usb_disconnect();
 				break;
+            case 'w':
+                write_period1();
+                break;
+            case 'k':
+                clear_period1();
+                break;
+            case 'a':
+                write_period1_2();
+                break;
 			default:
 				break;
 			}

projects/riscv_usb/fw/registers.c

@@ -0,0 +1,4 @@
+
+#pragma once
+
+#include "registers.h"

projects/riscv_usb/fw/registers.h

@@ -0,0 +1,29 @@
+// TODO: add copyright
+//
+//
+
+#include <stdint.h>
+
+#include "config.h"
+
+typedef struct {
+    uint16_t period1;
+    uint16_t delay1;
+    uint16_t duty2;
+    uint16_t delay2;
+    uint16_t duty3;
+    uint16_t delay3;
+    uint16_t npuls3;
+    uint16_t odd_train_flag;
+    uint16_t ena_odd_out3;
+    uint64_t reserved;
+} three_signal_regs_t __attribute__((packed,aligned(4)));
+
+typedef struct {
+    union {
+        uint16_t data[16];
+        three_signal_regs_t regs;
+    };
+} wb_mailbox_regs_t __attribute__((packed,aligned(4)));
+
+static volatile wb_mailbox_regs_t * const mailbox_regs = (void*)(MAILBOX_BASE);

projects/riscv_usb/rtl/mailbox_wb.v

@@ -11,7 +11,7 @@
 
 module mailbox_wb #(
     parameter AW = 4,  // Address width for 16 registers (4 bits)
-    parameter DW = 16   // Data width for each register (16 bits)
+    parameter DW = 32   // Data width for the Wishbone interface (32 bits)
 )(
     input  wire             clk,
     input  wire             rst,
@@ -24,11 +24,11 @@ module mailbox_wb #(
     output reg              wb_ack,
 
     // Flattened custom hardware side (RTL)
-    output wire [DW*16-1:0] registers_flat  // Flattened register array (16 registers of 16 bits each)
+    output wire [16*DW-1:0]     registers_flat  // Flattened register array (16 registers of 16 bits each)
 );
 
-    // Internal registers (flattened version)
-    reg [DW-1:0] registers_array[15:0];  // 16 registers, each 16 bits wide
+    // Internal registers (16 registers, each 16 bits wide)
+    reg [15:0] registers_array[15:0];
 
     // Always reset the registers on reset signal
     integer i;
@@ -36,7 +36,7 @@ module mailbox_wb #(
         if (rst) begin
             wb_ack <= 1'b0;
             for (i = 0; i < 16; i = i + 1) begin
-                registers_array[i] <= {DW{1'b0}}; // Reset all registers to 0
+                registers_array[i] <= 16'h0; // Reset all registers to 0
             end
         end else begin
             // Handle Wishbone communication
@@ -45,44 +45,44 @@ module mailbox_wb #(
             // Write operation (if write enable is active)
             if (wb_we && wb_cyc) begin
                 case (wb_addr)
-                    4'b0000: registers_array[0] <= wb_wdata;
-                    4'b0001: registers_array[1] <= wb_wdata;
-                    4'b0010: registers_array[2] <= wb_wdata;
-                    4'b0011: registers_array[3] <= wb_wdata;
-                    4'b0100: registers_array[4] <= wb_wdata;
-                    4'b0101: registers_array[5] <= wb_wdata;
-                    4'b0110: registers_array[6] <= wb_wdata;
-                    4'b0111: registers_array[7] <= wb_wdata;
-                    4'b1000: registers_array[8] <= wb_wdata;
-                    4'b1001: registers_array[9] <= wb_wdata;
-                    4'b1010: registers_array[10] <= wb_wdata;
-                    4'b1011: registers_array[11] <= wb_wdata;
-                    4'b1100: registers_array[12] <= wb_wdata;
-                    4'b1101: registers_array[13] <= wb_wdata;
-                    4'b1110: registers_array[14] <= wb_wdata;
-                    4'b1111: registers_array[15] <= wb_wdata;
+                    4'b0000: registers_array[0] <= wb_wdata[15:0]; // Only use lower 16 bits
+                    4'b0001: registers_array[1] <= wb_wdata[15:0];
+                    4'b0010: registers_array[2] <= wb_wdata[15:0];
+                    4'b0011: registers_array[3] <= wb_wdata[15:0];
+                    4'b0100: registers_array[4] <= wb_wdata[15:0];
+                    4'b0101: registers_array[5] <= wb_wdata[15:0];
+                    4'b0110: registers_array[6] <= wb_wdata[15:0];
+                    4'b0111: registers_array[7] <= wb_wdata[15:0];
+                    4'b1000: registers_array[8] <= wb_wdata[15:0];
+                    4'b1001: registers_array[9] <= wb_wdata[15:0];
+                    4'b1010: registers_array[10] <= wb_wdata[15:0];
+                    4'b1011: registers_array[11] <= wb_wdata[15:0];
+                    4'b1100: registers_array[12] <= wb_wdata[15:0];
+                    4'b1101: registers_array[13] <= wb_wdata[15:0];
+                    4'b1110: registers_array[14] <= wb_wdata[15:0];
+                    4'b1111: registers_array[15] <= wb_wdata[15:0];
                 endcase
             end
 
             // Read operation (read the correct register based on address)
             case (wb_addr)
-                4'b0000: wb_rdata <= registers_array[0];
-                4'b0001: wb_rdata <= registers_array[1];
-                4'b0010: wb_rdata <= registers_array[2];
-                4'b0011: wb_rdata <= registers_array[3];
-                4'b0100: wb_rdata <= registers_array[4];
-                4'b0101: wb_rdata <= registers_array[5];
-                4'b0110: wb_rdata <= registers_array[6];
-                4'b0111: wb_rdata <= registers_array[7];
-                4'b1000: wb_rdata <= registers_array[8];
-                4'b1001: wb_rdata <= registers_array[9];
-                4'b1010: wb_rdata <= registers_array[10];
-                4'b1011: wb_rdata <= registers_array[11];
-                4'b1100: wb_rdata <= registers_array[12];
-                4'b1101: wb_rdata <= registers_array[13];
-                4'b1110: wb_rdata <= registers_array[14];
-                4'b1111: wb_rdata <= registers_array[15];
-                default: wb_rdata <= {DW{1'b0}}; // Default error value
+                4'b0000: wb_rdata <= {16'h0, registers_array[0]}; // Place 16-bit value in lower half of 32-bit bus
+                4'b0001: wb_rdata <= {16'h0, registers_array[1]};
+                4'b0010: wb_rdata <= {16'h0, registers_array[2]};
+                4'b0011: wb_rdata <= {16'h0, registers_array[3]};
+                4'b0100: wb_rdata <= {16'h0, registers_array[4]};
+                4'b0101: wb_rdata <= {16'h0, registers_array[5]};
+                4'b0110: wb_rdata <= {16'h0, registers_array[6]};
+                4'b0111: wb_rdata <= {16'h0, registers_array[7]};
+                4'b1000: wb_rdata <= {16'h0, registers_array[8]};
+                4'b1001: wb_rdata <= {16'h0, registers_array[9]};
+                4'b1010: wb_rdata <= {16'h0, registers_array[10]};
+                4'b1011: wb_rdata <= {16'h0, registers_array[11]};
+                4'b1100: wb_rdata <= {16'h0, registers_array[12]};
+                4'b1101: wb_rdata <= {16'h0, registers_array[13]};
+                4'b1110: wb_rdata <= {16'h0, registers_array[14]};
+                4'b1111: wb_rdata <= {16'h0, registers_array[15]};
+                default: wb_rdata <= 32'hDEAD_BEEF; // Default error value
             endcase
         end
     end
@@ -91,9 +91,8 @@ module mailbox_wb #(
     generate
         genvar j;
         for (j = 0; j < 16; j = j + 1) begin : flatten
-            assign registers_flat[DW*(j+1)-1:DW*j] = registers_array[j];
+            assign registers_flat[16*(j+1)-1:16*j] = registers_array[j];
         end
     endgenerate
 
 endmodule
-

projects/riscv_usb/rtl/top.v

@@ -99,7 +99,7 @@ module top (
     wire ena_odd_out3;
 
 	// Mailbox signal wires
-    wire [16*16-1:0] mailbox_regs_flat;  // Flattened register array (16 registers of 16 bits each)
+    wire [16*WB_DW-1:0] mailbox_regs_flat;  // Flattened register array (16 registers of 16 bits each)
 
 	// SoC
 	// ---
@@ -223,7 +223,7 @@ module top (
 	// ----------
 	mailbox_wb #(
 		.AW(4),
-		.DW(16)
+		.DW(32)
 	) mailbox_I (
 		.clk(clk_48m),
 		.rst(rst),
@@ -238,7 +238,7 @@ module top (
 
     // 3 Signal
     // --------
-    //assign period1 = mailbox_regs[0];
+    assign period1 = mailbox_regs_flat[15:0];
 	// TODO: rest of assignments
     //wire [SLOW_PWM_WIDTH-1:0] delay1;
     //wire [SLOW_PWM_WIDTH-1:0] duty2;
@@ -272,6 +272,22 @@ module top (
         .Out3(out3)
     );
 
+    // TODO: dummy led onoff when value has been written
+    always @(posedge clk_48m or posedge rst)
+        if (rst) begin
+            led[0] = 1'b0;
+            led[1] = 1'b0;
+        end else if (period1 == 1) begin
+            led[0] = 1'b1;
+            led[1] = 1'b0;
+        end else if (period1 == 2) begin
+            led[0] = 1'b0;
+            led[1] = 1'b1;
+        end else begin
+            led[0] = 1'b0;
+            led[1] = 1'b0;
+        end
+
 	// Warm Boot
 	// ---------