/----------------------------------------------------------------------------\
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |  Copyright (C) 2012 - 2024  Claire Xenia Wolf <claire@yosyshq.com>         |
 |  Distributed under an ISC-like license, type "license" to see terms        |
 \----------------------------------------------------------------------------/
 Yosys 0.43 (git sha1 ead4718e5, g++ 14.2.1 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -ffile-prefix-map=/build/yosys/src=/usr/src/debug/yosys -fPIC -Os)

-- Executing script file `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/build-tmp/riscv_doom.ys' --

1. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/top.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/top.v' to AST representation.
Generating RTLIL representation for module `\top'.
Successfully finished Verilog frontend.

2. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v' to AST representation.
Generating RTLIL representation for module `\ice40_ebr'.
Successfully finished Verilog frontend.

3. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_i2c_wb.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_i2c_wb.v' to AST representation.
Generating RTLIL representation for module `\ice40_i2c_wb'.
Successfully finished Verilog frontend.

4. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_rgb_wb.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_rgb_wb.v' to AST representation.
Generating RTLIL representation for module `\ice40_rgb_wb'.
Successfully finished Verilog frontend.

5. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spi_wb.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spi_wb.v' to AST representation.
Generating RTLIL representation for module `\ice40_spi_wb'.
Successfully finished Verilog frontend.

6. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v' to AST representation.
Generating RTLIL representation for module `\ice40_spram_gen'.
ice40_spram_gen: (      32768x         32) ->           2x          2 array of SPRAM

ice40_spram_gen: (      32768x         32) ->           2x          2 array of SPRAM

/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
Successfully finished Verilog frontend.

7. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_wb.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_wb.v' to AST representation.
Generating RTLIL representation for module `\ice40_spram_wb'.
Successfully finished Verilog frontend.

8. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v' to AST representation.
Generating RTLIL representation for module `\ice40_iserdes'.
Successfully finished Verilog frontend.

9. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_oserdes.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_oserdes.v' to AST representation.
Generating RTLIL representation for module `\ice40_oserdes'.
Successfully finished Verilog frontend.

10. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v' to AST representation.
Generating RTLIL representation for module `\ice40_serdes_crg'.
Successfully finished Verilog frontend.

11. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_dff.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_dff.v' to AST representation.
Generating RTLIL representation for module `\ice40_serdes_dff'.
Successfully finished Verilog frontend.

12. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_sync.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_sync.v' to AST representation.
Generating RTLIL representation for module `\ice40_serdes_sync'.
Successfully finished Verilog frontend.

13. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v' to AST representation.
Generating RTLIL representation for module `\mc_bus_vex'.
Successfully finished Verilog frontend.

14. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_wb.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_wb.v' to AST representation.
Generating RTLIL representation for module `\mc_bus_wb'.
Successfully finished Verilog frontend.

15. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v' to AST representation.
Generating RTLIL representation for module `\mc_core'.
Warning: Replacing memory \way_tag_we with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:446
Warning: Replacing memory \way_age_nxt with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:406
Warning: Replacing memory \way_dirty_we with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:377
Warning: Replacing memory \way_dirty_nxt with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:376
Warning: Replacing memory \way_valid_we with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:373
Warning: Replacing memory \way_valid_nxt with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:372
Memory cache config :
 -           4 ways
 -          64 kbytes cache
 -          64 bytes cache lines
 -          64 Mbytes address space
 -          12/          8/          4 address split
Memory cache config :
 -           4 ways
 -          64 kbytes cache
 -          64 bytes cache lines
 -          64 Mbytes address space
 -          12/          8/          4 address split
Successfully finished Verilog frontend.

16. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_match.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_match.v' to AST representation.
Generating RTLIL representation for module `\mc_tag_match'.
Successfully finished Verilog frontend.

17. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_ram.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_ram.v' to AST representation.
Generating RTLIL representation for module `\mc_tag_ram'.
Cache tag memory config,           1 x         256 x          16
Successfully finished Verilog frontend.

18. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v' to AST representation.
Generating RTLIL representation for module `\delay_bit'.
Generating RTLIL representation for module `\delay_bus'.
Warning: Replacing memory \dl with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:59
Generating RTLIL representation for module `\delay_toggle'.
Successfully finished Verilog frontend.

19. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v' to AST representation.
Generating RTLIL representation for module `\fifo_sync_ram'.
Successfully finished Verilog frontend.

20. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v' to AST representation.
Generating RTLIL representation for module `\fifo_sync_shift'.
Successfully finished Verilog frontend.

21. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v' to AST representation.
Generating RTLIL representation for module `\glitch_filter'.
Successfully finished Verilog frontend.

22. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/i2c_master.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/i2c_master.v' to AST representation.
Generating RTLIL representation for module `\i2c_master'.
Successfully finished Verilog frontend.

23. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/i2c_master_wb.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/i2c_master_wb.v' to AST representation.
Generating RTLIL representation for module `\i2c_master_wb'.
Successfully finished Verilog frontend.

24. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/muacm2wb.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/muacm2wb.v' to AST representation.
Generating RTLIL representation for module `\muacm2wb'.
Successfully finished Verilog frontend.

25. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/prims.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/prims.v' to AST representation.
Lexer warning: The SystemVerilog keyword `bit' (at /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/prims.v:31) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `bit' (at /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/prims.v:75) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `bit' (at /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/prims.v:117) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `bit' (at /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/prims.v:150) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `bit' (at /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/prims.v:186) is not recognized unless read_verilog is called with -sv!
Lexer warning: The SystemVerilog keyword `bit' (at /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/prims.v:237) is not recognized unless read_verilog is called with -sv!
Generating RTLIL representation for module `\lut4_n'.
Generating RTLIL representation for module `\lut4_carry_n'.
Generating RTLIL representation for module `\dff_n'.
Generating RTLIL representation for module `\dffe_n'.
Generating RTLIL representation for module `\dffer_n'.
Generating RTLIL representation for module `\dffesr_n'.
Successfully finished Verilog frontend.

26. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/pdm.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/pdm.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/pdm.v:91)
Generating RTLIL representation for module `\pdm'.
Generating RTLIL representation for module `\pdm_lfsr'.
Successfully finished Verilog frontend.

27. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/pwm.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/pwm.v' to AST representation.
Warning: Yosys has only limited support for tri-state logic at the moment. (/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/pwm.v:69)
Generating RTLIL representation for module `\pwm'.
Successfully finished Verilog frontend.

28. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v' to AST representation.
Generating RTLIL representation for module `\ram_sdp'.
Successfully finished Verilog frontend.

29. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/stream2wb.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/stream2wb.v' to AST representation.
Generating RTLIL representation for module `\stream2wb'.
Successfully finished Verilog frontend.

30. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart2wb.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart2wb.v' to AST representation.
Generating RTLIL representation for module `\uart2wb'.
Successfully finished Verilog frontend.

31. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v' to AST representation.
Generating RTLIL representation for module `\uart_rx'.
Successfully finished Verilog frontend.

32. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v' to AST representation.
Generating RTLIL representation for module `\uart_tx'.
Successfully finished Verilog frontend.

33. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v' to AST representation.
Generating RTLIL representation for module `\uart_wb'.
Successfully finished Verilog frontend.

34. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/xclk_strobe.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/xclk_strobe.v' to AST representation.
Generating RTLIL representation for module `\xclk_strobe'.
Successfully finished Verilog frontend.

35. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/xclk_wb.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/xclk_wb.v' to AST representation.
Generating RTLIL representation for module `\xclk_wb'.
Successfully finished Verilog frontend.

36. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v' to AST representation.
Generating RTLIL representation for module `\qpi_memctrl'.
Successfully finished Verilog frontend.

37. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_phy_ice40_1x.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_phy_ice40_1x.v' to AST representation.
Generating RTLIL representation for module `\qpi_phy_ice40_1x'.
Successfully finished Verilog frontend.

38. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_phy_ice40_2x.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_phy_ice40_2x.v' to AST representation.
Generating RTLIL representation for module `\qpi_phy_ice40_2x'.
Successfully finished Verilog frontend.

39. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_phy_ice40_4x.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_phy_ice40_4x.v' to AST representation.
Lexer warning: The SystemVerilog keyword `bit' (at /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_phy_ice40_4x.v:57) is not recognized unless read_verilog is called with -sv!
Generating RTLIL representation for module `\qpi_phy_ice40_4x'.
Successfully finished Verilog frontend.

40. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb.v' to AST representation.
Generating RTLIL representation for module `\usb'.
Successfully finished Verilog frontend.

41. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_crc.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_crc.v' to AST representation.
Generating RTLIL representation for module `\usb_crc'.
Successfully finished Verilog frontend.

42. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_ep_buf.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_ep_buf.v' to AST representation.
Generating RTLIL representation for module `\usb_ep_buf'.
READ_MODE  :           3
WRITE_MODE :           3
Successfully finished Verilog frontend.

43. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_ep_status.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_ep_status.v' to AST representation.
Generating RTLIL representation for module `\usb_ep_status'.
Successfully finished Verilog frontend.

44. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_phy.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_phy.v' to AST representation.
Generating RTLIL representation for module `\usb_phy'.
Successfully finished Verilog frontend.

45. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_rx_ll.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_rx_ll.v' to AST representation.
Generating RTLIL representation for module `\usb_rx_ll'.
Successfully finished Verilog frontend.

46. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_rx_pkt.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_rx_pkt.v' to AST representation.
Generating RTLIL representation for module `\usb_rx_pkt'.
Successfully finished Verilog frontend.

47. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_trans.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_trans.v' to AST representation.
Generating RTLIL representation for module `\usb_trans'.
Successfully finished Verilog frontend.

48. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_tx_ll.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_tx_ll.v' to AST representation.
Generating RTLIL representation for module `\usb_tx_ll'.
Successfully finished Verilog frontend.

49. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_tx_pkt.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2usb//rtl/usb_tx_pkt.v' to AST representation.
Generating RTLIL representation for module `\usb_tx_pkt'.
Successfully finished Verilog frontend.

50. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_phy_1x.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_phy_1x.v' to AST representation.
Generating RTLIL representation for module `\hdmi_phy_1x'.
Successfully finished Verilog frontend.

51. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_phy_2x.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_phy_2x.v' to AST representation.
Generating RTLIL representation for module `\hdmi_phy_2x'.
Successfully finished Verilog frontend.

52. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_phy_4x.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_phy_4x.v' to AST representation.
Generating RTLIL representation for module `\hdmi_phy_4x'.
Successfully finished Verilog frontend.

53. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_text_2x.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/hdmi_text_2x.v' to AST representation.
Generating RTLIL representation for module `\hdmi_text_2x'.
Successfully finished Verilog frontend.

54. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_shared_ram.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_shared_ram.v' to AST representation.
Generating RTLIL representation for module `\vid_shared_ram'.
Successfully finished Verilog frontend.

55. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_text.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_text.v' to AST representation.
Generating RTLIL representation for module `\vid_text'.
Generating RTLIL representation for module `\vid_color_map'.
Successfully finished Verilog frontend.

56. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v' to AST representation.
Generating RTLIL representation for module `\vid_tgen'.
Successfully finished Verilog frontend.

57. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v' to AST representation.
Generating RTLIL representation for module `\vid_top'.
Successfully finished Verilog frontend.

58. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_palette.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_palette.v' to AST representation.
Generating RTLIL representation for module `\vid_palette'.
Successfully finished Verilog frontend.

59. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_framebuf.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_framebuf.v' to AST representation.
Generating RTLIL representation for module `\vid_framebuf'.
Successfully finished Verilog frontend.

60. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v' to AST representation.
Generating RTLIL representation for module `\soc_bram'.
Successfully finished Verilog frontend.

61. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/sysmgr.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/sysmgr.v' to AST representation.
Generating RTLIL representation for module `\sysmgr'.
Successfully finished Verilog frontend.

62. Executing Verilog-2005 frontend: /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v
Parsing Verilog input from `/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v' to AST representation.
Generating RTLIL representation for module `\InstructionCache'.
Generating RTLIL representation for module `\VexRiscv'.
Successfully finished Verilog frontend.

63. Executing SYNTH_ICE40 pass.

63.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_sim.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_sim.v' to AST representation.
Generating RTLIL representation for module `\SB_IO'.
Generating RTLIL representation for module `\SB_GB_IO'.
Generating RTLIL representation for module `\SB_GB'.
Generating RTLIL representation for module `\SB_LUT4'.
Generating RTLIL representation for module `\SB_CARRY'.
Generating RTLIL representation for module `\SB_DFF'.
Generating RTLIL representation for module `\SB_DFFE'.
Generating RTLIL representation for module `\SB_DFFSR'.
Generating RTLIL representation for module `\SB_DFFR'.
Generating RTLIL representation for module `\SB_DFFSS'.
Generating RTLIL representation for module `\SB_DFFS'.
Generating RTLIL representation for module `\SB_DFFESR'.
Generating RTLIL representation for module `\SB_DFFER'.
Generating RTLIL representation for module `\SB_DFFESS'.
Generating RTLIL representation for module `\SB_DFFES'.
Generating RTLIL representation for module `\SB_DFFN'.
Generating RTLIL representation for module `\SB_DFFNE'.
Generating RTLIL representation for module `\SB_DFFNSR'.
Generating RTLIL representation for module `\SB_DFFNR'.
Generating RTLIL representation for module `\SB_DFFNSS'.
Generating RTLIL representation for module `\SB_DFFNS'.
Generating RTLIL representation for module `\SB_DFFNESR'.
Generating RTLIL representation for module `\SB_DFFNER'.
Generating RTLIL representation for module `\SB_DFFNESS'.
Generating RTLIL representation for module `\SB_DFFNES'.
Generating RTLIL representation for module `\SB_RAM40_4K'.
Generating RTLIL representation for module `\SB_RAM40_4KNR'.
Generating RTLIL representation for module `\SB_RAM40_4KNW'.
Generating RTLIL representation for module `\SB_RAM40_4KNRNW'.
Generating RTLIL representation for module `\ICESTORM_LC'.
Generating RTLIL representation for module `\SB_PLL40_CORE'.
Generating RTLIL representation for module `\SB_PLL40_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2_PAD'.
Generating RTLIL representation for module `\SB_PLL40_2F_CORE'.
Generating RTLIL representation for module `\SB_PLL40_2F_PAD'.
Generating RTLIL representation for module `\SB_WARMBOOT'.
Generating RTLIL representation for module `\SB_SPRAM256KA'.
Generating RTLIL representation for module `\SB_HFOSC'.
Generating RTLIL representation for module `\SB_LFOSC'.
Generating RTLIL representation for module `\SB_RGBA_DRV'.
Generating RTLIL representation for module `\SB_LED_DRV_CUR'.
Generating RTLIL representation for module `\SB_RGB_DRV'.
Generating RTLIL representation for module `\SB_I2C'.
Generating RTLIL representation for module `\SB_SPI'.
Generating RTLIL representation for module `\SB_LEDDA_IP'.
Generating RTLIL representation for module `\SB_FILTER_50NS'.
Generating RTLIL representation for module `\SB_IO_I3C'.
Generating RTLIL representation for module `\SB_IO_OD'.
Generating RTLIL representation for module `\SB_MAC16'.
Generating RTLIL representation for module `\ICESTORM_RAM'.
Successfully finished Verilog frontend.

63.2. Executing HIERARCHY pass (managing design hierarchy).

63.2.1. Analyzing design hierarchy..
Top module:  \top
Used module:     \sysmgr
Used module:         \ice40_serdes_sync
Used module:             \ice40_serdes_dff
Used module:         \ice40_serdes_crg
Used module:     \ice40_rgb_wb
Used module:     \uart_wb
Used module:         \fifo_sync_ram
Used module:             \ram_sdp
Used module:         \uart_rx
Used module:             \glitch_filter
Used module:         \uart_tx
Used module:     \vid_top
Used module:         \hdmi_phy_1x
Used module:         \delay_bit
Used module:         \vid_tgen
Used module:             \dffer_n
Used module:         \vid_palette
Used module:         \vid_framebuf
Used module:     \qpi_phy_ice40_4x
Used module:         \ice40_oserdes
Used module:         \ice40_iserdes
Used module:     \qpi_memctrl
Used module:         \fifo_sync_shift
Used module:         \delay_bus
Used module:     \mc_core
Used module:         \mc_tag_match
Used module:         \mc_tag_ram
Used module:             \ice40_ebr
Used module:         \ice40_spram_gen
Used module:     \soc_bram
Used module:     \mc_bus_vex
Used module:     \VexRiscv
Used module:         \InstructionCache
Parameter \CURRENT_MODE = 24'001100000110001000110001
Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001
Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001
Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001

63.2.2. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_rgb_wb'.
Parameter \CURRENT_MODE = 24'001100000110001000110001
Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001
Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001
Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001
Generating RTLIL representation for module `$paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb'.
Parameter \DIV_WIDTH = 12
Parameter \DW = 32

63.2.3. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_wb'.
Parameter \DIV_WIDTH = 12
Parameter \DW = 32
Generating RTLIL representation for module `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb'.
Parameter \N_CS = 2
Parameter \WITH_CLK = 1

63.2.4. Executing AST frontend in derive mode using pre-parsed AST for module `\qpi_phy_ice40_4x'.
Parameter \N_CS = 2
Parameter \WITH_CLK = 1
Generating RTLIL representation for module `$paramod$9a9e2282df54acafd6229f692355382480e5c2ad\qpi_phy_ice40_4x'.
Parameter \CMD_READ = 16'1110101100001011
Parameter \CMD_WRITE = 16'0000001000000010
Parameter \DUMMY_CLK = 6
Parameter \PAUSE_CLK = 8
Parameter \FIFO_DEPTH = 1
Parameter \N_CS = 2
Parameter \PHY_SPEED = 4
Parameter \PHY_WIDTH = 1
Parameter \PHY_DELAY = 4

63.2.5. Executing AST frontend in derive mode using pre-parsed AST for module `\qpi_memctrl'.
Parameter \CMD_READ = 16'1110101100001011
Parameter \CMD_WRITE = 16'0000001000000010
Parameter \DUMMY_CLK = 6
Parameter \PAUSE_CLK = 8
Parameter \FIFO_DEPTH = 1
Parameter \N_CS = 2
Parameter \PHY_SPEED = 4
Parameter \PHY_WIDTH = 1
Parameter \PHY_DELAY = 4
Generating RTLIL representation for module `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl'.
Parameter \N_WAYS = 4
Parameter \ADDR_WIDTH = 24
Parameter \CACHE_LINE = 32
Parameter \CACHE_SIZE = 64

63.2.6. Executing AST frontend in derive mode using pre-parsed AST for module `\mc_core'.
Parameter \N_WAYS = 4
Parameter \ADDR_WIDTH = 24
Parameter \CACHE_LINE = 32
Parameter \CACHE_SIZE = 64
Generating RTLIL representation for module `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core'.
Warning: Replacing memory \way_tag_we with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:446
Warning: Replacing memory \way_age_nxt with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:406
Warning: Replacing memory \way_dirty_we with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:377
Warning: Replacing memory \way_dirty_nxt with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:376
Warning: Replacing memory \way_valid_we with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:373
Warning: Replacing memory \way_valid_nxt with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:372
Memory cache config :
 -           4 ways
 -          64 kbytes cache
 -          32 bytes cache lines
 -          64 Mbytes address space
 -          12/          9/          3 address split
Memory cache config :
 -           4 ways
 -          64 kbytes cache
 -          32 bytes cache lines
 -          64 Mbytes address space
 -          12/          9/          3 address split
Parameter \AW = 8
Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000

63.2.7. Executing AST frontend in derive mode using pre-parsed AST for module `\soc_bram'.
Parameter \AW = 8
Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000
Generating RTLIL representation for module `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram'.
Parameter \WB_N = 4

63.2.8. Executing AST frontend in derive mode using pre-parsed AST for module `\mc_bus_vex'.
Parameter \WB_N = 4
Generating RTLIL representation for module `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100'.
Reprocessing module top because instantiated module ice40_rgb_wb has become available.
Generating RTLIL representation for module `\top'.
Parameter \L = 2
Parameter \RST_VAL = 1'1
Parameter \WITH_SYNCHRONIZER = 1

63.2.9. Executing AST frontend in derive mode using pre-parsed AST for module `\glitch_filter'.
Parameter \L = 2
Parameter \RST_VAL = 1'1
Parameter \WITH_SYNCHRONIZER = 1
Generating RTLIL representation for module `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter'.
Parameter \TAG_WIDTH = 12

63.2.10. Executing AST frontend in derive mode using pre-parsed AST for module `\mc_tag_match'.
Parameter \TAG_WIDTH = 12
Generating RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \IDX_WIDTH = 8
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2

63.2.11. Executing AST frontend in derive mode using pre-parsed AST for module `\mc_tag_ram'.
Parameter \IDX_WIDTH = 8
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Generating RTLIL representation for module `$paramod$f397632cf779d01999ffbcfc67eeb9a2da1f7b6b\mc_tag_ram'.
Cache tag memory config,           1 x         256 x          16
Parameter \IDX_WIDTH = 8
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Found cached RTLIL representation for module `$paramod$f397632cf779d01999ffbcfc67eeb9a2da1f7b6b\mc_tag_ram'.
Parameter \IDX_WIDTH = 8
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Found cached RTLIL representation for module `$paramod$f397632cf779d01999ffbcfc67eeb9a2da1f7b6b\mc_tag_ram'.
Parameter \IDX_WIDTH = 8
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Found cached RTLIL representation for module `$paramod$f397632cf779d01999ffbcfc67eeb9a2da1f7b6b\mc_tag_ram'.
Parameter \ADDR_WIDTH = 14
Parameter \DATA_WIDTH = 32

63.2.12. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_spram_gen'.
Parameter \ADDR_WIDTH = 14
Parameter \DATA_WIDTH = 32
Generating RTLIL representation for module `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen'.
ice40_spram_gen: (      16384x         32) ->           1x          2 array of SPRAM

ice40_spram_gen: (      16384x         32) ->           1x          2 array of SPRAM

/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
Reprocessing module mc_core because instantiated module mc_tag_match has become available.
Generating RTLIL representation for module `\mc_core'.
Warning: Replacing memory \way_tag_we with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:446
Warning: Replacing memory \way_age_nxt with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:406
Warning: Replacing memory \way_dirty_we with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:377
Warning: Replacing memory \way_dirty_nxt with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:376
Warning: Replacing memory \way_valid_we with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:373
Warning: Replacing memory \way_valid_nxt with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:372
Memory cache config :
 -           4 ways
 -          64 kbytes cache
 -          64 bytes cache lines
 -          64 Mbytes address space
 -          12/          8/          4 address split
Memory cache config :
 -           4 ways
 -          64 kbytes cache
 -          64 bytes cache lines
 -          64 Mbytes address space
 -          12/          8/          4 address split
Parameter \DEPTH = 1
Parameter \WIDTH = 32

63.2.13. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_shift'.
Parameter \DEPTH = 1
Parameter \WIDTH = 32
Generating RTLIL representation for module `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift'.
Parameter \DEPTH = 1
Parameter \WIDTH = 36

63.2.14. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_shift'.
Parameter \DEPTH = 1
Parameter \WIDTH = 36
Generating RTLIL representation for module `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift'.
Parameter 1 (\DELAY) = 6
Parameter 2 (\WIDTH) = 2

63.2.15. Executing AST frontend in derive mode using pre-parsed AST for module `\delay_bus'.
Parameter 1 (\DELAY) = 6
Parameter 2 (\WIDTH) = 2
Generating RTLIL representation for module `$paramod$207d30fa21ecab167490f434b739f4dde492aa96\delay_bus'.
Warning: Replacing memory \dl with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:59
Parameter 1 (\DELAY) = 6

63.2.16. Executing AST frontend in derive mode using pre-parsed AST for module `\delay_bit'.
Parameter 1 (\DELAY) = 6
Generating RTLIL representation for module `$paramod\delay_bit\DELAY=s32'00000000000000000000000000000110'.
Parameter \MODE = 64'0100001101001100010010110011100100110000010111110011010001011000
Parameter \SERDES_GRP = 64

63.2.17. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_oserdes'.
Parameter \MODE = 64'0100001101001100010010110011100100110000010111110011010001011000
Parameter \SERDES_GRP = 64
Generating RTLIL representation for module `$paramod$ee5fa83b1ca770f4f834672f5d772cff0c2d7889\ice40_oserdes'.
Parameter \EDGE_SEL = 80'01010011010010010100111001000111010011000100010101011111010100000100111101010011
Parameter \PHASE_SEL = 48'010100110101010001000001010101000100100101000011
Parameter \PHASE = 1
Parameter \SERDES_GRP = 48

63.2.18. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_iserdes'.
Parameter \EDGE_SEL = 80'01010011010010010100111001000111010011000100010101011111010100000100111101010011
Parameter \PHASE_SEL = 48'010100110101010001000001010101000100100101000011
Parameter \PHASE = 1
Parameter \SERDES_GRP = 48
Generating RTLIL representation for module `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 48

63.2.19. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 48
Generating RTLIL representation for module `$paramod$863b677bc445782f1534bda513d3ab7f02676b5c\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 50

63.2.20. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 50
Generating RTLIL representation for module `$paramod$75c621542c1e9767613d02b1f3511b93ee44cfa1\ice40_oserdes'.
Parameter \EDGE_SEL = 80'01010011010010010100111001000111010011000100010101011111010100000100111101010011
Parameter \PHASE_SEL = 48'010100110101010001000001010101000100100101000011
Parameter \PHASE = 1
Parameter \SERDES_GRP = 32

63.2.21. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_iserdes'.
Parameter \EDGE_SEL = 80'01010011010010010100111001000111010011000100010101011111010100000100111101010011
Parameter \PHASE_SEL = 48'010100110101010001000001010101000100100101000011
Parameter \PHASE = 1
Parameter \SERDES_GRP = 32
Generating RTLIL representation for module `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 32

63.2.22. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 32
Generating RTLIL representation for module `$paramod$fe37dab75e68305ee07af1db6f0f96490b9fdc39\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 34

63.2.23. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 34
Generating RTLIL representation for module `$paramod$a13561ec4a4d594cc35622ccd91582314db7bb43\ice40_oserdes'.
Parameter \EDGE_SEL = 80'01010011010010010100111001000111010011000100010101011111010100000100111101010011
Parameter \PHASE_SEL = 48'010100110101010001000001010101000100100101000011
Parameter \PHASE = 1
Parameter \SERDES_GRP = 16

63.2.24. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_iserdes'.
Parameter \EDGE_SEL = 80'01010011010010010100111001000111010011000100010101011111010100000100111101010011
Parameter \PHASE_SEL = 48'010100110101010001000001010101000100100101000011
Parameter \PHASE = 1
Parameter \SERDES_GRP = 16
Generating RTLIL representation for module `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 16

63.2.25. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 16
Generating RTLIL representation for module `$paramod$5c6db5a604a4655a57dfd9340bd964139a251510\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 18

63.2.26. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 18
Generating RTLIL representation for module `$paramod$087675b5e9c65e52d59a156f0ccae4f673504c8c\ice40_oserdes'.
Parameter \EDGE_SEL = 80'01010011010010010100111001000111010011000100010101011111010100000100111101010011
Parameter \PHASE_SEL = 48'010100110101010001000001010101000100100101000011
Parameter \PHASE = 1
Parameter \SERDES_GRP = 0

63.2.27. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_iserdes'.
Parameter \EDGE_SEL = 80'01010011010010010100111001000111010011000100010101011111010100000100111101010011
Parameter \PHASE_SEL = 48'010100110101010001000001010101000100100101000011
Parameter \PHASE = 1
Parameter \SERDES_GRP = 0
Generating RTLIL representation for module `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 0

63.2.28. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 0
Generating RTLIL representation for module `$paramod$917d62ab073ab2caba68f39824d52335f3c1a5e3\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 2

63.2.29. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 2
Generating RTLIL representation for module `$paramod$9a9c4528a326fac997fd1fc463b8f4223e2e4501\ice40_oserdes'.
Parameter \DW = 12

63.2.30. Executing AST frontend in derive mode using pre-parsed AST for module `\hdmi_phy_1x'.
Parameter \DW = 12
Generating RTLIL representation for module `$paramod\hdmi_phy_1x\DW=s32'00000000000000000000000000001100'.
Parameter 1 (\DELAY) = 4

63.2.31. Executing AST frontend in derive mode using pre-parsed AST for module `\delay_bit'.
Parameter 1 (\DELAY) = 4
Generating RTLIL representation for module `$paramod\delay_bit\DELAY=s32'00000000000000000000000000000100'.
Parameter 1 (\DELAY) = 4
Found cached RTLIL representation for module `$paramod\delay_bit\DELAY=s32'00000000000000000000000000000100'.
Parameter 1 (\DELAY) = 4
Found cached RTLIL representation for module `$paramod\delay_bit\DELAY=s32'00000000000000000000000000000100'.
Parameter \H_WIDTH = 10
Parameter \H_FP = 16
Parameter \H_SYNC = 96
Parameter \H_BP = 48
Parameter \H_ACTIVE = 640
Parameter \V_WIDTH = 9
Parameter \V_FP = 10
Parameter \V_SYNC = 2
Parameter \V_BP = 33
Parameter \V_ACTIVE = 480

63.2.32. Executing AST frontend in derive mode using pre-parsed AST for module `\vid_tgen'.
Parameter \H_WIDTH = 10
Parameter \H_FP = 16
Parameter \H_SYNC = 96
Parameter \H_BP = 48
Parameter \H_ACTIVE = 640
Parameter \V_WIDTH = 9
Parameter \V_FP = 10
Parameter \V_SYNC = 2
Parameter \V_BP = 33
Parameter \V_ACTIVE = 480
Generating RTLIL representation for module `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen'.
Parameter \DEPTH = 512
Parameter \WIDTH = 8

63.2.33. Executing AST frontend in derive mode using pre-parsed AST for module `\fifo_sync_ram'.
Parameter \DEPTH = 512
Parameter \WIDTH = 8
Generating RTLIL representation for module `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram'.
Parameter \DIV_WIDTH = 8
Parameter \GLITCH_FILTER = 2

63.2.34. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \DIV_WIDTH = 8
Parameter \GLITCH_FILTER = 2
Generating RTLIL representation for module `$paramod$7f9c9dc10c5023dd2cab0d7f15aed8a846ffdc0f\uart_rx'.
Parameter \DEPTH = 512
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram'.
Parameter \DIV_WIDTH = 8

63.2.35. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \DIV_WIDTH = 8
Generating RTLIL representation for module `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001000'.
Parameter \PHASE = 2
Parameter \NEG_EDGE = 0
Parameter \GLOBAL_BUF = 0
Parameter \BEL_COL = 24'010110000011001000110000
Parameter \BEL_ROW = 16'0101100100110100

63.2.36. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_sync'.
Parameter \PHASE = 2
Parameter \NEG_EDGE = 0
Parameter \GLOBAL_BUF = 0
Parameter \BEL_COL = 24'010110000011001000110000
Parameter \BEL_ROW = 16'0101100100110100
Generating RTLIL representation for module `$paramod$ee292efbb55924cacfdc6c8744bdb7148f59d2f1\ice40_serdes_sync'.
Parameter \NO_CLOCK_2X = 1

63.2.37. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_crg'.
Parameter \NO_CLOCK_2X = 1
Generating RTLIL representation for module `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001'.
Reprocessing module ice40_spram_gen because instantiated module SB_SPRAM256KA has become available.
Generating RTLIL representation for module `\ice40_spram_gen'.
ice40_spram_gen: (      32768x         32) ->           2x          2 array of SPRAM

ice40_spram_gen: (      32768x         32) ->           2x          2 array of SPRAM

/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [0:-3] select out of bounds on signal `\mem_di_w': Setting 3 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [1:-2] select out of bounds on signal `\mem_di_w': Setting 2 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [2:-1] select out of bounds on signal `\mem_di_w': Setting 1 LSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [32:29] select out of bounds on signal `\mem_di_w': Setting 1 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [33:30] select out of bounds on signal `\mem_di_w': Setting 2 MSB bits to undef.
/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93: Warning: Range [34:31] select out of bounds on signal `\mem_di_w': Setting 3 MSB bits to undef.
Parameter \SERDES_GRP = 1667

63.2.38. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 1667
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000011'.
Parameter \SERDES_GRP = 1666

63.2.39. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 1666
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000010'.
Parameter \SERDES_GRP = 1665

63.2.40. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 1665
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000001'.
Parameter \SERDES_GRP = 1664

63.2.41. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 1664
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000000'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1171

63.2.42. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1171
Generating RTLIL representation for module `$paramod$692a90536143b3fec671d73677449145eabc3620\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1170

63.2.43. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1170
Generating RTLIL representation for module `$paramod$e44b3f6b88bd9f13d1f900764c097b88a8073837\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1169

63.2.44. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1169
Generating RTLIL representation for module `$paramod$7f62c438601400b211e700d756641d52d2e1073c\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1168

63.2.45. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1168
Generating RTLIL representation for module `$paramod$b32caa8ce454d2e243a8fb7a97f312acff133bb3\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1187

63.2.46. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1187
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100011'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1186

63.2.47. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1186
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100010'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1185

63.2.48. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1185
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100001'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1184

63.2.49. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1184
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100000'.
Reprocessing module ice40_iserdes because instantiated module ice40_serdes_dff has become available.
Generating RTLIL representation for module `\ice40_iserdes'.
Parameter \SERDES_GRP = 19

63.2.50. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 19
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010011'.
Parameter \SERDES_GRP = 18

63.2.51. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 18
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010010'.
Parameter \SERDES_GRP = 17

63.2.52. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 17
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010001'.
Parameter \SERDES_GRP = 16

63.2.53. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 16
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010000'.
Parameter \SERDES_GRP = 3

63.2.54. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 3
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000011'.
Parameter \SERDES_GRP = 2

63.2.55. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 2
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000010'.
Parameter \SERDES_GRP = 1

63.2.56. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 1
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000001'.
Parameter \SERDES_GRP = 0

63.2.57. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 0
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000000'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110000

63.2.58. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110000
Generating RTLIL representation for module `$paramod$e582e01de39d2ccec0eda709a059c6502ef10ca2\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110011

63.2.59. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110011
Generating RTLIL representation for module `$paramod$07ca3d1f78a879dc39a837b8d9e903991da7bbdb\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110001

63.2.60. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110001
Generating RTLIL representation for module `$paramod$7e9a852169de2d5a3807011d4af0c0c979be79db\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110010

63.2.61. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110010
Generating RTLIL representation for module `$paramod$354937bc6e2407abb5374fb8b6b45a93b3cf4dcf\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110100

63.2.62. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110100
Generating RTLIL representation for module `$paramod$5553150595ce128e8881055d0643ebec9e06010a\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110101

63.2.63. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110101
Generating RTLIL representation for module `$paramod$b756c283dac417a3f66bb2faa83643ea2ae173f9\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110110

63.2.64. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110110
Generating RTLIL representation for module `$paramod$3a038e4ae1bbb4a9811d27dd9e1d6c2d2e5d256c\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110111

63.2.65. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0101100000110001001100100010111101011001001100010011010100101111011011000110001100110111
Generating RTLIL representation for module `$paramod$feb33513e5e8d86bcdd307ab9a0650ce90ec0260\ice40_serdes_dff'.
Parameter \READ_MODE = 0
Parameter \WRITE_MODE = 0
Parameter \MASK_WORKAROUND = 1
Parameter \NEG_WR_CLK = 1

63.2.66. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_ebr'.
Parameter \READ_MODE = 0
Parameter \WRITE_MODE = 0
Parameter \MASK_WORKAROUND = 1
Parameter \NEG_WR_CLK = 1
Generating RTLIL representation for module `$paramod$7db067aaa473dab241a2e6bd8e04bce79caf2659\ice40_ebr'.
Parameter \AWIDTH = 8
Parameter \DWIDTH = 16

63.2.67. Executing AST frontend in derive mode using pre-parsed AST for module `\ram_sdp'.
Parameter \AWIDTH = 8
Parameter \DWIDTH = 16
Generating RTLIL representation for module `$paramod$b719a54c035d67416e4798d4fba708942b43d3ac\ram_sdp'.
Parameter \WIDTH = 13

63.2.68. Executing AST frontend in derive mode using pre-parsed AST for module `\dffer_n'.
Parameter \WIDTH = 13
Generating RTLIL representation for module `$paramod\dffer_n\WIDTH=s32'00000000000000000000000000001101'.

63.2.69. Analyzing design hierarchy..
Top module:  \top
Used module:     \sysmgr
Used module:         $paramod$ee292efbb55924cacfdc6c8744bdb7148f59d2f1\ice40_serdes_sync
Used module:             \ice40_serdes_dff
Used module:         $paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001
Used module:     \ice40_rgb_wb
Used module:     \uart_wb
Used module:         $paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram
Used module:             \ram_sdp
Used module:         $paramod$7f9c9dc10c5023dd2cab0d7f15aed8a846ffdc0f\uart_rx
Used module:             \glitch_filter
Used module:         $paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001000
Used module:     \vid_top
Used module:         $paramod\hdmi_phy_1x\DW=s32'00000000000000000000000000001100
Used module:         $paramod\delay_bit\DELAY=s32'00000000000000000000000000000100
Used module:         $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen
Used module:             \dffer_n
Used module:         \vid_palette
Used module:         \vid_framebuf
Used module:     \qpi_phy_ice40_4x
Used module:         $paramod$ee5fa83b1ca770f4f834672f5d772cff0c2d7889\ice40_oserdes
Used module:         $paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes
Used module:         $paramod$863b677bc445782f1534bda513d3ab7f02676b5c\ice40_oserdes
Used module:         $paramod$75c621542c1e9767613d02b1f3511b93ee44cfa1\ice40_oserdes
Used module:         $paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes
Used module:         $paramod$fe37dab75e68305ee07af1db6f0f96490b9fdc39\ice40_oserdes
Used module:         $paramod$a13561ec4a4d594cc35622ccd91582314db7bb43\ice40_oserdes
Used module:         $paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes
Used module:         $paramod$5c6db5a604a4655a57dfd9340bd964139a251510\ice40_oserdes
Used module:         $paramod$087675b5e9c65e52d59a156f0ccae4f673504c8c\ice40_oserdes
Used module:         $paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes
Used module:         $paramod$917d62ab073ab2caba68f39824d52335f3c1a5e3\ice40_oserdes
Used module:         $paramod$9a9c4528a326fac997fd1fc463b8f4223e2e4501\ice40_oserdes
Used module:     \qpi_memctrl
Used module:         $paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift
Used module:         $paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift
Used module:         $paramod$207d30fa21ecab167490f434b739f4dde492aa96\delay_bus
Used module:         $paramod\delay_bit\DELAY=s32'00000000000000000000000000000110
Used module:     \mc_core
Used module:         \mc_tag_match
Used module:         \mc_tag_ram
Used module:             $paramod$7db067aaa473dab241a2e6bd8e04bce79caf2659\ice40_ebr
Used module:         \ice40_spram_gen
Used module:     \soc_bram
Used module:     \mc_bus_vex
Used module:     \VexRiscv
Used module:         \InstructionCache
Parameter \CURRENT_MODE = 24'001100000110001000110001
Parameter \RGB0_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001
Parameter \RGB1_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001
Parameter \RGB2_CURRENT = 64'0011000001100010001100000011000000110000001100000011000000110001
Found cached RTLIL representation for module `$paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb'.
Parameter \DIV_WIDTH = 12
Parameter \DW = 32
Found cached RTLIL representation for module `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb'.
Parameter \N_CS = 2
Parameter \WITH_CLK = 1
Found cached RTLIL representation for module `$paramod$9a9e2282df54acafd6229f692355382480e5c2ad\qpi_phy_ice40_4x'.
Parameter \CMD_READ = 16'1110101100001011
Parameter \CMD_WRITE = 16'0000001000000010
Parameter \DUMMY_CLK = 6
Parameter \PAUSE_CLK = 8
Parameter \FIFO_DEPTH = 1
Parameter \N_CS = 2
Parameter \PHY_SPEED = 4
Parameter \PHY_WIDTH = 1
Parameter \PHY_DELAY = 4
Found cached RTLIL representation for module `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl'.
Parameter \N_WAYS = 4
Parameter \ADDR_WIDTH = 24
Parameter \CACHE_LINE = 32
Parameter \CACHE_SIZE = 64
Found cached RTLIL representation for module `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core'.
Parameter \AW = 8
Parameter \INIT_FILE = 64'0110001001101111011011110111010000101110011010000110010101111000
Found cached RTLIL representation for module `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram'.
Parameter \WB_N = 4
Found cached RTLIL representation for module `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100'.
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \IDX_WIDTH = 8
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Found cached RTLIL representation for module `$paramod$f397632cf779d01999ffbcfc67eeb9a2da1f7b6b\mc_tag_ram'.
Parameter \IDX_WIDTH = 8
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Found cached RTLIL representation for module `$paramod$f397632cf779d01999ffbcfc67eeb9a2da1f7b6b\mc_tag_ram'.
Parameter \IDX_WIDTH = 8
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Found cached RTLIL representation for module `$paramod$f397632cf779d01999ffbcfc67eeb9a2da1f7b6b\mc_tag_ram'.
Parameter \IDX_WIDTH = 8
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Found cached RTLIL representation for module `$paramod$f397632cf779d01999ffbcfc67eeb9a2da1f7b6b\mc_tag_ram'.
Parameter \ADDR_WIDTH = 14
Parameter \DATA_WIDTH = 32
Found cached RTLIL representation for module `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen'.
Parameter \SERDES_GRP = 16416

63.2.70. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 16416
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000100000'.
Parameter \SERDES_GRP = 16403

63.2.71. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 16403
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010011'.
Parameter \SERDES_GRP = 16402

63.2.72. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 16402
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010010'.
Parameter \SERDES_GRP = 16401

63.2.73. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 16401
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010001'.
Parameter \SERDES_GRP = 16400

63.2.74. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 16400
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010000'.
Parameter \SERDES_GRP = 16387

63.2.75. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 16387
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000011'.
Parameter \SERDES_GRP = 16386

63.2.76. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 16386
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000010'.
Parameter \SERDES_GRP = 16385

63.2.77. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 16385
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000001'.
Parameter \SERDES_GRP = 16384

63.2.78. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 16384
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000000'.
Parameter \SERDES_GRP = 13956

63.2.79. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 13956
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000100'.
Parameter \SERDES_GRP = 13955

63.2.80. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 13955
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000011'.
Parameter \SERDES_GRP = 13954

63.2.81. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 13954
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000010'.
Parameter \SERDES_GRP = 13953

63.2.82. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 13953
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000001'.
Parameter \SERDES_GRP = 13952

63.2.83. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 13952
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000000'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 13459

63.2.84. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 13459
Generating RTLIL representation for module `$paramod$4d8f22cf4ec64d0fb9f63f1c98686217b3799a7d\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 13458

63.2.85. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 13458
Generating RTLIL representation for module `$paramod$e7ef2081568887628eb303394d34c9d8476d8a88\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 13457

63.2.86. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 13457
Generating RTLIL representation for module `$paramod$2797d931cd0954c5520f5806e7f1ebd82a03ad28\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 13456

63.2.87. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 13456
Generating RTLIL representation for module `$paramod$9424c184a55595b25ce0f57bb97552df113fdbb7\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 13475

63.2.88. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 13475
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100011'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 13474

63.2.89. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 13474
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100010'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 13473

63.2.90. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 13473
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100001'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 13472

63.2.91. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 13472
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100000'.
Reprocessing module $paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes because instantiated module $paramod$4d8f22cf4ec64d0fb9f63f1c98686217b3799a7d\ice40_serdes_dff has become available.
Generating RTLIL representation for module `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes'.
Parameter \SERDES_GRP = 12307

63.2.92. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12307
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010011'.
Parameter \SERDES_GRP = 12306

63.2.93. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12306
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010010'.
Parameter \SERDES_GRP = 12305

63.2.94. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12305
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010001'.
Parameter \SERDES_GRP = 12304

63.2.95. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12304
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010000'.
Parameter \SERDES_GRP = 12291

63.2.96. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12291
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000011'.
Parameter \SERDES_GRP = 12290

63.2.97. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12290
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000010'.
Parameter \SERDES_GRP = 12289

63.2.98. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12289
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000001'.
Parameter \SERDES_GRP = 12288

63.2.99. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12288
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000000'.
Parameter \SERDES_GRP = 12819

63.2.100. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12819
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010011'.
Parameter \SERDES_GRP = 12818

63.2.101. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12818
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010010'.
Parameter \SERDES_GRP = 12817

63.2.102. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12817
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010001'.
Parameter \SERDES_GRP = 12816

63.2.103. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12816
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010000'.
Parameter \SERDES_GRP = 12803

63.2.104. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12803
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000011'.
Parameter \SERDES_GRP = 12802

63.2.105. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12802
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000010'.
Parameter \SERDES_GRP = 12801

63.2.106. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12801
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000001'.
Parameter \SERDES_GRP = 12800

63.2.107. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 12800
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000000'.
Parameter \SERDES_GRP = 9860

63.2.108. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 9860
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000100'.
Parameter \SERDES_GRP = 9859

63.2.109. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 9859
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000011'.
Parameter \SERDES_GRP = 9858

63.2.110. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 9858
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000010'.
Parameter \SERDES_GRP = 9857

63.2.111. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 9857
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000001'.
Parameter \SERDES_GRP = 9856

63.2.112. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 9856
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000000'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 9363

63.2.113. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 9363
Generating RTLIL representation for module `$paramod$8364285540c9e5de4006551b06ee5b25c31d3ac4\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 9362

63.2.114. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 9362
Generating RTLIL representation for module `$paramod$3b1dc861a4d0285a9c0e28e86e84bf3f3bf78af8\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 9361

63.2.115. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 9361
Generating RTLIL representation for module `$paramod$c937d5e4376f8f2580c5fe8fd2426ef1292329e8\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 9360

63.2.116. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 9360
Generating RTLIL representation for module `$paramod$4f4cafaa8e148481ffc96bfe5f39236edef69b27\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 9379

63.2.117. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 9379
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100011'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 9378

63.2.118. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 9378
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100010'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 9377

63.2.119. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 9377
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100001'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 9376

63.2.120. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 9376
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100000'.
Reprocessing module $paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes because instantiated module $paramod$8364285540c9e5de4006551b06ee5b25c31d3ac4\ice40_serdes_dff has become available.
Generating RTLIL representation for module `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes'.
Parameter \SERDES_GRP = 8211

63.2.121. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8211
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010011'.
Parameter \SERDES_GRP = 8210

63.2.122. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8210
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010010'.
Parameter \SERDES_GRP = 8209

63.2.123. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8209
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010001'.
Parameter \SERDES_GRP = 8208

63.2.124. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8208
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010000'.
Parameter \SERDES_GRP = 8195

63.2.125. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8195
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000011'.
Parameter \SERDES_GRP = 8194

63.2.126. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8194
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000010'.
Parameter \SERDES_GRP = 8193

63.2.127. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8193
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000001'.
Parameter \SERDES_GRP = 8192

63.2.128. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8192
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000000'.
Parameter \SERDES_GRP = 8723

63.2.129. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8723
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010011'.
Parameter \SERDES_GRP = 8722

63.2.130. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8722
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010010'.
Parameter \SERDES_GRP = 8721

63.2.131. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8721
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010001'.
Parameter \SERDES_GRP = 8720

63.2.132. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8720
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010000'.
Parameter \SERDES_GRP = 8707

63.2.133. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8707
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000011'.
Parameter \SERDES_GRP = 8706

63.2.134. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8706
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000010'.
Parameter \SERDES_GRP = 8705

63.2.135. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8705
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000001'.
Parameter \SERDES_GRP = 8704

63.2.136. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 8704
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000000'.
Parameter \SERDES_GRP = 5764

63.2.137. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 5764
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000100'.
Parameter \SERDES_GRP = 5763

63.2.138. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 5763
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000011'.
Parameter \SERDES_GRP = 5762

63.2.139. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 5762
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000010'.
Parameter \SERDES_GRP = 5761

63.2.140. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 5761
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000001'.
Parameter \SERDES_GRP = 5760

63.2.141. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 5760
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000000'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 5267

63.2.142. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 5267
Generating RTLIL representation for module `$paramod$585d871e3f028093b352aaf4a6a5ed67b111fc87\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 5266

63.2.143. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 5266
Generating RTLIL representation for module `$paramod$cc9a6e6bf39368ff82a94c2c06971bb1433935c4\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 5265

63.2.144. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 5265
Generating RTLIL representation for module `$paramod$609ef96eefd5f217e59829af7272b2c75ca4270a\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 5264

63.2.145. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 5264
Generating RTLIL representation for module `$paramod$287ed5c83870694bd6af0f98e8abdcf9f10a3b0d\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 5283

63.2.146. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 5283
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100011'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 5282

63.2.147. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 5282
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100010'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 5281

63.2.148. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 5281
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100001'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 5280

63.2.149. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 5280
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100000'.
Reprocessing module $paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes because instantiated module $paramod$585d871e3f028093b352aaf4a6a5ed67b111fc87\ice40_serdes_dff has become available.
Generating RTLIL representation for module `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes'.
Parameter \SERDES_GRP = 4115

63.2.150. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4115
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010011'.
Parameter \SERDES_GRP = 4114

63.2.151. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4114
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010010'.
Parameter \SERDES_GRP = 4113

63.2.152. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4113
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010001'.
Parameter \SERDES_GRP = 4112

63.2.153. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4112
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010000'.
Parameter \SERDES_GRP = 4099

63.2.154. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4099
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000011'.
Parameter \SERDES_GRP = 4098

63.2.155. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4098
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000010'.
Parameter \SERDES_GRP = 4097

63.2.156. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4097
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000001'.
Parameter \SERDES_GRP = 4096

63.2.157. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4096
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000000'.
Parameter \SERDES_GRP = 4627

63.2.158. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4627
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010011'.
Parameter \SERDES_GRP = 4626

63.2.159. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4626
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010010'.
Parameter \SERDES_GRP = 4625

63.2.160. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4625
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010001'.
Parameter \SERDES_GRP = 4624

63.2.161. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4624
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010000'.
Parameter \SERDES_GRP = 4611

63.2.162. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4611
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000011'.
Parameter \SERDES_GRP = 4610

63.2.163. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4610
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000010'.
Parameter \SERDES_GRP = 4609

63.2.164. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4609
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000001'.
Parameter \SERDES_GRP = 4608

63.2.165. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 4608
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000000'.
Parameter \SERDES_GRP = 1668

63.2.166. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 1668
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000100'.
Parameter \SERDES_GRP = 1667
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000011'.
Parameter \SERDES_GRP = 1666
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000010'.
Parameter \SERDES_GRP = 1665
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000001'.
Parameter \SERDES_GRP = 1664
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000000'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1171
Found cached RTLIL representation for module `$paramod$692a90536143b3fec671d73677449145eabc3620\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1170
Found cached RTLIL representation for module `$paramod$e44b3f6b88bd9f13d1f900764c097b88a8073837\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1169
Found cached RTLIL representation for module `$paramod$7f62c438601400b211e700d756641d52d2e1073c\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1168
Found cached RTLIL representation for module `$paramod$b32caa8ce454d2e243a8fb7a97f312acff133bb3\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1187
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100011'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1186
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100010'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1185
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100001'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1184
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100000'.
Reprocessing module $paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes because instantiated module $paramod$692a90536143b3fec671d73677449145eabc3620\ice40_serdes_dff has become available.
Generating RTLIL representation for module `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes'.
Parameter \SERDES_GRP = 19
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010011'.
Parameter \SERDES_GRP = 18
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010010'.
Parameter \SERDES_GRP = 17
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010001'.
Parameter \SERDES_GRP = 16
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010000'.
Parameter \SERDES_GRP = 3
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000011'.
Parameter \SERDES_GRP = 2
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000010'.
Parameter \SERDES_GRP = 1
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000001'.
Parameter \SERDES_GRP = 0
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000000'.
Parameter \SERDES_GRP = 531

63.2.167. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 531
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010011'.
Parameter \SERDES_GRP = 530

63.2.168. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 530
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010010'.
Parameter \SERDES_GRP = 529

63.2.169. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 529
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010001'.
Parameter \SERDES_GRP = 528

63.2.170. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 528
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010000'.
Parameter \SERDES_GRP = 515

63.2.171. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 515
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000011'.
Parameter \SERDES_GRP = 514

63.2.172. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 514
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000010'.
Parameter \SERDES_GRP = 513

63.2.173. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 513
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000001'.
Parameter \SERDES_GRP = 512

63.2.174. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \SERDES_GRP = 512
Generating RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000000'.
Parameter \WIDTH = 10

63.2.175. Executing AST frontend in derive mode using pre-parsed AST for module `\dffer_n'.
Parameter \WIDTH = 10
Generating RTLIL representation for module `$paramod\dffer_n\WIDTH=s32'00000000000000000000000000001010'.
Parameter \AWIDTH = 9
Parameter \DWIDTH = 8

63.2.176. Executing AST frontend in derive mode using pre-parsed AST for module `\ram_sdp'.
Parameter \AWIDTH = 9
Parameter \DWIDTH = 8
Generating RTLIL representation for module `$paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp'.
Parameter \L = 2
Parameter \RST_VAL = 1'1
Parameter \WITH_SYNCHRONIZER = 1
Found cached RTLIL representation for module `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110000

63.2.177. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110000
Generating RTLIL representation for module `$paramod$681b594bc9ea94cf8d9a4c2606247a2c915777f4\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110011

63.2.178. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110011
Generating RTLIL representation for module `$paramod$30ee323e18e10972cd7003a5025831d5a704d820\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110001

63.2.179. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110001
Generating RTLIL representation for module `$paramod$3ad1583e0481d446cb74cb52afebc0dc3fce6746\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110010

63.2.180. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110010
Generating RTLIL representation for module `$paramod$52fdd5761ec779f8f28128b640a08a8cc595d827\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110100

63.2.181. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110100
Generating RTLIL representation for module `$paramod$d1350f99652fccfa0eca6f20eb458128402cb851\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110101

63.2.182. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110101
Generating RTLIL representation for module `$paramod$eddda7c69c5b1281f2431cd4e70f1617a655638d\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110110

63.2.183. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110110
Generating RTLIL representation for module `$paramod$152f54a12eb3ca1dd5881a1a75733b2cc275300e\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110111

63.2.184. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_serdes_dff'.
Parameter \NEG = 0
Parameter \RST = 1
Parameter \BEL = 88'0000000001011000001100100011000000101111010110010011010000101111011011000110001100110111
Generating RTLIL representation for module `$paramod$728f7da6b691d49936b0c3bda28a068249eab591\ice40_serdes_dff'.

63.2.185. Analyzing design hierarchy..
Top module:  \top
Used module:     \sysmgr
Used module:         $paramod$ee292efbb55924cacfdc6c8744bdb7148f59d2f1\ice40_serdes_sync
Used module:             $paramod$681b594bc9ea94cf8d9a4c2606247a2c915777f4\ice40_serdes_dff
Used module:             $paramod$30ee323e18e10972cd7003a5025831d5a704d820\ice40_serdes_dff
Used module:             $paramod$3ad1583e0481d446cb74cb52afebc0dc3fce6746\ice40_serdes_dff
Used module:             $paramod$52fdd5761ec779f8f28128b640a08a8cc595d827\ice40_serdes_dff
Used module:             $paramod$d1350f99652fccfa0eca6f20eb458128402cb851\ice40_serdes_dff
Used module:             $paramod$eddda7c69c5b1281f2431cd4e70f1617a655638d\ice40_serdes_dff
Used module:             $paramod$152f54a12eb3ca1dd5881a1a75733b2cc275300e\ice40_serdes_dff
Used module:             $paramod$728f7da6b691d49936b0c3bda28a068249eab591\ice40_serdes_dff
Used module:         $paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001
Used module:     $paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb
Used module:     $paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb
Used module:         \fifo_sync_ram
Used module:             $paramod$b719a54c035d67416e4798d4fba708942b43d3ac\ram_sdp
Used module:         \uart_rx
Used module:             $paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter
Used module:         \uart_tx
Used module:     \vid_top
Used module:         $paramod\hdmi_phy_1x\DW=s32'00000000000000000000000000001100
Used module:         $paramod\delay_bit\DELAY=s32'00000000000000000000000000000100
Used module:         $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen
Used module:             $paramod\dffer_n\WIDTH=s32'00000000000000000000000000001010
Used module:         \vid_palette
Used module:         \vid_framebuf
Used module:     $paramod$9a9e2282df54acafd6229f692355382480e5c2ad\qpi_phy_ice40_4x
Used module:         \ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000000
Used module:         \ice40_iserdes
Used module:             \ice40_serdes_dff
Used module:     $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl
Used module:         \fifo_sync_shift
Used module:         \delay_bus
Used module:         \delay_bit
Used module:     $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core
Used module:         \mc_tag_match
Used module:         \mc_tag_ram
Used module:             $paramod$7db067aaa473dab241a2e6bd8e04bce79caf2659\ice40_ebr
Used module:         \ice40_spram_gen
Used module:     $paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram
Used module:     $paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100
Used module:     \VexRiscv
Used module:         \InstructionCache
Parameter \SERDES_GRP = 1667
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000011'.
Parameter \SERDES_GRP = 1666
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000010'.
Parameter \SERDES_GRP = 1665
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000001'.
Parameter \SERDES_GRP = 1664
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000000'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1171
Found cached RTLIL representation for module `$paramod$692a90536143b3fec671d73677449145eabc3620\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1170
Found cached RTLIL representation for module `$paramod$e44b3f6b88bd9f13d1f900764c097b88a8073837\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1169
Found cached RTLIL representation for module `$paramod$7f62c438601400b211e700d756641d52d2e1073c\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1168
Found cached RTLIL representation for module `$paramod$b32caa8ce454d2e243a8fb7a97f312acff133bb3\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1187
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100011'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1186
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100010'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1185
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100001'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1184
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100000'.
Parameter \DEPTH = 512
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram'.
Parameter \DIV_WIDTH = 12
Parameter \GLITCH_FILTER = 2

63.2.186. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_rx'.
Parameter \DIV_WIDTH = 12
Parameter \GLITCH_FILTER = 2
Generating RTLIL representation for module `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx'.
Parameter \DEPTH = 512
Parameter \WIDTH = 8
Found cached RTLIL representation for module `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram'.
Parameter \DIV_WIDTH = 12

63.2.187. Executing AST frontend in derive mode using pre-parsed AST for module `\uart_tx'.
Parameter \DIV_WIDTH = 12
Generating RTLIL representation for module `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100'.
Parameter \MODE = 64'0100001101001100010010110011100100110000010111110011010001011000
Parameter \SERDES_GRP = 64
Found cached RTLIL representation for module `$paramod$ee5fa83b1ca770f4f834672f5d772cff0c2d7889\ice40_oserdes'.
Parameter \EDGE_SEL = 80'01010011010010010100111001000111010011000100010101011111010100000100111101010011
Parameter \PHASE_SEL = 48'010100110101010001000001010101000100100101000011
Parameter \PHASE = 1
Parameter \SERDES_GRP = 48
Found cached RTLIL representation for module `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 48
Found cached RTLIL representation for module `$paramod$863b677bc445782f1534bda513d3ab7f02676b5c\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 50
Found cached RTLIL representation for module `$paramod$75c621542c1e9767613d02b1f3511b93ee44cfa1\ice40_oserdes'.
Parameter \EDGE_SEL = 80'01010011010010010100111001000111010011000100010101011111010100000100111101010011
Parameter \PHASE_SEL = 48'010100110101010001000001010101000100100101000011
Parameter \PHASE = 1
Parameter \SERDES_GRP = 32
Found cached RTLIL representation for module `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 32
Found cached RTLIL representation for module `$paramod$fe37dab75e68305ee07af1db6f0f96490b9fdc39\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 34
Found cached RTLIL representation for module `$paramod$a13561ec4a4d594cc35622ccd91582314db7bb43\ice40_oserdes'.
Parameter \EDGE_SEL = 80'01010011010010010100111001000111010011000100010101011111010100000100111101010011
Parameter \PHASE_SEL = 48'010100110101010001000001010101000100100101000011
Parameter \PHASE = 1
Parameter \SERDES_GRP = 16
Found cached RTLIL representation for module `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 16
Found cached RTLIL representation for module `$paramod$5c6db5a604a4655a57dfd9340bd964139a251510\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 18
Found cached RTLIL representation for module `$paramod$087675b5e9c65e52d59a156f0ccae4f673504c8c\ice40_oserdes'.
Parameter \EDGE_SEL = 80'01010011010010010100111001000111010011000100010101011111010100000100111101010011
Parameter \PHASE_SEL = 48'010100110101010001000001010101000100100101000011
Parameter \PHASE = 1
Parameter \SERDES_GRP = 0
Found cached RTLIL representation for module `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 0
Found cached RTLIL representation for module `$paramod$917d62ab073ab2caba68f39824d52335f3c1a5e3\ice40_oserdes'.
Parameter \MODE = 1145132097
Parameter \SERDES_GRP = 2
Found cached RTLIL representation for module `$paramod$9a9c4528a326fac997fd1fc463b8f4223e2e4501\ice40_oserdes'.
Parameter \DEPTH = 1
Parameter \WIDTH = 32
Found cached RTLIL representation for module `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift'.
Parameter \DEPTH = 1
Parameter \WIDTH = 36
Found cached RTLIL representation for module `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift'.
Parameter 1 (\DELAY) = 4
Parameter 2 (\WIDTH) = 2

63.2.188. Executing AST frontend in derive mode using pre-parsed AST for module `\delay_bus'.
Parameter 1 (\DELAY) = 4
Parameter 2 (\WIDTH) = 2
Generating RTLIL representation for module `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus'.
Warning: Replacing memory \dl with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:59
Parameter 1 (\DELAY) = 4
Found cached RTLIL representation for module `$paramod\delay_bit\DELAY=s32'00000000000000000000000000000100'.
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \IDX_WIDTH = 9
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2

63.2.189. Executing AST frontend in derive mode using pre-parsed AST for module `\mc_tag_ram'.
Parameter \IDX_WIDTH = 9
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Generating RTLIL representation for module `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram'.
Cache tag memory config,           2 x         512 x           8
Parameter \IDX_WIDTH = 9
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Found cached RTLIL representation for module `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram'.
Parameter \IDX_WIDTH = 9
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Found cached RTLIL representation for module `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram'.
Parameter \IDX_WIDTH = 9
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Found cached RTLIL representation for module `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram'.
Parameter \ADDR_WIDTH = 14
Parameter \DATA_WIDTH = 32
Found cached RTLIL representation for module `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen'.
Reprocessing module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core because instantiated module $paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100 has become available.
Generating RTLIL representation for module `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core'.
Warning: Replacing memory \way_tag_we with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:446
Warning: Replacing memory \way_age_nxt with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:406
Warning: Replacing memory \way_dirty_we with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:377
Warning: Replacing memory \way_dirty_nxt with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:376
Warning: Replacing memory \way_valid_we with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:373
Warning: Replacing memory \way_valid_nxt with list of registers. See /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:372
Memory cache config :
 -           4 ways
 -          64 kbytes cache
 -          32 bytes cache lines
 -          64 Mbytes address space
 -          12/          9/          3 address split
Memory cache config :
 -           4 ways
 -          64 kbytes cache
 -          32 bytes cache lines
 -          64 Mbytes address space
 -          12/          9/          3 address split

63.2.190. Analyzing design hierarchy..
Top module:  \top
Used module:     \sysmgr
Used module:         $paramod$ee292efbb55924cacfdc6c8744bdb7148f59d2f1\ice40_serdes_sync
Used module:             $paramod$681b594bc9ea94cf8d9a4c2606247a2c915777f4\ice40_serdes_dff
Used module:             $paramod$30ee323e18e10972cd7003a5025831d5a704d820\ice40_serdes_dff
Used module:             $paramod$3ad1583e0481d446cb74cb52afebc0dc3fce6746\ice40_serdes_dff
Used module:             $paramod$52fdd5761ec779f8f28128b640a08a8cc595d827\ice40_serdes_dff
Used module:             $paramod$d1350f99652fccfa0eca6f20eb458128402cb851\ice40_serdes_dff
Used module:             $paramod$eddda7c69c5b1281f2431cd4e70f1617a655638d\ice40_serdes_dff
Used module:             $paramod$152f54a12eb3ca1dd5881a1a75733b2cc275300e\ice40_serdes_dff
Used module:             $paramod$728f7da6b691d49936b0c3bda28a068249eab591\ice40_serdes_dff
Used module:         $paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001
Used module:     $paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb
Used module:     $paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb
Used module:         $paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram
Used module:             $paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp
Used module:         $paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx
Used module:             \glitch_filter
Used module:         $paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100
Used module:     \vid_top
Used module:         $paramod\hdmi_phy_1x\DW=s32'00000000000000000000000000001100
Used module:         $paramod\delay_bit\DELAY=s32'00000000000000000000000000000100
Used module:         $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen
Used module:             $paramod\dffer_n\WIDTH=s32'00000000000000000000000000001010
Used module:         \vid_palette
Used module:         \vid_framebuf
Used module:     $paramod$9a9e2282df54acafd6229f692355382480e5c2ad\qpi_phy_ice40_4x
Used module:         $paramod$ee5fa83b1ca770f4f834672f5d772cff0c2d7889\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000100000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000000
Used module:         $paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes
Used module:             \ice40_serdes_dff
Used module:         $paramod$863b677bc445782f1534bda513d3ab7f02676b5c\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000000
Used module:         $paramod$75c621542c1e9767613d02b1f3511b93ee44cfa1\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000000
Used module:         $paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes
Used module:         $paramod$fe37dab75e68305ee07af1db6f0f96490b9fdc39\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000000
Used module:         $paramod$a13561ec4a4d594cc35622ccd91582314db7bb43\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000000
Used module:         $paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes
Used module:         $paramod$5c6db5a604a4655a57dfd9340bd964139a251510\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000000
Used module:         $paramod$087675b5e9c65e52d59a156f0ccae4f673504c8c\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000000
Used module:         $paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes
Used module:         $paramod$917d62ab073ab2caba68f39824d52335f3c1a5e3\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000000
Used module:         $paramod$9a9c4528a326fac997fd1fc463b8f4223e2e4501\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000000
Used module:     $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl
Used module:         $paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift
Used module:         $paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift
Used module:         $paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus
Used module:     $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core
Used module:         \mc_tag_match
Used module:         \mc_tag_ram
Used module:             $paramod$7db067aaa473dab241a2e6bd8e04bce79caf2659\ice40_ebr
Used module:         \ice40_spram_gen
Used module:     $paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram
Used module:     $paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100
Used module:     \VexRiscv
Used module:         \InstructionCache
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \TAG_WIDTH = 12
Found cached RTLIL representation for module `$paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100'.
Parameter \IDX_WIDTH = 9
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Found cached RTLIL representation for module `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram'.
Parameter \IDX_WIDTH = 9
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Found cached RTLIL representation for module `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram'.
Parameter \IDX_WIDTH = 9
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Found cached RTLIL representation for module `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram'.
Parameter \IDX_WIDTH = 9
Parameter \TAG_WIDTH = 12
Parameter \AGE_WIDTH = 2
Found cached RTLIL representation for module `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram'.
Parameter \ADDR_WIDTH = 14
Parameter \DATA_WIDTH = 32
Found cached RTLIL representation for module `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen'.
Parameter \SERDES_GRP = 13956
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000100'.
Parameter \SERDES_GRP = 13955
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000011'.
Parameter \SERDES_GRP = 13954
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000010'.
Parameter \SERDES_GRP = 13953
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000001'.
Parameter \SERDES_GRP = 13952
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000000'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 13459
Found cached RTLIL representation for module `$paramod$4d8f22cf4ec64d0fb9f63f1c98686217b3799a7d\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 13458
Found cached RTLIL representation for module `$paramod$e7ef2081568887628eb303394d34c9d8476d8a88\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 13457
Found cached RTLIL representation for module `$paramod$2797d931cd0954c5520f5806e7f1ebd82a03ad28\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 13456
Found cached RTLIL representation for module `$paramod$9424c184a55595b25ce0f57bb97552df113fdbb7\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 13475
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100011'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 13474
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100010'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 13473
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100001'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 13472
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100000'.
Parameter \L = 2
Parameter \RST_VAL = 1'1
Parameter \WITH_SYNCHRONIZER = 1
Found cached RTLIL representation for module `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter'.
Parameter \SERDES_GRP = 9860
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000100'.
Parameter \SERDES_GRP = 9859
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000011'.
Parameter \SERDES_GRP = 9858
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000010'.
Parameter \SERDES_GRP = 9857
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000001'.
Parameter \SERDES_GRP = 9856
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000000'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 9363
Found cached RTLIL representation for module `$paramod$8364285540c9e5de4006551b06ee5b25c31d3ac4\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 9362
Found cached RTLIL representation for module `$paramod$3b1dc861a4d0285a9c0e28e86e84bf3f3bf78af8\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 9361
Found cached RTLIL representation for module `$paramod$c937d5e4376f8f2580c5fe8fd2426ef1292329e8\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 9360
Found cached RTLIL representation for module `$paramod$4f4cafaa8e148481ffc96bfe5f39236edef69b27\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 9379
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100011'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 9378
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100010'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 9377
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100001'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 9376
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100000'.
Parameter \SERDES_GRP = 5764
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000100'.
Parameter \SERDES_GRP = 5763
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000011'.
Parameter \SERDES_GRP = 5762
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000010'.
Parameter \SERDES_GRP = 5761
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000001'.
Parameter \SERDES_GRP = 5760
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000000'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 5267
Found cached RTLIL representation for module `$paramod$585d871e3f028093b352aaf4a6a5ed67b111fc87\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 5266
Found cached RTLIL representation for module `$paramod$cc9a6e6bf39368ff82a94c2c06971bb1433935c4\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 5265
Found cached RTLIL representation for module `$paramod$609ef96eefd5f217e59829af7272b2c75ca4270a\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 5264
Found cached RTLIL representation for module `$paramod$287ed5c83870694bd6af0f98e8abdcf9f10a3b0d\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 5283
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100011'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 5282
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100010'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 5281
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100001'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 5280
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100000'.
Parameter \SERDES_GRP = 1668
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000100'.
Parameter \SERDES_GRP = 1667
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000011'.
Parameter \SERDES_GRP = 1666
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000010'.
Parameter \SERDES_GRP = 1665
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000001'.
Parameter \SERDES_GRP = 1664
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000000'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1171
Found cached RTLIL representation for module `$paramod$692a90536143b3fec671d73677449145eabc3620\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1170
Found cached RTLIL representation for module `$paramod$e44b3f6b88bd9f13d1f900764c097b88a8073837\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1169
Found cached RTLIL representation for module `$paramod$7f62c438601400b211e700d756641d52d2e1073c\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \ENA = 1
Parameter \SERDES_GRP = 1168
Found cached RTLIL representation for module `$paramod$b32caa8ce454d2e243a8fb7a97f312acff133bb3\ice40_serdes_dff'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1187
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100011'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1186
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100010'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1185
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100001'.
Parameter \NEG = 1'0
Parameter \SERDES_GRP = 1184
Found cached RTLIL representation for module `$paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100000'.

63.2.191. Analyzing design hierarchy..
Top module:  \top
Used module:     \sysmgr
Used module:         $paramod$ee292efbb55924cacfdc6c8744bdb7148f59d2f1\ice40_serdes_sync
Used module:             $paramod$681b594bc9ea94cf8d9a4c2606247a2c915777f4\ice40_serdes_dff
Used module:             $paramod$30ee323e18e10972cd7003a5025831d5a704d820\ice40_serdes_dff
Used module:             $paramod$3ad1583e0481d446cb74cb52afebc0dc3fce6746\ice40_serdes_dff
Used module:             $paramod$52fdd5761ec779f8f28128b640a08a8cc595d827\ice40_serdes_dff
Used module:             $paramod$d1350f99652fccfa0eca6f20eb458128402cb851\ice40_serdes_dff
Used module:             $paramod$eddda7c69c5b1281f2431cd4e70f1617a655638d\ice40_serdes_dff
Used module:             $paramod$152f54a12eb3ca1dd5881a1a75733b2cc275300e\ice40_serdes_dff
Used module:             $paramod$728f7da6b691d49936b0c3bda28a068249eab591\ice40_serdes_dff
Used module:         $paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001
Used module:     $paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb
Used module:     $paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb
Used module:         $paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram
Used module:             $paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp
Used module:         $paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx
Used module:             $paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter
Used module:         $paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100
Used module:     \vid_top
Used module:         $paramod\hdmi_phy_1x\DW=s32'00000000000000000000000000001100
Used module:         $paramod\delay_bit\DELAY=s32'00000000000000000000000000000100
Used module:         $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen
Used module:             $paramod\dffer_n\WIDTH=s32'00000000000000000000000000001010
Used module:         \vid_palette
Used module:         \vid_framebuf
Used module:     $paramod$9a9e2282df54acafd6229f692355382480e5c2ad\qpi_phy_ice40_4x
Used module:         $paramod$ee5fa83b1ca770f4f834672f5d772cff0c2d7889\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000100000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000000
Used module:         $paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000100
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000011
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Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000000
Used module:             $paramod$4d8f22cf4ec64d0fb9f63f1c98686217b3799a7d\ice40_serdes_dff
Used module:             $paramod$e7ef2081568887628eb303394d34c9d8476d8a88\ice40_serdes_dff
Used module:             $paramod$2797d931cd0954c5520f5806e7f1ebd82a03ad28\ice40_serdes_dff
Used module:             $paramod$9424c184a55595b25ce0f57bb97552df113fdbb7\ice40_serdes_dff
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100011
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100010
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100001
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100000
Used module:         $paramod$863b677bc445782f1534bda513d3ab7f02676b5c\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000000
Used module:         $paramod$75c621542c1e9767613d02b1f3511b93ee44cfa1\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000000
Used module:         $paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000100
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000000
Used module:             $paramod$8364285540c9e5de4006551b06ee5b25c31d3ac4\ice40_serdes_dff
Used module:             $paramod$3b1dc861a4d0285a9c0e28e86e84bf3f3bf78af8\ice40_serdes_dff
Used module:             $paramod$c937d5e4376f8f2580c5fe8fd2426ef1292329e8\ice40_serdes_dff
Used module:             $paramod$4f4cafaa8e148481ffc96bfe5f39236edef69b27\ice40_serdes_dff
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100011
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100010
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100001
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100000
Used module:         $paramod$fe37dab75e68305ee07af1db6f0f96490b9fdc39\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000000
Used module:         $paramod$a13561ec4a4d594cc35622ccd91582314db7bb43\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000000
Used module:         $paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000100
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000000
Used module:             $paramod$585d871e3f028093b352aaf4a6a5ed67b111fc87\ice40_serdes_dff
Used module:             $paramod$cc9a6e6bf39368ff82a94c2c06971bb1433935c4\ice40_serdes_dff
Used module:             $paramod$609ef96eefd5f217e59829af7272b2c75ca4270a\ice40_serdes_dff
Used module:             $paramod$287ed5c83870694bd6af0f98e8abdcf9f10a3b0d\ice40_serdes_dff
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100011
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100010
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100001
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100000
Used module:         $paramod$5c6db5a604a4655a57dfd9340bd964139a251510\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000000
Used module:         $paramod$087675b5e9c65e52d59a156f0ccae4f673504c8c\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000000
Used module:         $paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000100
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000000
Used module:             $paramod$692a90536143b3fec671d73677449145eabc3620\ice40_serdes_dff
Used module:             $paramod$e44b3f6b88bd9f13d1f900764c097b88a8073837\ice40_serdes_dff
Used module:             $paramod$7f62c438601400b211e700d756641d52d2e1073c\ice40_serdes_dff
Used module:             $paramod$b32caa8ce454d2e243a8fb7a97f312acff133bb3\ice40_serdes_dff
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100011
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100010
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100001
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100000
Used module:         $paramod$917d62ab073ab2caba68f39824d52335f3c1a5e3\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000000
Used module:         $paramod$9a9c4528a326fac997fd1fc463b8f4223e2e4501\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000000
Used module:     $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl
Used module:         $paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift
Used module:         $paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift
Used module:         $paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus
Used module:     $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core
Used module:         $paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100
Used module:         $paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram
Used module:             \ice40_ebr
Used module:         $paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen
Used module:     $paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram
Used module:     $paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100
Used module:     \VexRiscv
Used module:         \InstructionCache
Parameter \READ_MODE = 1
Parameter \WRITE_MODE = 1
Parameter \MASK_WORKAROUND = 1
Parameter \NEG_WR_CLK = 1

63.2.192. Executing AST frontend in derive mode using pre-parsed AST for module `\ice40_ebr'.
Parameter \READ_MODE = 1
Parameter \WRITE_MODE = 1
Parameter \MASK_WORKAROUND = 1
Parameter \NEG_WR_CLK = 1
Generating RTLIL representation for module `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr'.
Parameter \READ_MODE = 1
Parameter \WRITE_MODE = 1
Parameter \MASK_WORKAROUND = 1
Parameter \NEG_WR_CLK = 1
Found cached RTLIL representation for module `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr'.

63.2.193. Analyzing design hierarchy..
Top module:  \top
Used module:     \sysmgr
Used module:         $paramod$ee292efbb55924cacfdc6c8744bdb7148f59d2f1\ice40_serdes_sync
Used module:             $paramod$681b594bc9ea94cf8d9a4c2606247a2c915777f4\ice40_serdes_dff
Used module:             $paramod$30ee323e18e10972cd7003a5025831d5a704d820\ice40_serdes_dff
Used module:             $paramod$3ad1583e0481d446cb74cb52afebc0dc3fce6746\ice40_serdes_dff
Used module:             $paramod$52fdd5761ec779f8f28128b640a08a8cc595d827\ice40_serdes_dff
Used module:             $paramod$d1350f99652fccfa0eca6f20eb458128402cb851\ice40_serdes_dff
Used module:             $paramod$eddda7c69c5b1281f2431cd4e70f1617a655638d\ice40_serdes_dff
Used module:             $paramod$152f54a12eb3ca1dd5881a1a75733b2cc275300e\ice40_serdes_dff
Used module:             $paramod$728f7da6b691d49936b0c3bda28a068249eab591\ice40_serdes_dff
Used module:         $paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001
Used module:     $paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb
Used module:     $paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb
Used module:         $paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram
Used module:             $paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp
Used module:         $paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx
Used module:             $paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter
Used module:         $paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100
Used module:     \vid_top
Used module:         $paramod\hdmi_phy_1x\DW=s32'00000000000000000000000000001100
Used module:         $paramod\delay_bit\DELAY=s32'00000000000000000000000000000100
Used module:         $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen
Used module:             $paramod\dffer_n\WIDTH=s32'00000000000000000000000000001010
Used module:         \vid_palette
Used module:         \vid_framebuf
Used module:     $paramod$9a9e2282df54acafd6229f692355382480e5c2ad\qpi_phy_ice40_4x
Used module:         $paramod$ee5fa83b1ca770f4f834672f5d772cff0c2d7889\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000100000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000000
Used module:         $paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000100
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000000
Used module:             $paramod$4d8f22cf4ec64d0fb9f63f1c98686217b3799a7d\ice40_serdes_dff
Used module:             $paramod$e7ef2081568887628eb303394d34c9d8476d8a88\ice40_serdes_dff
Used module:             $paramod$2797d931cd0954c5520f5806e7f1ebd82a03ad28\ice40_serdes_dff
Used module:             $paramod$9424c184a55595b25ce0f57bb97552df113fdbb7\ice40_serdes_dff
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100011
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100010
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100001
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63.2.194. Analyzing design hierarchy..
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Used module:             $paramod$585d871e3f028093b352aaf4a6a5ed67b111fc87\ice40_serdes_dff
Used module:             $paramod$cc9a6e6bf39368ff82a94c2c06971bb1433935c4\ice40_serdes_dff
Used module:             $paramod$609ef96eefd5f217e59829af7272b2c75ca4270a\ice40_serdes_dff
Used module:             $paramod$287ed5c83870694bd6af0f98e8abdcf9f10a3b0d\ice40_serdes_dff
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100011
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100010
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100001
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100000
Used module:         $paramod$5c6db5a604a4655a57dfd9340bd964139a251510\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000000
Used module:         $paramod$087675b5e9c65e52d59a156f0ccae4f673504c8c\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000000
Used module:         $paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000100
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000000
Used module:             $paramod$692a90536143b3fec671d73677449145eabc3620\ice40_serdes_dff
Used module:             $paramod$e44b3f6b88bd9f13d1f900764c097b88a8073837\ice40_serdes_dff
Used module:             $paramod$7f62c438601400b211e700d756641d52d2e1073c\ice40_serdes_dff
Used module:             $paramod$b32caa8ce454d2e243a8fb7a97f312acff133bb3\ice40_serdes_dff
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100011
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100010
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100001
Used module:             $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100000
Used module:         $paramod$917d62ab073ab2caba68f39824d52335f3c1a5e3\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000000
Used module:         $paramod$9a9c4528a326fac997fd1fc463b8f4223e2e4501\ice40_oserdes
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010000
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000011
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000010
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000001
Used module:             $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000000
Used module:     $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl
Used module:         $paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift
Used module:         $paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift
Used module:         $paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus
Used module:     $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core
Used module:         $paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100
Used module:         $paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram
Used module:             $paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr
Used module:         $paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen
Used module:     $paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram
Used module:     $paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100
Used module:     \VexRiscv
Used module:         \InstructionCache
Removing unused module `$paramod$3a038e4ae1bbb4a9811d27dd9e1d6c2d2e5d256c\ice40_serdes_dff'.
Removing unused module `$paramod$b756c283dac417a3f66bb2faa83643ea2ae173f9\ice40_serdes_dff'.
Removing unused module `$paramod$5553150595ce128e8881055d0643ebec9e06010a\ice40_serdes_dff'.
Removing unused module `$paramod$354937bc6e2407abb5374fb8b6b45a93b3cf4dcf\ice40_serdes_dff'.
Removing unused module `$paramod$7e9a852169de2d5a3807011d4af0c0c979be79db\ice40_serdes_dff'.
Removing unused module `$paramod$07ca3d1f78a879dc39a837b8d9e903991da7bbdb\ice40_serdes_dff'.
Removing unused module `$paramod$e582e01de39d2ccec0eda709a059c6502ef10ca2\ice40_serdes_dff'.
Removing unused module `\ice40_iserdes'.
Removing unused module `$paramod\dffer_n\WIDTH=s32'00000000000000000000000000001101'.
Removing unused module `\ice40_spram_gen'.
Removing unused module `$paramod$b719a54c035d67416e4798d4fba708942b43d3ac\ram_sdp'.
Removing unused module `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001000'.
Removing unused module `$paramod$7f9c9dc10c5023dd2cab0d7f15aed8a846ffdc0f\uart_rx'.
Removing unused module `$paramod\delay_bit\DELAY=s32'00000000000000000000000000000110'.
Removing unused module `$paramod$207d30fa21ecab167490f434b739f4dde492aa96\delay_bus'.
Removing unused module `\mc_core'.
Removing unused module `$paramod$7db067aaa473dab241a2e6bd8e04bce79caf2659\ice40_ebr'.
Removing unused module `$paramod$f397632cf779d01999ffbcfc67eeb9a2da1f7b6b\mc_tag_ram'.
Removing unused module `$paramod$feb33513e5e8d86bcdd307ab9a0650ce90ec0260\ice40_serdes_dff'.
Removing unused module `\soc_bram'.
Removing unused module `\vid_tgen'.
Removing unused module `\vid_color_map'.
Removing unused module `\vid_text'.
Removing unused module `\vid_shared_ram'.
Removing unused module `\hdmi_text_2x'.
Removing unused module `\hdmi_phy_4x'.
Removing unused module `\hdmi_phy_2x'.
Removing unused module `\hdmi_phy_1x'.
Removing unused module `\usb_tx_pkt'.
Removing unused module `\usb_tx_ll'.
Removing unused module `\usb_trans'.
Removing unused module `\usb_rx_pkt'.
Removing unused module `\usb_rx_ll'.
Removing unused module `\usb_phy'.
Removing unused module `\usb_ep_status'.
Removing unused module `\usb_ep_buf'.
Removing unused module `\usb_crc'.
Removing unused module `\usb'.
Removing unused module `\qpi_phy_ice40_4x'.
Removing unused module `\qpi_phy_ice40_2x'.
Removing unused module `\qpi_phy_ice40_1x'.
Removing unused module `\qpi_memctrl'.
Removing unused module `\xclk_wb'.
Removing unused module `\xclk_strobe'.
Removing unused module `\uart_wb'.
Removing unused module `\uart_tx'.
Removing unused module `\uart_rx'.
Removing unused module `\uart2wb'.
Removing unused module `\stream2wb'.
Removing unused module `\ram_sdp'.
Removing unused module `\pwm'.
Removing unused module `\pdm_lfsr'.
Removing unused module `\pdm'.
Removing unused module `\dffesr_n'.
Removing unused module `\dffer_n'.
Removing unused module `\dffe_n'.
Removing unused module `\dff_n'.
Removing unused module `\lut4_carry_n'.
Removing unused module `\lut4_n'.
Removing unused module `\muacm2wb'.
Removing unused module `\i2c_master_wb'.
Removing unused module `\i2c_master'.
Removing unused module `\glitch_filter'.
Removing unused module `\fifo_sync_shift'.
Removing unused module `\fifo_sync_ram'.
Removing unused module `\delay_bus'.
Removing unused module `\delay_bit'.
Removing unused module `\mc_tag_ram'.
Removing unused module `\mc_tag_match'.
Removing unused module `\mc_bus_wb'.
Removing unused module `\mc_bus_vex'.
Removing unused module `\ice40_serdes_sync'.
Removing unused module `\ice40_serdes_dff'.
Removing unused module `\ice40_serdes_crg'.
Removing unused module `\ice40_oserdes'.
Removing unused module `\ice40_spram_wb'.
Removing unused module `\ice40_spi_wb'.
Removing unused module `\ice40_rgb_wb'.
Removing unused module `\ice40_i2c_wb'.
Removing unused module `\ice40_ebr'.
Removed 80 unused modules.
Module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core directly or indirectly displays text -> setting "keep" attribute.
Module top directly or indirectly displays text -> setting "keep" attribute.
Module $paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram directly or indirectly displays text -> setting "keep" attribute.
Module $paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen directly or indirectly displays text -> setting "keep" attribute.
Mapping positional arguments of cell $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.dly_si_dst ($paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus).
Mapping positional arguments of cell $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.dly_si_mode ($paramod\delay_bit\DELAY=s32'00000000000000000000000000000100).
Mapping positional arguments of cell vid_top.dly_de ($paramod\delay_bit\DELAY=s32'00000000000000000000000000000100).
Mapping positional arguments of cell vid_top.dly_vsync ($paramod\delay_bit\DELAY=s32'00000000000000000000000000000100).
Mapping positional arguments of cell vid_top.dly_hsync ($paramod\delay_bit\DELAY=s32'00000000000000000000000000000100).

63.3. Executing PROC pass (convert processes to netlists).

63.3.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Found and cleaned up 1 empty switch in `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:0$3388'.
Removing empty process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:0$3388'.
Found and cleaned up 1 empty switch in `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_ram.v:0$4451'.
Removing empty process `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_ram.v:0$4451'.
Found and cleaned up 1 empty switch in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
Found and cleaned up 1 empty switch in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
Found and cleaned up 2 empty switches in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:700$3085'.
Cleaned up 6 empty switches.

63.3.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed 1 dead cases from process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4631 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4631 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Removed 1 dead cases from process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4628 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4628 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Removed 1 dead cases from process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4625 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4625 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:503$4617 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:476$4615 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Marked 21 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:396$4577 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:330$4546 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:309$4541 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:220$4524 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Removed 1 dead cases from process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:174$4514 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Marked 5 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:174$4514 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:167$4513 in module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:58$4440 in module $paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:51$4437 in module $paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:42$4433 in module $paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:35$4429 in module $paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:88$4419 in module $paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:77$4415 in module $paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:70$4411 in module $paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:39$4400 in module $paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:116$3982 in module $paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:108$3976 in module $paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:95$3974 in module $paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:83$3965 in module $paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:67$3959 in module $paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:179$3945 in module $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.
Removed 1 dead cases from process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:147$3944 in module $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:147$3944 in module $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:141$3942 in module $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:135$3941 in module $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:121$3936 in module $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.
Removed 1 dead cases from process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:108$3935 in module $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:108$3935 in module $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:102$3933 in module $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:96$3932 in module $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:64$3884 in module $paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:57$3882 in module $paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:64$3871 in module $paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:57$3869 in module $paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:95$3509 in module $paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:80$3505 in module $paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:70$3501 in module $paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:60$3493 in module $paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.
Marked 4 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353 in module $paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.
Marked 5 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:615$3181 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Removed 1 dead cases from process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Marked 4 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:700$3085 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:691$3083 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:677$3077 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Removed 2 dead cases from process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:544$3063 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:544$3063 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:515$3051 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:506$3043 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Marked 9 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:466$3036 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:459$3035 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:373$3025 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:331$3001 in module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:185$2971 in module $paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:177$2961 in module $paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:164$2944 in module $paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:154$2939 in module $paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_rgb_wb.v:94$2932 in module $paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$2791 in module SB_DFFNES.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$2786 in module SB_DFFNESS.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$2782 in module SB_DFFNER.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$2777 in module SB_DFFNESR.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$2774 in module SB_DFFNS.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$2771 in module SB_DFFNSS.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$2768 in module SB_DFFNR.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$2765 in module SB_DFFNSR.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$2757 in module SB_DFFES.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$2752 in module SB_DFFESS.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$2748 in module SB_DFFER.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$2743 in module SB_DFFESR.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$2740 in module SB_DFFS.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$2737 in module SB_DFFSS.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$2734 in module SB_DFFR.
Marked 1 switch rules as full_case in process $proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$2731 in module SB_DFFSR.
Marked 5 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4288$2381 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4274$2380 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4246$2369 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4239$2368 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4232$2367 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4224$2366 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4217$2365 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4208$2364 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4199$2363 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4190$2362 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4117$2295 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4108$2292 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4099$2291 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4077$2287 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4063$2286 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4049$2281 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4029$2268 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4022$2267 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4013$2263 in module VexRiscv.
Marked 17 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3963$2258 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3950$2256 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3939$2255 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3932$2254 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3925$2253 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3914$2249 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3900$2245 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3890$2244 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3880$2243 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3864$2237 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3808$2229 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3773$2227 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3758$2224 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3679$2220 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3667$2213 in module VexRiscv.
Marked 10 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3631$2204 in module VexRiscv.
Marked 10 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3603$2202 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3523$2194 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3506$2193 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3441$2190 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3427$2189 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3413$2185 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3404$2183 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3350$2167 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3283$2160 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3272$2159 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3262$2156 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3248$2155 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3228$2150 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3213$2149 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3200$2138 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3183$2134 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3173$2133 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3106$2116 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3061$2109 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3025$2105 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3002$2090 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2991$2086 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2980$2082 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2970$2081 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2958$2078 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2946$2076 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2939$2075 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2928$2073 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2901$2066 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2891$2065 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2882$2063 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2869$2061 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2855$2060 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2847$2059 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2832$2058 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2825$2057 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2815$2056 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2802$2046 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2795$2045 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2784$2044 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2771$2036 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2764$2035 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2756$2034 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2743$2024 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2736$2021 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2726$2020 in module VexRiscv.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2716$2019 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2707$2018 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2700$2017 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2652$2007 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2644$2005 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2636$2003 in module VexRiscv.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2599$2002 in module VexRiscv.
Marked 11 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2568$2000 in module VexRiscv.
Marked 11 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2538$1998 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2525$1997 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1765$1977 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1713$1970 in module VexRiscv.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:264$1773 in module InstructionCache.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:219$1752 in module InstructionCache.
Marked 3 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:203$1747 in module InstructionCache.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:194$1745 in module InstructionCache.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:186$1744 in module InstructionCache.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:179$1743 in module InstructionCache.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:167$1734 in module InstructionCache.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:155$1725 in module InstructionCache.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:307$1657 in module vid_top.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:239$1636 in module vid_top.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:231$1633 in module vid_top.
Marked 2 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:200$1628 in module vid_top.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:178$1625 in module vid_top.
Marked 16 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557 in module $paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:74$4053 in module $paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:57$4050 in module $paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:50$4047 in module $paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:294$3451 in module $paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:241$3428 in module $paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:175$3395 in module $paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.
Marked 7 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:137$3390 in module $paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.
Marked 1 switch rules as full_case in process $proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:130$3389 in module $paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.
Removed a total of 9 dead cases.

63.3.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 72 redundant assignments.
Promoted 785 assignments to connections.

63.3.4. Executing PROC_INIT pass (extract init attributes).
Found init rule in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2794'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2790'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2785'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2781'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2776'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2773'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2770'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2767'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2764'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2762'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2760'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2756'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2751'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2747'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2742'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2739'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2736'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2733'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2730'.
  Set init value: \Q = 1'0
Found init rule in `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2728'.
  Set init value: \Q = 1'0
Found init rule in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1161$2551'.
  Set init value: \CsrPlugin_minstret = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1160$2550'.
  Set init value: \CsrPlugin_mcycle = 64'0000000000000000000000000000000000000000000000000000000000000000
Found init rule in `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:32$4072'.
  Set init value: \rst_cnt = 4'1000

63.3.5. Executing PROC_ARST pass (detect async resets in processes).
Found async reset \rst in `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:503$4617'.
Found async reset \rst in `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:167$4513'.
Found async reset \rst in `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:58$4440'.
Found async reset \rst in `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:35$4429'.
Found async reset \rst in `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:70$4411'.
Found async reset \rst in `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:116$3982'.
Found async reset \rst in `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:108$3976'.
Found async reset \rst in `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:95$3974'.
Found async reset \rst in `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:83$3965'.
Found async reset \rst in `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:67$3959'.
Found async reset \rst in `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:179$3945'.
Found async reset \rst in `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:141$3942'.
Found async reset \rst in `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:135$3941'.
Found async reset \rst in `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:121$3936'.
Found async reset \rst in `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:102$3933'.
Found async reset \rst in `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:96$3932'.
Found async reset \rst in `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:64$3884'.
Found async reset \rst in `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:57$3882'.
Found async reset \rst in `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:64$3871'.
Found async reset \rst in `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:57$3869'.
Found async reset \rst in `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:154$2939'.
Found async reset \rst in `$paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_rgb_wb.v:94$2932'.
Found async reset \S in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$2791'.
Found async reset \R in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$2782'.
Found async reset \S in `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$2774'.
Found async reset \R in `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$2768'.
Found async reset \S in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$2757'.
Found async reset \R in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$2748'.
Found async reset \S in `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$2740'.
Found async reset \R in `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$2734'.
Found async reset \reset in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
Found async reset \reset in `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:264$1773'.
Found async reset \pll_lock in `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:74$4053'.
Found async reset \pll_lock in `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:57$4050'.
Found async reset \pll_lock in `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:50$4047'.

63.3.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 1 switch.
<suppressed ~548 debug messages>

63.3.7. Executing PROC_MUX pass (convert decision trees to multiplexers).
Creating decoders for process `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4334'.
Creating decoders for process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4660'.
Creating decoders for process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4656'.
Creating decoders for process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4652'.
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4639'.
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4631'.
     1/1: $1$mem2reg_rd$\way_tag$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:344$4512_DATA[11:0]$4633
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4628'.
     1/1: $1$mem2reg_rd$\way_dirty$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:343$4511_DATA[0:0]$4630
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4625'.
     1/1: $1$mem2reg_rd$\way_valid$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:342$4510_DATA[0:0]$4627
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:503$4617'.
     1/2: $0\resp_nak[0:0]
     2/2: $0\resp_ack[0:0]
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:476$4615'.
     1/5: $1\dm_we[0:0]
     2/5: $1\dm_wmsk[3:0]
     3/5: $1\dm_wdata[31:0]
     4/5: $1\dm_re[0:0]
     5/5: $1\dm_addr[13:0]
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:441$4602'.
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:396$4577'.
     1/25: $6\way_age_nxt[3][1:0]
     2/25: $5\way_age_nxt[3][1:0]
     3/25: $6\way_age_nxt[2][1:0]
     4/25: $5\way_age_nxt[2][1:0]
     5/25: $6\way_age_nxt[1][1:0]
     6/25: $5\way_age_nxt[1][1:0]
     7/25: $6\way_age_nxt[0][1:0]
     8/25: $5\way_age_nxt[0][1:0]
     9/25: $4\way_age_nxt[3][1:0]
    10/25: $3\way_age_nxt[3][1:0]
    11/25: $2\way_age_nxt[3][1:0]
    12/25: $4\way_age_nxt[2][1:0]
    13/25: $3\way_age_nxt[2][1:0]
    14/25: $2\way_age_nxt[2][1:0]
    15/25: $4\way_age_nxt[1][1:0]
    16/25: $3\way_age_nxt[1][1:0]
    17/25: $2\way_age_nxt[1][1:0]
    18/25: $4\way_age_nxt[0][1:0]
    19/25: $3\way_age_nxt[0][1:0]
    20/25: $2\way_age_nxt[0][1:0]
    21/25: $1\age_next.w[31:0]
    22/25: $1\way_age_nxt[3][1:0]
    23/25: $1\way_age_nxt[2][1:0]
    24/25: $1\way_age_nxt[1][1:0]
    25/25: $1\way_age_nxt[0][1:0]
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
     1/17: $1\dirty_next.w[31:0]
     2/17: $1\way_dirty_we[3][0:0]
     3/17: $1\way_dirty_nxt[3][0:0]
     4/17: $1\way_valid_we[3][0:0]
     5/17: $1\way_valid_nxt[3][0:0]
     6/17: $1\way_dirty_we[2][0:0]
     7/17: $1\way_dirty_nxt[2][0:0]
     8/17: $1\way_valid_we[2][0:0]
     9/17: $1\way_valid_nxt[2][0:0]
    10/17: $1\way_dirty_we[1][0:0]
    11/17: $1\way_dirty_nxt[1][0:0]
    12/17: $1\way_valid_we[1][0:0]
    13/17: $1\way_valid_nxt[1][0:0]
    14/17: $1\way_dirty_we[0][0:0]
    15/17: $1\way_dirty_nxt[0][0:0]
    16/17: $1\way_valid_we[0][0:0]
    17/17: $1\way_valid_nxt[0][0:0]
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:347$4556'.
     1/3: $0\ev_tag_r[11:0]
     2/3: $0\ev_valid_r[0:0]
     3/3: $0\ev_way_r[1:0]
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:330$4546'.
     1/3: $3\ev_way[1:0]
     2/3: $2\ev_way[1:0]
     3/3: $1\ev_way[1:0]
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:309$4541'.
     1/3: $3\lu_hit_way[1:0]
     2/3: $2\lu_hit_way[1:0]
     3/3: $1\lu_hit_way[1:0]
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:237$4532'.
     1/1: $0\req_addr[23:0]
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:220$4524'.
     1/1: $0\cnt_ofs[2:0]
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:174$4514'.
     1/5: $5\ctrl_state_nxt[1:0]
     2/5: $4\ctrl_state_nxt[1:0]
     3/5: $3\ctrl_state_nxt[1:0]
     4/5: $2\ctrl_state_nxt[1:0]
     5/5: $1\ctrl_state_nxt[1:0]
Creating decoders for process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:167$4513'.
     1/1: $0\ctrl_state[1:0]
Creating decoders for process `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:63$4445'.
Creating decoders for process `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:63$4444'.
Creating decoders for process `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:63$4443'.
Creating decoders for process `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:58$4442'.
Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:67$4441'.
Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:58$4440'.
     1/1: $0\shift[9:0]
Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:51$4437'.
     1/1: $0\bit_cnt[4:0]
Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:42$4433'.
     1/1: $0\div_cnt[12:0]
Creating decoders for process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:35$4429'.
     1/1: $0\active[0:0]
Creating decoders for process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:102$4423'.
Creating decoders for process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:95$4422'.
     1/1: $0\shift[8:0]
Creating decoders for process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:88$4419'.
     1/1: $0\bit_cnt[4:0]
Creating decoders for process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:77$4415'.
     1/1: $0\div_cnt[12:0]
Creating decoders for process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:70$4411'.
     1/1: $0\active[0:0]
Creating decoders for process `$paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:39$4400'.
     1/4: $1$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4407
     2/4: $1$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_DATA[7:0]$4406
     3/4: $1$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_ADDR[8:0]$4405
     4/4: $0\rd_data[7:0]
Creating decoders for process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:116$3982'.
     1/1: $0\rd_valid[0:0]
Creating decoders for process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:108$3976'.
     1/1: $0\ram_rd_addr[8:0]
Creating decoders for process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:95$3974'.
     1/1: $0\ram_wr_addr[8:0]
Creating decoders for process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:83$3965'.
     1/1: $0\full[0:0]
Creating decoders for process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:67$3959'.
     1/1: $0\level[9:0]
Creating decoders for process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:179$3945'.
     1/7: $0\vid_v_last[0:0]
     2/7: $0\vid_v_first[0:0]
     3/7: $0\vid_h_last[0:0]
     4/7: $0\vid_h_first[0:0]
     5/7: $0\vid_active[0:0]
     6/7: $0\vid_vsync[0:0]
     7/7: $0\vid_hsync[0:0]
Creating decoders for process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:147$3944'.
     1/2: $2\v_mux[9:0]
     2/2: $1\v_mux[9:0]
Creating decoders for process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:141$3942'.
     1/1: $0\v_zone[1:0]
Creating decoders for process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:135$3941'.
     1/1: $0\v_first[0:0]
Creating decoders for process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:132$3940'.
Creating decoders for process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:121$3936'.
     1/1: $0\h_cnt[10:0]
Creating decoders for process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:108$3935'.
     1/2: $2\h_mux[10:0]
     2/2: $1\h_mux[10:0]
Creating decoders for process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:102$3933'.
     1/1: $0\h_zone[1:0]
Creating decoders for process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:96$3932'.
     1/1: $0\h_first[0:0]
Creating decoders for process `$paramod\delay_bit\DELAY=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:30$3930'.
Creating decoders for process `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:0$3893'.
Creating decoders for process `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:64$3884'.
     1/1: $0\stage[1].l_valid[0:0]
Creating decoders for process `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:57$3882'.
     1/1: $0\stage[1].l_data[35:0]
Creating decoders for process `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:0$3880'.
Creating decoders for process `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:64$3871'.
     1/1: $0\stage[1].l_valid[0:0]
Creating decoders for process `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:57$3869'.
     1/1: $0\stage[1].l_data[31:0]
Creating decoders for process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:53$3514'.
Creating decoders for process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:95$3509'.
     1/2: $0\fall[0:0]
     2/2: $0\rise[0:0]
Creating decoders for process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:80$3505'.
     1/1: $0\state[0:0]
Creating decoders for process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:70$3501'.
     1/1: $0\cnt[1:0]
Creating decoders for process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:60$3493'.
     1/2: $2\cnt_move[1:0]
     2/2: $1\cnt_move[1:0]
Creating decoders for process `\top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/top.v:0$3492'.
Creating decoders for process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
     1/12: $1$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_EN[31:0]$3386
     2/12: $1$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_DATA[31:0]$3385
     3/12: $1$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_ADDR[7:0]$3384
     4/12: $1$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_EN[31:0]$3381
     5/12: $1$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_DATA[31:0]$3380
     6/12: $1$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_ADDR[7:0]$3379
     7/12: $1$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_EN[31:0]$3376
     8/12: $1$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_DATA[31:0]$3375
     9/12: $1$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_ADDR[7:0]$3374
    10/12: $1$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_EN[31:0]$3371
    11/12: $1$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_DATA[31:0]$3370
    12/12: $1$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_ADDR[7:0]$3369
Creating decoders for process `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_ram.v:0$4452'.
Creating decoders for process `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_ram.v:114$4450'.
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:615$3181'.
     1/12: $5$lookahead\phy_cs_o$3180[1:0]$3211
     2/12: $4$lookahead\phy_cs_o$3180[1:0]$3202
     3/12: $4$bitselwrite$pos$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:627$2979[1:0]$3201
     4/12: $3$lookahead\phy_cs_o$3180[1:0]$3193
     5/12: $3$bitselwrite$pos$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:625$2978[1:0]$3191
     6/12: $3$bitselwrite$pos$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:627$2979[1:0]$3192
     7/12: $2$lookahead\phy_cs_o$3180[1:0]$3190
     8/12: $2$bitselwrite$pos$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:627$2979[1:0]$3189
     9/12: $2$bitselwrite$pos$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:625$2978[1:0]$3188
    10/12: $1$lookahead\phy_cs_o$3180[1:0]$3187
    11/12: $1$bitselwrite$pos$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:627$2979[1:0]$3186
    12/12: $1$bitselwrite$pos$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:625$2978[1:0]$3185
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
     1/29: $1\phy2shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:781$2987.$result[31:0]$3175 [31:4]
     2/29: $1\phy2shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:781$2987.$result[31:0]$3175 [3:0]
     3/29: $0\si_data_n[31:0]
     4/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.chan[31:0]$3172
     5/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.t[31:0]$3173
     6/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.io[31:0]$3174
     7/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [14]
     8/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [13]
     9/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [12]
    10/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [11]
    11/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [10]
    12/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [9]
    13/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [8]
    14/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [7]
    15/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [6]
    16/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [5]
    17/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [4]
    18/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [3]
    19/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [2]
    20/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [1]
    21/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [0]
    22/29: $2\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:16]$3179
    23/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [15]
    24/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.phy[15:0]$3171
    25/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.prev[31:0]$3170
    26/29: $1\phy2shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:781$2987.chan[31:0]$3178
    27/29: $1\phy2shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:781$2987.phy[15:0]$3177
    28/29: $1\phy2shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:781$2987.prev[31:0]$3176
    29/29: $1\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result[31:0]$3169 [31:16]
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:758$3151'.
     1/1: $0\si_dst_1[1:0]
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
     1/56: $1\shift2phy_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:748$2985.$result[15:0]$3147 [15:4]
     2/56: $1\shift2phy_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:748$2985.chan[31:0]$3150
     3/56: $2\phy_io_o[15:0]
     4/56: $1\shift2phy_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:748$2985.$result[15:0]$3147 [3:0]
     5/56: $1\shift2phy_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:748$2985.base[15:0]$3149
     6/56: $1\shift2phy_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:748$2985.shift[31:0]$3148
     7/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [15]
     8/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [14]
     9/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [10]
    10/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [6]
    11/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [2]
    12/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [13]
    13/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [9]
    14/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [5]
    15/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [1]
    16/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [12]
    17/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [3]
    18/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [8]
    19/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [11]
    20/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [4]
    21/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [7]
    22/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result[15:0]$3141 [0]
    23/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.chan[31:0]$3138
    24/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.t[31:0]$3140
    25/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.io[31:0]$3139
    26/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [14]
    27/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [10]
    28/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [6]
    29/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [2]
    30/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [13]
    31/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [9]
    32/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [5]
    33/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [1]
    34/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [12]
    35/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [8]
    36/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [4]
    37/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [0]
    38/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [11]
    39/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [7]
    40/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [3]
    41/56: $1\phy_io_o[15:0]
    42/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.shift[31:0]$3137
    43/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.t[31:0]$3145
    44/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.io[31:0]$3144
    45/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.chan[31:0]$3143
    46/56: $1\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.shift[31:0]$3142
    47/56: $1\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result[15:0]$3136 [15]
    48/56: $2\phy_io_oe[3:0]
    49/56: $2\io_ctrl.i[31:0]
    50/56: $2\phy_clk_o[3:0] [3]
    51/56: $2\phy_clk_o[3:0] [2]
    52/56: $2\phy_clk_o[3:0] [1]
    53/56: $2\phy_clk_o[3:0] [0]
    54/56: $1\phy_io_oe[3:0]
    55/56: $1\io_ctrl.i[31:0]
    56/56: $1\phy_clk_o[3:0]
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:700$3085'.
     1/12: $2\shift_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:705$2982.$result[31:0]$3104
     2/12: $2\shift_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:704$2981.chan[31:0]$3103
     3/12: $2\shift_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:704$2981.$result[31:0]$3102
     4/12: $0\so_data[31:0]
     5/12: $1\shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:703$2980.chan[31:0]$3096
     6/12: $1\shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:703$2980.$result[31:0]$3094
     7/12: $1\shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:703$2980.shift[31:0]$3095
     8/12: $1\shift_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:705$2982.shift[31:0]$3101
     9/12: $1\shift_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:705$2982.$result[31:0]$3100
    10/12: $1\shift_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:704$2981.chan[31:0]$3099
    11/12: $1\shift_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:704$2981.shift[31:0]$3098
    12/12: $1\shift_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:704$2981.$result[31:0]$3097
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:691$3083'.
     1/1: $0\so_cnt[5:0]
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:684$3082'.
     1/2: $0\so_dst[1:0]
     2/2: $0\so_mode[1:0]
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:677$3077'.
     1/1: $0\so_valid[0:0]
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:544$3063'.
     1/9: $2$mem2reg_rd$\cmd_len_rom$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:570$2988_DATA[5:0]$3069
     2/9: { $2\so_ld_mode[1:0] $2\so_ld_dst[1:0] }
     3/9: $1\so_ld_src[1:0]
     4/9: $1\so_ld_cnt[5:0]
     5/9: $1\so_ld_dst[1:0]
     6/9: $1\so_ld_mode[1:0]
     7/9: $1\so_ld_valid[0:0]
     8/9: $1$mem2reg_rd$\cmd_len_rom$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:570$2988_DATA[5:0]$3067
     9/9: $1$mem2reg_rd$\cmd_len_rom$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:570$2988_ADDR[3:0]$3066
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:515$3051'.
     1/1: $0\pause_cnt[3:0]
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:506$3043'.
     1/1: $0\xfer_cnt[7:0]
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:466$3036'.
     1/9: $9\state_nxt[2:0]
     2/9: $8\state_nxt[2:0]
     3/9: $7\state_nxt[2:0]
     4/9: $6\state_nxt[2:0]
     5/9: $5\state_nxt[2:0]
     6/9: $4\state_nxt[2:0]
     7/9: $3\state_nxt[2:0]
     8/9: $2\state_nxt[2:0]
     9/9: $1\state_nxt[2:0]
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:459$3035'.
     1/1: $0\state[2:0]
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:447$3029'.
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:373$3025'.
     1/1: $0\wb_rdata[31:0]
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:363$3017'.
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:359$3010'.
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:344$3008'.
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:337$3005'.
     1/1: $0\ectl_cs[1:0]
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:331$3001'.
     1/1: $0\ectl_req[0:0]
Creating decoders for process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:314$2989'.
     1/1: $0\wb_ack[0:0]
Creating decoders for process `$paramod$9a9e2282df54acafd6229f692355382480e5c2ad\qpi_phy_ice40_4x.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_phy_ice40_4x.v:163$2977'.
Creating decoders for process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:193$2973'.
     1/1: $0\uart_div[11:0]
Creating decoders for process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:185$2971'.
     1/1: $0\ub_rdata[31:0]
Creating decoders for process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:177$2961'.
     1/1: $0\ub_ack[0:0]
Creating decoders for process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:164$2944'.
     1/4: $0\ub_wr_div[0:0]
     2/4: $0\ub_wr_data[0:0]
     3/4: $0\ub_rd_ctrl[0:0]
     4/4: $0\ub_rd_data[0:0]
Creating decoders for process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:154$2939'.
     1/1: $0\urf_overflow[0:0]
Creating decoders for process `$paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_rgb_wb.v:94$2932'.
     1/1: $0\led_ctrl[4:0]
Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2794'.
Creating decoders for process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$2791'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2790'.
Creating decoders for process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$2786'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2785'.
Creating decoders for process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$2782'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2781'.
Creating decoders for process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$2777'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2776'.
Creating decoders for process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$2774'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2773'.
Creating decoders for process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$2771'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2770'.
Creating decoders for process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$2768'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2767'.
Creating decoders for process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$2765'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2764'.
Creating decoders for process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$2763'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2762'.
Creating decoders for process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$2761'.
Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2760'.
Creating decoders for process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$2757'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2756'.
Creating decoders for process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$2752'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2751'.
Creating decoders for process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$2748'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2747'.
Creating decoders for process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$2743'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2742'.
Creating decoders for process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$2740'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2739'.
Creating decoders for process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$2737'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2736'.
Creating decoders for process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$2734'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2733'.
Creating decoders for process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$2731'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2730'.
Creating decoders for process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$2729'.
     1/1: $0\Q[0:0]
Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2728'.
Creating decoders for process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$2727'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1161$2551'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1160$2550'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
     1/104: $0\memory_DivPlugin_rs1[32:0] [32]
     2/104: $0\memory_DivPlugin_accumulator[64:0] [31:0]
     3/104: $0\memory_DivPlugin_accumulator[64:0] [64:32]
     4/104: $0\dBus_cmd_halfPipe_regs_payload_size[1:0]
     5/104: $0\dBus_cmd_halfPipe_regs_payload_data[31:0]
     6/104: $0\dBus_cmd_halfPipe_regs_payload_address[31:0]
     7/104: $0\dBus_cmd_halfPipe_regs_payload_wr[0:0]
     8/104: $0\execute_CsrPlugin_csr_4032[0:0]
     9/104: $0\execute_CsrPlugin_csr_3008[0:0]
    10/104: $0\execute_CsrPlugin_csr_835[0:0]
    11/104: $0\execute_CsrPlugin_csr_834[0:0]
    12/104: $0\execute_CsrPlugin_csr_833[0:0]
    13/104: $0\execute_CsrPlugin_csr_773[0:0]
    14/104: $0\execute_CsrPlugin_csr_772[0:0]
    15/104: $0\execute_CsrPlugin_csr_836[0:0]
    16/104: $0\execute_CsrPlugin_csr_768[0:0]
    17/104: $0\execute_CsrPlugin_csr_1984[0:0]
    18/104: $0\memory_to_writeBack_MEMORY_READ_DATA[31:0]
    19/104: $0\execute_to_memory_MUL_LH[33:0]
    20/104: $0\decode_to_execute_SRC2_CTRL[1:0]
    21/104: $0\decode_to_execute_IS_RS2_SIGNED[0:0]
    22/104: $0\decode_to_execute_IS_RS1_SIGNED[0:0]
    23/104: $0\memory_to_writeBack_MEMORY_ADDRESS_LOW[1:0]
    24/104: $0\execute_to_memory_MEMORY_ADDRESS_LOW[1:0]
    25/104: $0\decode_to_execute_SRC1_CTRL[1:0]
    26/104: $0\decode_to_execute_RS2[31:0]
    27/104: $0\execute_to_memory_MMU_FAULT[0:0]
    28/104: $0\execute_to_memory_BRANCH_DO[0:0]
    29/104: $0\memory_to_writeBack_MUL_LOW[51:0]
    30/104: $0\decode_to_execute_BYPASSABLE_EXECUTE_STAGE[0:0]
    31/104: $0\memory_to_writeBack_ENV_CTRL[1:0]
    32/104: $0\execute_to_memory_ENV_CTRL[1:0]
    33/104: $0\decode_to_execute_ENV_CTRL[1:0]
    34/104: $0\execute_to_memory_BRANCH_CALC[31:0]
    35/104: $0\decode_to_execute_IS_CSR[0:0]
    36/104: $0\execute_to_memory_REGFILE_WRITE_DATA[31:0]
    37/104: $0\execute_to_memory_BYPASSABLE_MEMORY_STAGE[0:0]
    38/104: $0\decode_to_execute_BYPASSABLE_MEMORY_STAGE[0:0]
    39/104: $0\decode_to_execute_ALU_CTRL[1:0]
    40/104: $0\decode_to_execute_SRC_LESS_UNSIGNED[0:0]
    41/104: $0\decode_to_execute_CSR_WRITE_OPCODE[0:0]
    42/104: $0\memory_to_writeBack_PC[31:0]
    43/104: $0\execute_to_memory_PC[31:0]
    44/104: $0\decode_to_execute_PC[31:0]
    45/104: $0\memory_to_writeBack_REGFILE_WRITE_VALID[0:0]
    46/104: $0\execute_to_memory_REGFILE_WRITE_VALID[0:0]
    47/104: $0\decode_to_execute_REGFILE_WRITE_VALID[0:0]
    48/104: $0\execute_to_memory_MUL_HL[33:0]
    49/104: $0\execute_to_memory_IS_DIV[0:0]
    50/104: $0\decode_to_execute_IS_DIV[0:0]
    51/104: $0\decode_to_execute_ALU_BITWISE_CTRL[1:0]
    52/104: $0\execute_to_memory_SHIFT_CTRL[1:0]
    53/104: $0\decode_to_execute_SHIFT_CTRL[1:0]
    54/104: $0\memory_to_writeBack_FORMAL_PC_NEXT[31:0]
    55/104: $0\execute_to_memory_FORMAL_PC_NEXT[31:0]
    56/104: $0\decode_to_execute_FORMAL_PC_NEXT[31:0]
    57/104: $0\execute_to_memory_SHIFT_RIGHT[31:0]
    58/104: $0\execute_to_memory_INSTRUCTION[31:0]
    59/104: $0\decode_to_execute_INSTRUCTION[31:0]
    60/104: $0\decode_to_execute_BRANCH_CTRL[1:0]
    61/104: $0\decode_to_execute_SRC_USE_SUB_LESS[0:0]
    62/104: $0\execute_to_memory_MMU_RSP_refilling[0:0]
    63/104: $0\execute_to_memory_MMU_RSP_exception[0:0]
    64/104: $0\execute_to_memory_MMU_RSP_allowExecute[0:0]
    65/104: $0\execute_to_memory_MMU_RSP_allowWrite[0:0]
    66/104: $0\execute_to_memory_MMU_RSP_allowRead[0:0]
    67/104: $0\execute_to_memory_MMU_RSP_isIoAccess[0:0]
    68/104: $0\execute_to_memory_MMU_RSP_physicalAddress[31:0]
    69/104: $0\execute_to_memory_MUL_LL[31:0]
    70/104: $0\decode_to_execute_SRC2_FORCE_ZERO[0:0]
    71/104: $0\decode_to_execute_CSR_READ_OPCODE[0:0]
    72/104: $0\memory_to_writeBack_IS_MUL[0:0]
    73/104: $0\execute_to_memory_IS_MUL[0:0]
    74/104: $0\decode_to_execute_IS_MUL[0:0]
    75/104: $0\memory_to_writeBack_MEMORY_ENABLE[0:0]
    76/104: $0\execute_to_memory_MEMORY_ENABLE[0:0]
    77/104: $0\decode_to_execute_MEMORY_ENABLE[0:0]
    78/104: $0\memory_to_writeBack_MEMORY_STORE[0:0]
    79/104: $0\execute_to_memory_MEMORY_STORE[0:0]
    80/104: $0\decode_to_execute_MEMORY_STORE[0:0]
    81/104: $0\decode_to_execute_PREDICTION_HAD_BRANCHED2[0:0]
    82/104: $0\decode_to_execute_RS1[31:0]
    83/104: $0\memory_to_writeBack_MUL_HH[33:0]
    84/104: $0\execute_to_memory_MUL_HH[33:0]
    85/104: $0\memory_DivPlugin_div_result[31:0]
    86/104: $0\memory_DivPlugin_div_done[0:0]
    87/104: $0\memory_DivPlugin_div_needRevert[0:0]
    88/104: $0\memory_DivPlugin_rs1[32:0] [31:0]
    89/104: $0\memory_DivPlugin_rs2[31:0]
    90/104: $0\CsrPlugin_mip_MSIP[0:0]
    91/104: $0\CsrPlugin_interrupt_targetPrivilege[1:0]
    92/104: $0\CsrPlugin_interrupt_code[3:0]
    93/104: $0\CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[31:0]
    94/104: $0\CsrPlugin_exceptionPortCtrl_exceptionContext_code[3:0]
    95/104: $0\CsrPlugin_minstret[63:0]
    96/104: $0\CsrPlugin_mtval[31:0]
    97/104: $0\CsrPlugin_mcause_exceptionCode[3:0]
    98/104: $0\CsrPlugin_mcause_interrupt[0:0]
    99/104: $0\CsrPlugin_mepc[31:0]
   100/104: $0\CsrPlugin_mtvec_base[29:0]
   101/104: $0\CsrPlugin_mtvec_mode[1:0]
   102/104: $0\IBusCachedPlugin_s2_tightlyCoupledHit[0:0]
   103/104: $0\IBusCachedPlugin_s1_tightlyCoupledHit[0:0]
   104/104: $0\_zz_68_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
     1/41: $0\dBus_cmd_halfPipe_regs_ready[0:0]
     2/41: $0\dBus_cmd_halfPipe_regs_valid[0:0]
     3/41: $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack[0:0]
     4/41: $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory[0:0]
     5/41: $0\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute[0:0]
     6/41: $0\memory_DivPlugin_div_counter_value[5:0]
     7/41: $0\execute_CsrPlugin_wfiWake[0:0]
     8/41: $0\CsrPlugin_hadException[0:0]
     9/41: $0\CsrPlugin_interrupt_valid[0:0]
    10/41: $0\_zz_113_[0:0]
    11/41: $0\_zz_101_[0:0]
    12/41: $0\IBusCachedPlugin_fetchPc_booted[0:0]
    13/41: $0\memory_to_writeBack_REGFILE_WRITE_DATA[31:0]
    14/41: $0\memory_to_writeBack_INSTRUCTION[31:0]
    15/41: $0\_zz_146_[31:0]
    16/41: $0\CsrPlugin_pipelineLiberator_pcValids_2[0:0]
    17/41: $0\CsrPlugin_pipelineLiberator_pcValids_1[0:0]
    18/41: $0\CsrPlugin_pipelineLiberator_pcValids_0[0:0]
    19/41: $0\CsrPlugin_mie_MSIE[0:0]
    20/41: $0\CsrPlugin_mie_MTIE[0:0]
    21/41: $0\CsrPlugin_mie_MEIE[0:0]
    22/41: $0\CsrPlugin_mstatus_MPP[1:0]
    23/41: $0\CsrPlugin_mstatus_MPIE[0:0]
    24/41: $0\CsrPlugin_mstatus_MIE[0:0]
    25/41: $0\RegFilePlugin_shadow_clear[0:0]
    26/41: $0\RegFilePlugin_shadow_read[0:0]
    27/41: $0\RegFilePlugin_shadow_write[0:0]
    28/41: $0\IBusCachedPlugin_rspCounter[31:0]
    29/41: $0\IBusCachedPlugin_injector_nextPcCalc_valids_4[0:0]
    30/41: $0\IBusCachedPlugin_injector_nextPcCalc_valids_3[0:0]
    31/41: $0\IBusCachedPlugin_injector_nextPcCalc_valids_2[0:0]
    32/41: $0\IBusCachedPlugin_injector_nextPcCalc_valids_1[0:0]
    33/41: $0\IBusCachedPlugin_injector_nextPcCalc_valids_0[0:0]
    34/41: $0\_zz_67_[0:0]
    35/41: $0\_zz_65_[0:0]
    36/41: $0\IBusCachedPlugin_fetchPc_inc[0:0]
    37/41: $0\IBusCachedPlugin_fetchPc_correctionReg[0:0]
    38/41: $0\IBusCachedPlugin_fetchPc_pcReg[31:0]
    39/41: $0\writeBack_arbitration_isValid[0:0]
    40/41: $0\memory_arbitration_isValid[0:0]
    41/41: $0\execute_arbitration_isValid[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4288$2381'.
     1/1: $1\dBusWishbone_SEL[3:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4274$2380'.
     1/1: $1\_zz_156_[3:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4246$2369'.
     1/1: $1\_zz_155_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4239$2368'.
     1/1: $1\_zz_154_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4232$2367'.
     1/1: $1\_zz_153_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4224$2366'.
     1/2: $1\_zz_152_[3:0]
     2/2: $2\_zz_152_[31:31]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4217$2365'.
     1/1: $1\_zz_151_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4208$2364'.
     1/3: $1\_zz_150_[3:3]
     2/3: $2\_zz_150_[7:7]
     3/3: $3\_zz_150_[11:11]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4199$2363'.
     1/3: $1\_zz_149_[3:3]
     2/3: $2\_zz_149_[7:7]
     3/3: $3\_zz_149_[11:11]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4190$2362'.
     1/3: $1\_zz_148_[3:3]
     2/3: $2\_zz_148_[7:7]
     3/3: $3\_zz_148_[12:11]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4136$2305'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4117$2295'.
     1/2: $2\memory_DivPlugin_div_counter_valueNext[5:0]
     2/2: $1\memory_DivPlugin_div_counter_valueNext[5:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4108$2292'.
     1/1: $1\memory_DivPlugin_div_counter_willClear[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4099$2291'.
     1/2: $2\memory_DivPlugin_div_counter_willIncrement[0:0]
     2/2: $1\memory_DivPlugin_div_counter_willIncrement[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4077$2287'.
     1/1: $1\execute_MulPlugin_bSigned[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4063$2286'.
     1/1: $1\execute_MulPlugin_aSigned[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4049$2281'.
     1/1: $1\execute_CsrPlugin_writeData[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4029$2268'.
     1/2: $2\CsrPlugin_selfException_payload_code[3:0]
     2/2: $1\CsrPlugin_selfException_payload_code[3:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4022$2267'.
     1/1: $1\CsrPlugin_selfException_valid[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4013$2263'.
     1/2: $2\execute_CsrPlugin_illegalInstruction[0:0]
     2/2: $1\execute_CsrPlugin_illegalInstruction[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3963$2258'.
     1/17: $17\execute_CsrPlugin_illegalAccess[0:0]
     2/17: $16\execute_CsrPlugin_illegalAccess[0:0]
     3/17: $15\execute_CsrPlugin_illegalAccess[0:0]
     4/17: $14\execute_CsrPlugin_illegalAccess[0:0]
     5/17: $13\execute_CsrPlugin_illegalAccess[0:0]
     6/17: $12\execute_CsrPlugin_illegalAccess[0:0]
     7/17: $11\execute_CsrPlugin_illegalAccess[0:0]
     8/17: $10\execute_CsrPlugin_illegalAccess[0:0]
     9/17: $9\execute_CsrPlugin_illegalAccess[0:0]
    10/17: $8\execute_CsrPlugin_illegalAccess[0:0]
    11/17: $7\execute_CsrPlugin_illegalAccess[0:0]
    12/17: $6\execute_CsrPlugin_illegalAccess[0:0]
    13/17: $5\execute_CsrPlugin_illegalAccess[0:0]
    14/17: $4\execute_CsrPlugin_illegalAccess[0:0]
    15/17: $3\execute_CsrPlugin_illegalAccess[0:0]
    16/17: $2\execute_CsrPlugin_illegalAccess[0:0]
    17/17: $1\execute_CsrPlugin_illegalAccess[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3950$2256'.
     1/1: $1\CsrPlugin_xtvec_base[29:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3939$2255'.
     1/1: $1\CsrPlugin_xtvec_mode[1:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3932$2254'.
     1/1: $1\CsrPlugin_trapCause[3:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3925$2253'.
     1/1: $1\CsrPlugin_targetPrivilege[1:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3914$2249'.
     1/2: $2\CsrPlugin_pipelineLiberator_done[0:0]
     2/2: $1\CsrPlugin_pipelineLiberator_done[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3900$2245'.
     1/1: $1\CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3890$2244'.
     1/2: $2\CsrPlugin_exceptionPortCtrl_exceptionValids_memory[0:0]
     2/2: $1\CsrPlugin_exceptionPortCtrl_exceptionValids_memory[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3880$2243'.
     1/2: $2\CsrPlugin_exceptionPortCtrl_exceptionValids_execute[0:0]
     2/2: $1\CsrPlugin_exceptionPortCtrl_exceptionValids_execute[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3864$2237'.
     1/1: $1\CsrPlugin_privilege[1:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3838$2233'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3823$2232'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3808$2229'.
     1/2: $2\execute_BranchPlugin_branch_src2[31:0]
     2/2: $1\execute_BranchPlugin_branch_src2[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3785$2228'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3773$2227'.
     1/1: $1\execute_BranchPlugin_branch_src1[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3758$2224'.
     1/1: $1\_zz_131_[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3736$2223'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3721$2222'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3697$2221'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3679$2220'.
     1/1: $1\_zz_124_[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3667$2213'.
     1/3: $3\_zz_123_[0:0]
     2/3: $2\_zz_123_[0:0]
     3/3: $1\_zz_123_[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3631$2204'.
     1/10: $10\_zz_112_[0:0]
     2/10: $9\_zz_112_[0:0]
     3/10: $8\_zz_112_[0:0]
     4/10: $7\_zz_112_[0:0]
     5/10: $6\_zz_112_[0:0]
     6/10: $5\_zz_112_[0:0]
     7/10: $4\_zz_112_[0:0]
     8/10: $3\_zz_112_[0:0]
     9/10: $2\_zz_112_[0:0]
    10/10: $1\_zz_112_[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3603$2202'.
     1/10: $10\_zz_111_[0:0]
     2/10: $9\_zz_111_[0:0]
     3/10: $8\_zz_111_[0:0]
     4/10: $7\_zz_111_[0:0]
     5/10: $6\_zz_111_[0:0]
     6/10: $5\_zz_111_[0:0]
     7/10: $4\_zz_111_[0:0]
     8/10: $3\_zz_111_[0:0]
     9/10: $2\_zz_111_[0:0]
    10/10: $1\_zz_111_[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3568$2201'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3532$2198'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3523$2194'.
     1/1: $1\execute_SrcPlugin_addSub[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3506$2193'.
     1/1: $1\_zz_108_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3483$2192'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3459$2191'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3441$2190'.
     1/1: $1\_zz_103_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3427$2189'.
     1/1: $1\_zz_102_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3413$2185'.
     1/1: $1\execute_IntAluPlugin_bitwise[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3404$2183'.
     1/1: $1\lastStageRegFileWrite_valid[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3350$2167'.
     1/1: $1\writeBack_DBusSimplePlugin_rspFormated[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3330$2166'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3301$2163'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3283$2160'.
     1/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [15:8]
     2/2: $1\writeBack_DBusSimplePlugin_rspShifted[15:0] [7:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3272$2159'.
     1/2: $2\DBusSimplePlugin_redoBranch_valid[0:0]
     2/2: $1\DBusSimplePlugin_redoBranch_valid[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3262$2156'.
     1/2: $2\DBusSimplePlugin_memoryExceptionPort_payload_code[3:0]
     2/2: $1\DBusSimplePlugin_memoryExceptionPort_payload_code[3:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3248$2155'.
     1/3: $3\DBusSimplePlugin_memoryExceptionPort_valid[0:0]
     2/3: $2\DBusSimplePlugin_memoryExceptionPort_valid[0:0]
     3/3: $1\DBusSimplePlugin_memoryExceptionPort_valid[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3228$2150'.
     1/1: $1\_zz_83_[3:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3213$2149'.
     1/1: $1\_zz_82_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3200$2138'.
     1/2: $2\execute_DBusSimplePlugin_skipCmd[0:0]
     2/2: $1\execute_DBusSimplePlugin_skipCmd[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3183$2134'.
     1/1: $1\_zz_164_[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3173$2133'.
     1/2: $2\IBusCachedPlugin_rsp_redoFetch[0:0]
     2/2: $1\IBusCachedPlugin_rsp_redoFetch[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3158$2123'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3134$2119'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3119$2118'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3106$2116'.
     1/1: $1\_zz_75_[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3084$2115'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3069$2114'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3061$2109'.
     1/1: $1\IBusCachedPlugin_decodePrediction_cmd_hadBranch[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3039$2108'.
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3025$2105'.
     1/1: $1\IBusCachedPlugin_iBusRsp_readyForError[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3002$2090'.
     1/1: $1\IBusCachedPlugin_iBusRsp_stages_2_halt[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2991$2086'.
     1/1: $1\IBusCachedPlugin_iBusRsp_stages_1_halt[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2980$2082'.
     1/1: $1\IBusCachedPlugin_iBusRsp_stages_0_halt[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2970$2081'.
     1/1: $1\IBusCachedPlugin_iBusRsp_redoFetch[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2958$2078'.
     1/2: $2\IBusCachedPlugin_fetchPc_flushed[0:0]
     2/2: $1\IBusCachedPlugin_fetchPc_flushed[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2946$2076'.
     1/2: $2\IBusCachedPlugin_fetchPc_pc[31:0]
     2/2: $1\IBusCachedPlugin_fetchPc_pc[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2939$2075'.
     1/1: $1\IBusCachedPlugin_fetchPc_pcRegPropagate[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2928$2073'.
     1/2: $2\IBusCachedPlugin_fetchPc_correction[0:0]
     2/2: $1\IBusCachedPlugin_fetchPc_correction[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2901$2066'.
     1/3: $3\CsrPlugin_jumpInterface_payload[31:0]
     2/3: $2\CsrPlugin_jumpInterface_payload[31:0]
     3/3: $1\CsrPlugin_jumpInterface_payload[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2891$2065'.
     1/2: $2\CsrPlugin_jumpInterface_valid[0:0]
     2/2: $1\CsrPlugin_jumpInterface_valid[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2882$2063'.
     1/1: $1\IBusCachedPlugin_incomingInstruction[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2869$2061'.
     1/3: $3\IBusCachedPlugin_fetcherHalt[0:0]
     2/3: $2\IBusCachedPlugin_fetcherHalt[0:0]
     3/3: $1\IBusCachedPlugin_fetcherHalt[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2855$2060'.
     1/2: $2\writeBack_arbitration_flushNext[0:0]
     2/2: $1\writeBack_arbitration_flushNext[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2847$2059'.
     1/1: $1\writeBack_arbitration_removeIt[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2832$2058'.
     1/3: $3\memory_arbitration_flushNext[0:0]
     2/3: $2\memory_arbitration_flushNext[0:0]
     3/3: $1\memory_arbitration_flushNext[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2825$2057'.
     1/1: $1\memory_arbitration_flushIt[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2815$2056'.
     1/2: $2\memory_arbitration_removeIt[0:0]
     2/2: $1\memory_arbitration_removeIt[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2802$2046'.
     1/3: $3\memory_arbitration_haltItself[0:0]
     2/3: $2\memory_arbitration_haltItself[0:0]
     3/3: $1\memory_arbitration_haltItself[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2795$2045'.
     1/1: $1\execute_arbitration_flushNext[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2784$2044'.
     1/2: $2\execute_arbitration_removeIt[0:0]
     2/2: $1\execute_arbitration_removeIt[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2771$2036'.
     1/3: $3\execute_arbitration_haltItself[0:0]
     2/3: $2\execute_arbitration_haltItself[0:0]
     3/3: $1\execute_arbitration_haltItself[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2764$2035'.
     1/1: $1\decode_arbitration_flushNext[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2756$2034'.
     1/1: $1\decode_arbitration_removeIt[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2743$2024'.
     1/3: $3\decode_arbitration_haltByOther[0:0]
     2/3: $2\decode_arbitration_haltByOther[0:0]
     3/3: $1\decode_arbitration_haltByOther[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2736$2021'.
     1/1: $1\decode_arbitration_haltItself[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2726$2020'.
     1/1: $1\_zz_54_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2716$2019'.
     1/2: $2\_zz_53_[31:0]
     2/2: $1\_zz_53_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2707$2018'.
     1/1: $1\_zz_51__0[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2700$2017'.
     1/1: $1\_zz_51_[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2652$2007'.
     1/3: $3\_zz_50_[31:0]
     2/3: $2\_zz_50_[31:0]
     3/3: $1\_zz_50_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2644$2005'.
     1/1: $1\decode_REGFILE_WRITE_VALID[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2636$2003'.
     1/1: $1\_zz_42_[0:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2599$2002'.
     1/3: $3\_zz_32_[31:0]
     2/3: $2\_zz_32_[31:0]
     3/3: $1\_zz_32_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2568$2000'.
     1/11: $11\decode_RS1[31:0]
     2/11: $10\decode_RS1[31:0]
     3/11: $9\decode_RS1[31:0]
     4/11: $8\decode_RS1[31:0]
     5/11: $7\decode_RS1[31:0]
     6/11: $6\decode_RS1[31:0]
     7/11: $5\decode_RS1[31:0]
     8/11: $4\decode_RS1[31:0]
     9/11: $3\decode_RS1[31:0]
    10/11: $2\decode_RS1[31:0]
    11/11: $1\decode_RS1[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2538$1998'.
     1/11: $11\decode_RS2[31:0]
     2/11: $10\decode_RS2[31:0]
     3/11: $9\decode_RS2[31:0]
     4/11: $8\decode_RS2[31:0]
     5/11: $7\decode_RS2[31:0]
     6/11: $6\decode_RS2[31:0]
     7/11: $5\decode_RS2[31:0]
     8/11: $4\decode_RS2[31:0]
     9/11: $3\decode_RS2[31:0]
    10/11: $2\decode_RS2[31:0]
    11/11: $1\decode_RS2[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2525$1997'.
     1/1: $1\_zz_31_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1765$1977'.
     1/1: $1\_zz_167_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1713$1970'.
     1/3: $1$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1976
     2/3: $1$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_DATA[31:0]$1975
     3/3: $1$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_ADDR[5:0]$1974
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1707$1968'.
     1/1: $0\_zz_166_[31:0]
Creating decoders for process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1701$1966'.
     1/1: $0\_zz_165_[31:0]
Creating decoders for process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
     1/12: $0\decodeStage_hit_error[0:0]
     2/12: $0\decodeStage_hit_valid[0:0]
     3/12: $0\decodeStage_mmuRsp_refilling[0:0]
     4/12: $0\decodeStage_mmuRsp_exception[0:0]
     5/12: $0\decodeStage_mmuRsp_allowExecute[0:0]
     6/12: $0\decodeStage_mmuRsp_allowWrite[0:0]
     7/12: $0\decodeStage_mmuRsp_allowRead[0:0]
     8/12: $0\decodeStage_mmuRsp_isIoAccess[0:0]
     9/12: $0\decodeStage_mmuRsp_physicalAddress[31:0]
    10/12: $0\io_cpu_fetch_data_regNextWhen[31:0]
    11/12: $0\lineLoader_flushCounter[6:0]
    12/12: $0\lineLoader_address[31:0]
Creating decoders for process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:264$1773'.
     1/5: $0\lineLoader_wordIndex[2:0]
     2/5: $0\lineLoader_cmdSent[0:0]
     3/5: $0\lineLoader_flushPending[0:0]
     4/5: $0\lineLoader_hadError[0:0]
     5/5: $0\lineLoader_valid[0:0]
Creating decoders for process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:219$1752'.
     1/1: $1\lineLoader_wayToAllocate_willIncrement[0:0]
Creating decoders for process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:203$1747'.
     1/3: $3\io_cpu_prefetch_haltIt[0:0]
     2/3: $2\io_cpu_prefetch_haltIt[0:0]
     3/3: $1\io_cpu_prefetch_haltIt[0:0]
Creating decoders for process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:194$1745'.
     1/2: $2\lineLoader_fire[0:0]
     2/2: $1\lineLoader_fire[0:0]
Creating decoders for process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:186$1744'.
     1/1: $1\_zz_2_[0:0]
Creating decoders for process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:179$1743'.
     1/1: $1\_zz_1_[0:0]
Creating decoders for process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:173$1741'.
     1/1: $0\_zz_11_[31:0]
Creating decoders for process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:167$1734'.
     1/3: $1$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1740
     2/3: $1$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_DATA[31:0]$1739
     3/3: $1$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_ADDR[8:0]$1738
Creating decoders for process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:161$1732'.
     1/1: $0\_zz_10_[22:0]
Creating decoders for process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:155$1725'.
     1/3: $1$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1731
     2/3: $1$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_DATA[22:0]$1730
     3/3: $1$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_ADDR[5:0]$1729
Creating decoders for process `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4397'.
Creating decoders for process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:307$1657'.
     1/1: $1\wb_rdata[31:0]
Creating decoders for process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:303$1651'.
Creating decoders for process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:253$1644'.
     1/1: $0\pp_data_3[31:0]
Creating decoders for process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:250$1643'.
Creating decoders for process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:239$1636'.
     1/1: $0\pp_addr_cur_1[15:0]
Creating decoders for process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:231$1633'.
     1/1: $0\pp_addr_base_1[15:0]
Creating decoders for process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:224$1629'.
Creating decoders for process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:200$1628'.
     1/2: $0\pp_ydbl_1[0:0]
     2/2: $0\pp_yscale_state[3:0]
Creating decoders for process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:178$1625'.
     1/1: $0\vs_frame_cnt[15:0]
Creating decoders for process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:175$1620'.
Creating decoders for process `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4376'.
Creating decoders for process `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4355'.
Creating decoders for process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:0$3674'.
Creating decoders for process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:0$3673'.
Creating decoders for process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
     1/320: $8\mem_dm_w[7:0] [7]
     2/320: $8\mem_dm_w[7:0] [4]
     3/320: $8\mem_dm_w[7:0] [2]
     4/320: $8\mem_dm_w[7:0] [0]
     5/320: $8\mem_dm_w[7:0] [6]
     6/320: $8\mem_dm_w[7:0] [1]
     7/320: $8\mem_dm_w[7:0] [3]
     8/320: $8\mem_dm_w[7:0] [5]
     9/320: $8\mem_di_w[31:0] [31]
    10/320: $8\mem_di_w[31:0] [24]
    11/320: $8\mem_di_w[31:0] [22]
    12/320: $8\mem_di_w[31:0] [20]
    13/320: $8\mem_di_w[31:0] [18]
    14/320: $8\mem_di_w[31:0] [16]
    15/320: $8\mem_di_w[31:0] [14]
    16/320: $8\mem_di_w[31:0] [12]
    17/320: $8\mem_di_w[31:0] [10]
    18/320: $8\mem_di_w[31:0] [8]
    19/320: $8\mem_di_w[31:0] [6]
    20/320: $8\mem_di_w[31:0] [4]
    21/320: $8\mem_di_w[31:0] [2]
    22/320: $8\mem_di_w[31:0] [0]
    23/320: $8\mem_di_w[31:0] [30]
    24/320: $8\mem_di_w[31:0] [27]
    25/320: $8\mem_di_w[31:0] [23]
    26/320: $8\mem_di_w[31:0] [21]
    27/320: $8\mem_di_w[31:0] [17]
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    29/320: $8\mem_di_w[31:0] [9]
    30/320: $8\mem_di_w[31:0] [5]
    31/320: $8\mem_di_w[31:0] [1]
    32/320: $8\mem_di_w[31:0] [28]
    33/320: $8\mem_di_w[31:0] [26]
    34/320: $8\mem_di_w[31:0] [15]
    35/320: $8\mem_di_w[31:0] [7]
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    37/320: $8\mem_di_w[31:0] [19]
    38/320: $8\mem_di_w[31:0] [3]
    39/320: $8\mem_di_w[31:0] [25]
    40/320: $8\mem_di_w[31:0] [11]
    41/320: $7\mem_dm_w[7:0] [7]
    42/320: $7\mem_dm_w[7:0] [4]
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    44/320: $7\mem_dm_w[7:0] [0]
    45/320: $7\mem_dm_w[7:0] [6]
    46/320: $7\mem_dm_w[7:0] [1]
    47/320: $7\mem_dm_w[7:0] [3]
    48/320: $7\mem_dm_w[7:0] [5]
    49/320: $7\mem_di_w[31:0] [31]
    50/320: $7\mem_di_w[31:0] [24]
    51/320: $7\mem_di_w[31:0] [22]
    52/320: $7\mem_di_w[31:0] [20]
    53/320: $7\mem_di_w[31:0] [18]
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    55/320: $7\mem_di_w[31:0] [14]
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    60/320: $7\mem_di_w[31:0] [4]
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    62/320: $7\mem_di_w[31:0] [0]
    63/320: $7\mem_di_w[31:0] [30]
    64/320: $7\mem_di_w[31:0] [27]
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    68/320: $7\mem_di_w[31:0] [13]
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    70/320: $7\mem_di_w[31:0] [5]
    71/320: $7\mem_di_w[31:0] [1]
    72/320: $7\mem_di_w[31:0] [28]
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    75/320: $7\mem_di_w[31:0] [7]
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    78/320: $7\mem_di_w[31:0] [3]
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    80/320: $7\mem_di_w[31:0] [11]
    81/320: $6\mem_dm_w[7:0] [7]
    82/320: $6\mem_dm_w[7:0] [4]
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    84/320: $6\mem_dm_w[7:0] [0]
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    86/320: $6\mem_dm_w[7:0] [1]
    87/320: $6\mem_dm_w[7:0] [3]
    88/320: $6\mem_dm_w[7:0] [5]
    89/320: $6\mem_di_w[31:0] [31]
    90/320: $6\mem_di_w[31:0] [24]
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   120/320: $6\mem_di_w[31:0] [11]
   121/320: $5\mem_dm_w[7:0] [7]
   122/320: $5\mem_dm_w[7:0] [4]
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   124/320: $5\mem_dm_w[7:0] [0]
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   126/320: $5\mem_dm_w[7:0] [1]
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   128/320: $5\mem_dm_w[7:0] [5]
   129/320: $5\mem_di_w[31:0] [31]
   130/320: $5\mem_di_w[31:0] [24]
   131/320: $5\mem_di_w[31:0] [22]
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   151/320: $5\mem_di_w[31:0] [1]
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   153/320: $5\mem_di_w[31:0] [26]
   154/320: $5\mem_di_w[31:0] [15]
   155/320: $5\mem_di_w[31:0] [7]
   156/320: $5\mem_di_w[31:0] [29]
   157/320: $5\mem_di_w[31:0] [19]
   158/320: $5\mem_di_w[31:0] [3]
   159/320: $5\mem_di_w[31:0] [25]
   160/320: $5\mem_di_w[31:0] [11]
   161/320: $4\mem_dm_w[7:0] [7]
   162/320: $4\mem_dm_w[7:0] [4]
   163/320: $4\mem_dm_w[7:0] [2]
   164/320: $4\mem_dm_w[7:0] [0]
   165/320: $4\mem_dm_w[7:0] [6]
   166/320: $4\mem_dm_w[7:0] [1]
   167/320: $4\mem_dm_w[7:0] [3]
   168/320: $4\mem_dm_w[7:0] [5]
   169/320: $4\mem_di_w[31:0] [31]
   170/320: $4\mem_di_w[31:0] [24]
   171/320: $4\mem_di_w[31:0] [22]
   172/320: $4\mem_di_w[31:0] [20]
   173/320: $4\mem_di_w[31:0] [18]
   174/320: $4\mem_di_w[31:0] [16]
   175/320: $4\mem_di_w[31:0] [14]
   176/320: $4\mem_di_w[31:0] [12]
   177/320: $4\mem_di_w[31:0] [10]
   178/320: $4\mem_di_w[31:0] [8]
   179/320: $4\mem_di_w[31:0] [6]
   180/320: $4\mem_di_w[31:0] [4]
   181/320: $4\mem_di_w[31:0] [2]
   182/320: $4\mem_di_w[31:0] [0]
   183/320: $4\mem_di_w[31:0] [30]
   184/320: $4\mem_di_w[31:0] [27]
   185/320: $4\mem_di_w[31:0] [23]
   186/320: $4\mem_di_w[31:0] [21]
   187/320: $4\mem_di_w[31:0] [17]
   188/320: $4\mem_di_w[31:0] [13]
   189/320: $4\mem_di_w[31:0] [9]
   190/320: $4\mem_di_w[31:0] [5]
   191/320: $4\mem_di_w[31:0] [1]
   192/320: $4\mem_di_w[31:0] [28]
   193/320: $4\mem_di_w[31:0] [26]
   194/320: $4\mem_di_w[31:0] [15]
   195/320: $4\mem_di_w[31:0] [7]
   196/320: $4\mem_di_w[31:0] [29]
   197/320: $4\mem_di_w[31:0] [19]
   198/320: $4\mem_di_w[31:0] [3]
   199/320: $4\mem_di_w[31:0] [25]
   200/320: $4\mem_di_w[31:0] [11]
   201/320: $3\mem_dm_w[7:0] [7]
   202/320: $3\mem_dm_w[7:0] [4]
   203/320: $3\mem_dm_w[7:0] [2]
   204/320: $3\mem_dm_w[7:0] [0]
   205/320: $3\mem_dm_w[7:0] [6]
   206/320: $3\mem_dm_w[7:0] [1]
   207/320: $3\mem_dm_w[7:0] [3]
   208/320: $3\mem_dm_w[7:0] [5]
   209/320: $3\mem_di_w[31:0] [31]
   210/320: $3\mem_di_w[31:0] [24]
   211/320: $3\mem_di_w[31:0] [22]
   212/320: $3\mem_di_w[31:0] [20]
   213/320: $3\mem_di_w[31:0] [18]
   214/320: $3\mem_di_w[31:0] [16]
   215/320: $3\mem_di_w[31:0] [14]
   216/320: $3\mem_di_w[31:0] [12]
   217/320: $3\mem_di_w[31:0] [10]
   218/320: $3\mem_di_w[31:0] [8]
   219/320: $3\mem_di_w[31:0] [6]
   220/320: $3\mem_di_w[31:0] [4]
   221/320: $3\mem_di_w[31:0] [2]
   222/320: $3\mem_di_w[31:0] [0]
   223/320: $3\mem_di_w[31:0] [30]
   224/320: $3\mem_di_w[31:0] [27]
   225/320: $3\mem_di_w[31:0] [23]
   226/320: $3\mem_di_w[31:0] [21]
   227/320: $3\mem_di_w[31:0] [17]
   228/320: $3\mem_di_w[31:0] [13]
   229/320: $3\mem_di_w[31:0] [9]
   230/320: $3\mem_di_w[31:0] [5]
   231/320: $3\mem_di_w[31:0] [1]
   232/320: $3\mem_di_w[31:0] [28]
   233/320: $3\mem_di_w[31:0] [26]
   234/320: $3\mem_di_w[31:0] [15]
   235/320: $3\mem_di_w[31:0] [7]
   236/320: $3\mem_di_w[31:0] [29]
   237/320: $3\mem_di_w[31:0] [19]
   238/320: $3\mem_di_w[31:0] [3]
   239/320: $3\mem_di_w[31:0] [25]
   240/320: $3\mem_di_w[31:0] [11]
   241/320: $2\mem_dm_w[7:0] [7]
   242/320: $2\mem_dm_w[7:0] [4]
   243/320: $2\mem_dm_w[7:0] [2]
   244/320: $2\mem_dm_w[7:0] [0]
   245/320: $2\mem_dm_w[7:0] [6]
   246/320: $2\mem_dm_w[7:0] [1]
   247/320: $2\mem_dm_w[7:0] [3]
   248/320: $2\mem_dm_w[7:0] [5]
   249/320: $2\mem_di_w[31:0] [31]
   250/320: $2\mem_di_w[31:0] [24]
   251/320: $2\mem_di_w[31:0] [22]
   252/320: $2\mem_di_w[31:0] [20]
   253/320: $2\mem_di_w[31:0] [18]
   254/320: $2\mem_di_w[31:0] [16]
   255/320: $2\mem_di_w[31:0] [14]
   256/320: $2\mem_di_w[31:0] [12]
   257/320: $2\mem_di_w[31:0] [10]
   258/320: $2\mem_di_w[31:0] [8]
   259/320: $2\mem_di_w[31:0] [6]
   260/320: $2\mem_di_w[31:0] [4]
   261/320: $2\mem_di_w[31:0] [2]
   262/320: $2\mem_di_w[31:0] [0]
   263/320: $2\mem_di_w[31:0] [30]
   264/320: $2\mem_di_w[31:0] [27]
   265/320: $2\mem_di_w[31:0] [23]
   266/320: $2\mem_di_w[31:0] [21]
   267/320: $2\mem_di_w[31:0] [17]
   268/320: $2\mem_di_w[31:0] [13]
   269/320: $2\mem_di_w[31:0] [9]
   270/320: $2\mem_di_w[31:0] [5]
   271/320: $2\mem_di_w[31:0] [1]
   272/320: $2\mem_di_w[31:0] [28]
   273/320: $2\mem_di_w[31:0] [26]
   274/320: $2\mem_di_w[31:0] [15]
   275/320: $2\mem_di_w[31:0] [7]
   276/320: $2\mem_di_w[31:0] [29]
   277/320: $2\mem_di_w[31:0] [19]
   278/320: $2\mem_di_w[31:0] [3]
   279/320: $2\mem_di_w[31:0] [25]
   280/320: $2\mem_di_w[31:0] [11]
   281/320: $1\mem_dm_w[7:0] [7]
   282/320: $1\mem_dm_w[7:0] [4]
   283/320: $1\mem_dm_w[7:0] [2]
   284/320: $1\mem_dm_w[7:0] [0]
   285/320: $1\mem_dm_w[7:0] [6]
   286/320: $1\mem_dm_w[7:0] [1]
   287/320: $1\mem_dm_w[7:0] [3]
   288/320: $1\mem_dm_w[7:0] [5]
   289/320: $1\mem_di_w[31:0] [31]
   290/320: $1\mem_di_w[31:0] [24]
   291/320: $1\mem_di_w[31:0] [22]
   292/320: $1\mem_di_w[31:0] [20]
   293/320: $1\mem_di_w[31:0] [18]
   294/320: $1\mem_di_w[31:0] [16]
   295/320: $1\mem_di_w[31:0] [14]
   296/320: $1\mem_di_w[31:0] [12]
   297/320: $1\mem_di_w[31:0] [10]
   298/320: $1\mem_di_w[31:0] [8]
   299/320: $1\mem_di_w[31:0] [6]
   300/320: $1\mem_di_w[31:0] [4]
   301/320: $1\mem_di_w[31:0] [2]
   302/320: $1\mem_di_w[31:0] [0]
   303/320: $1\mem_di_w[31:0] [30]
   304/320: $1\mem_di_w[31:0] [27]
   305/320: $1\mem_di_w[31:0] [23]
   306/320: $1\mem_di_w[31:0] [21]
   307/320: $1\mem_di_w[31:0] [17]
   308/320: $1\mem_di_w[31:0] [13]
   309/320: $1\mem_di_w[31:0] [9]
   310/320: $1\mem_di_w[31:0] [5]
   311/320: $1\mem_di_w[31:0] [1]
   312/320: $1\mem_di_w[31:0] [28]
   313/320: $1\mem_di_w[31:0] [26]
   314/320: $1\mem_di_w[31:0] [15]
   315/320: $1\mem_di_w[31:0] [7]
   316/320: $1\mem_di_w[31:0] [29]
   317/320: $1\mem_di_w[31:0] [19]
   318/320: $1\mem_di_w[31:0] [3]
   319/320: $1\mem_di_w[31:0] [25]
   320/320: $1\mem_di_w[31:0] [11]
Creating decoders for process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:73$3556'.
     1/1: $0\addr_r[13:0]
Creating decoders for process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
Creating decoders for process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:32$4072'.
Creating decoders for process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:74$4053'.
     1/1: $0\clk_div[1:0]
Creating decoders for process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:57$4050'.
     1/1: $0\rst_i[0:0]
Creating decoders for process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:50$4047'.
     1/1: $0\rst_cnt[3:0]
Creating decoders for process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:294$3451'.
     1/5: $0\wb_cyc[3:0] [3]
     2/5: $0\wb_cyc[3:0] [2]
     3/5: $0\wb_cyc[3:0] [1]
     4/5: $0\wb_cyc[3:0] [0]
     5/5: $1\wb_cyc_proc.i[31:0]
Creating decoders for process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:291$3449'.
Creating decoders for process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:268$3436'.
Creating decoders for process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:241$3428'.
     1/1: $1\d_wb_ack[0:0]
Creating decoders for process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:221$3416'.
Creating decoders for process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:198$3408'.
Creating decoders for process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:175$3395'.
     1/5: $1\ctrl_is_io[0:0]
     2/5: $1\ctrl_is_ram[0:0]
     3/5: $1\ctrl_is_cache[0:0]
     4/5: $0\ctrl_is_dbus[0:0]
     5/5: $0\ctrl_is_ibus[0:0]
Creating decoders for process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:137$3390'.
     1/7: $7\state_nxt[2:0]
     2/7: $6\state_nxt[2:0]
     3/7: $5\state_nxt[2:0]
     4/7: $4\state_nxt[2:0]
     5/7: $3\state_nxt[2:0]
     6/7: $2\state_nxt[2:0]
     7/7: $1\state_nxt[2:0]
Creating decoders for process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:130$3389'.
     1/1: $0\state[2:0]

63.3.8. Executing PROC_DLATCH pass (convert process syncs to latches).
No latch inferred for signal `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes.\shift_in[0]' from process `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4334'.
No latch inferred for signal `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes.\shift_out[0]' from process `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4334'.
No latch inferred for signal `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes.\fcap_in[0]' from process `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4334'.
No latch inferred for signal `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes.\fcap_out[0]' from process `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4334'.
No latch inferred for signal `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes.\fcap_out[1]' from process `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4334'.
No latch inferred for signal `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.\bitrev16$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:105$4651.sig' from process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4660'.
No latch inferred for signal `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.\bitrev16$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:105$4651.$result' from process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4660'.
No latch inferred for signal `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.\bitrev16$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:105$4648.$result' from process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4660'.
No latch inferred for signal `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.\bitrev16$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:104$4650.sig' from process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4656'.
No latch inferred for signal `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.\bitrev16$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:104$4650.$result' from process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4656'.
No latch inferred for signal `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.\bitrev16$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:104$4647.$result' from process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4656'.
No latch inferred for signal `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.\bitrev16$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:81$4649.sig' from process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4652'.
No latch inferred for signal `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.\bitrev16$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:81$4649.$result' from process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4652'.
No latch inferred for signal `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.\bitrev16$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:81$4646.$result' from process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4652'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_valid[0]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_valid[1]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_valid[2]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_valid[3]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_dirty[0]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_dirty[1]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_dirty[2]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_dirty[3]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_age[0]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_age[1]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_age[2]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_age[3]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_tag[0]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_tag[1]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_tag[2]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_tag[3]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_match_age[0]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_match_age[1]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_match_age[2]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_match_age[3]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$mem2reg_rd$\way_tag$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:344$4512_DATA' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4631'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$mem2reg_rd$\way_dirty$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:343$4511_DATA' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4628'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$mem2reg_rd$\way_valid$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:342$4510_DATA' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4625'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\dm_addr' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:476$4615'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\dm_re' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:476$4615'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\dm_wdata' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:476$4615'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\dm_wmsk' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:476$4615'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\dm_we' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:476$4615'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\tag_next.w' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:441$4602'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_tag_we[0]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:441$4602'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_tag_we[1]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:441$4602'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_tag_we[2]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:441$4602'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_tag_we[3]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:441$4602'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\age_next.w' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:396$4577'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_age_nxt[0]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:396$4577'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_age_nxt[1]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:396$4577'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_age_nxt[2]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:396$4577'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_age_nxt[3]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:396$4577'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\dirty_next.w' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_valid_nxt[0]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_valid_nxt[1]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_valid_nxt[2]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_valid_nxt[3]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_valid_we[0]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_valid_we[1]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_valid_we[2]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_valid_we[3]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_dirty_nxt[0]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_dirty_nxt[1]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_dirty_nxt[2]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_dirty_nxt[3]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_dirty_we[0]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_dirty_we[1]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_dirty_we[2]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\way_dirty_we[3]' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\ev_way' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:330$4546'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\evict.w' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:330$4546'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\lu_hit_way' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:309$4541'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\lu_hit_age' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:309$4541'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\hit.w' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:309$4541'.
No latch inferred for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\ctrl_state_nxt' from process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:174$4514'.
No latch inferred for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\v_mux' from process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:147$3944'.
No latch inferred for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\h_mux' from process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:108$3935'.
No latch inferred for signal `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.\data[0]' from process `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:0$3893'.
No latch inferred for signal `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.\data[1]' from process `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:0$3893'.
No latch inferred for signal `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.\data[2]' from process `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:0$3893'.
No latch inferred for signal `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.\data[0]' from process `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:0$3880'.
No latch inferred for signal `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.\data[1]' from process `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:0$3880'.
No latch inferred for signal `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.\data[2]' from process `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:0$3880'.
No latch inferred for signal `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.\cnt_move' from process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:60$3493'.
No latch inferred for signal `\top.\wb_rdata[0]' from process `\top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/top.v:0$3492'.
No latch inferred for signal `\top.\wb_rdata[1]' from process `\top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/top.v:0$3492'.
No latch inferred for signal `\top.\wb_rdata[2]' from process `\top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/top.v:0$3492'.
No latch inferred for signal `\top.\wb_rdata[3]' from process `\top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/top.v:0$3492'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\rom_cmd_len.i' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[0]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[1]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[2]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[3]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[4]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[5]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[6]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[7]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[8]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[9]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[10]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[11]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[12]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[13]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[14]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cmd_len_rom[15]' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\phy_io_o' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\phy_io_oe' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\phy_clk_o' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.$result' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.shift' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.chan' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.io' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift2phy_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:743$2983.t' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.$result' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.shift' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.chan' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.io' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift2phy_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:745$2984.t' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift2phy_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:748$2985.$result' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift2phy_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:748$2985.shift' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift2phy_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:748$2985.base' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift2phy_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:748$2985.chan' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
Latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\io_ctrl.i' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105': $auto$proc_dlatch.cc:433:proc_dlatch$13269
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\so_ld_valid' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:544$3063'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\so_ld_mode' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:544$3063'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\so_ld_dst' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:544$3063'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\so_ld_cnt' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:544$3063'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\so_ld_src' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:544$3063'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$mem2reg_rd$\cmd_len_rom$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:570$2988_ADDR' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:544$3063'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$mem2reg_rd$\cmd_len_rom$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:570$2988_DATA' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:544$3063'.
No latch inferred for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\state_nxt' from process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:466$3036'.
No latch inferred for signal `\VexRiscv.\dBusWishbone_SEL' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4288$2381'.
No latch inferred for signal `\VexRiscv.\_zz_156_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4274$2380'.
No latch inferred for signal `\VexRiscv.\_zz_155_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4246$2369'.
No latch inferred for signal `\VexRiscv.\_zz_154_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4239$2368'.
No latch inferred for signal `\VexRiscv.\_zz_153_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4232$2367'.
No latch inferred for signal `\VexRiscv.\_zz_152_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4224$2366'.
No latch inferred for signal `\VexRiscv.\_zz_151_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4217$2365'.
No latch inferred for signal `\VexRiscv.\_zz_150_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4208$2364'.
No latch inferred for signal `\VexRiscv.\_zz_149_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4199$2363'.
No latch inferred for signal `\VexRiscv.\_zz_148_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4190$2362'.
No latch inferred for signal `\VexRiscv.\_zz_145_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4136$2305'.
No latch inferred for signal `\VexRiscv.\memory_DivPlugin_div_counter_valueNext' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4117$2295'.
No latch inferred for signal `\VexRiscv.\memory_DivPlugin_div_counter_willClear' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4108$2292'.
No latch inferred for signal `\VexRiscv.\memory_DivPlugin_div_counter_willIncrement' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4099$2291'.
No latch inferred for signal `\VexRiscv.\execute_MulPlugin_bSigned' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4077$2287'.
No latch inferred for signal `\VexRiscv.\execute_MulPlugin_aSigned' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4063$2286'.
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_writeData' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4049$2281'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_selfException_payload_code' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4029$2268'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_selfException_valid' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4022$2267'.
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalInstruction' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4013$2263'.
No latch inferred for signal `\VexRiscv.\execute_CsrPlugin_illegalAccess' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3963$2258'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_base' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3950$2256'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_xtvec_mode' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3939$2255'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_trapCause' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3932$2254'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_targetPrivilege' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3925$2253'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_done' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3914$2249'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_exceptionPortCtrl_exceptionValids_writeBack' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3900$2245'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_exceptionPortCtrl_exceptionValids_memory' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3890$2244'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_exceptionPortCtrl_exceptionValids_execute' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3880$2243'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_privilege' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3864$2237'.
No latch inferred for signal `\VexRiscv.\_zz_137_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3838$2233'.
No latch inferred for signal `\VexRiscv.\_zz_135_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3823$2232'.
No latch inferred for signal `\VexRiscv.\execute_BranchPlugin_branch_src2' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3808$2229'.
No latch inferred for signal `\VexRiscv.\_zz_133_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3785$2228'.
No latch inferred for signal `\VexRiscv.\execute_BranchPlugin_branch_src1' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3773$2227'.
No latch inferred for signal `\VexRiscv.\_zz_131_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3758$2224'.
No latch inferred for signal `\VexRiscv.\_zz_130_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3736$2223'.
No latch inferred for signal `\VexRiscv.\_zz_128_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3721$2222'.
No latch inferred for signal `\VexRiscv.\_zz_126_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3697$2221'.
No latch inferred for signal `\VexRiscv.\_zz_124_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3679$2220'.
No latch inferred for signal `\VexRiscv.\_zz_123_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3667$2213'.
No latch inferred for signal `\VexRiscv.\_zz_112_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3631$2204'.
No latch inferred for signal `\VexRiscv.\_zz_111_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3603$2202'.
No latch inferred for signal `\VexRiscv.\_zz_110_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3568$2201'.
No latch inferred for signal `\VexRiscv.\_zz_109_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3532$2198'.
No latch inferred for signal `\VexRiscv.\execute_SrcPlugin_addSub' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3523$2194'.
No latch inferred for signal `\VexRiscv.\_zz_108_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3506$2193'.
No latch inferred for signal `\VexRiscv.\_zz_107_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3483$2192'.
No latch inferred for signal `\VexRiscv.\_zz_105_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3459$2191'.
No latch inferred for signal `\VexRiscv.\_zz_103_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3441$2190'.
No latch inferred for signal `\VexRiscv.\_zz_102_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3427$2189'.
No latch inferred for signal `\VexRiscv.\execute_IntAluPlugin_bitwise' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3413$2185'.
No latch inferred for signal `\VexRiscv.\lastStageRegFileWrite_valid' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3404$2183'.
No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspFormated' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3350$2167'.
No latch inferred for signal `\VexRiscv.\_zz_87_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3330$2166'.
No latch inferred for signal `\VexRiscv.\_zz_85_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3301$2163'.
No latch inferred for signal `\VexRiscv.\writeBack_DBusSimplePlugin_rspShifted' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3283$2160'.
No latch inferred for signal `\VexRiscv.\DBusSimplePlugin_redoBranch_valid' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3272$2159'.
No latch inferred for signal `\VexRiscv.\DBusSimplePlugin_memoryExceptionPort_payload_code' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3262$2156'.
No latch inferred for signal `\VexRiscv.\DBusSimplePlugin_memoryExceptionPort_valid' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3248$2155'.
No latch inferred for signal `\VexRiscv.\_zz_83_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3228$2150'.
No latch inferred for signal `\VexRiscv.\_zz_82_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3213$2149'.
No latch inferred for signal `\VexRiscv.\execute_DBusSimplePlugin_skipCmd' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3200$2138'.
No latch inferred for signal `\VexRiscv.\_zz_164_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3183$2134'.
No latch inferred for signal `\VexRiscv.\IBusCachedPlugin_rsp_redoFetch' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3173$2133'.
No latch inferred for signal `\VexRiscv.\iBus_cmd_payload_address' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3158$2123'.
No latch inferred for signal `\VexRiscv.\_zz_79_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3134$2119'.
No latch inferred for signal `\VexRiscv.\_zz_77_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3119$2118'.
No latch inferred for signal `\VexRiscv.\_zz_75_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3106$2116'.
No latch inferred for signal `\VexRiscv.\_zz_74_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3084$2115'.
No latch inferred for signal `\VexRiscv.\_zz_72_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3069$2114'.
No latch inferred for signal `\VexRiscv.\IBusCachedPlugin_decodePrediction_cmd_hadBranch' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3061$2109'.
No latch inferred for signal `\VexRiscv.\_zz_70_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3039$2108'.
No latch inferred for signal `\VexRiscv.\IBusCachedPlugin_iBusRsp_readyForError' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3025$2105'.
No latch inferred for signal `\VexRiscv.\IBusCachedPlugin_iBusRsp_stages_2_halt' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3002$2090'.
No latch inferred for signal `\VexRiscv.\IBusCachedPlugin_iBusRsp_stages_1_halt' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2991$2086'.
No latch inferred for signal `\VexRiscv.\IBusCachedPlugin_iBusRsp_stages_0_halt' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2980$2082'.
No latch inferred for signal `\VexRiscv.\IBusCachedPlugin_iBusRsp_redoFetch' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2970$2081'.
No latch inferred for signal `\VexRiscv.\IBusCachedPlugin_fetchPc_flushed' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2958$2078'.
No latch inferred for signal `\VexRiscv.\IBusCachedPlugin_fetchPc_pc' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2946$2076'.
No latch inferred for signal `\VexRiscv.\IBusCachedPlugin_fetchPc_pcRegPropagate' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2939$2075'.
No latch inferred for signal `\VexRiscv.\IBusCachedPlugin_fetchPc_correction' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2928$2073'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_payload' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2901$2066'.
No latch inferred for signal `\VexRiscv.\CsrPlugin_jumpInterface_valid' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2891$2065'.
No latch inferred for signal `\VexRiscv.\IBusCachedPlugin_incomingInstruction' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2882$2063'.
No latch inferred for signal `\VexRiscv.\IBusCachedPlugin_fetcherHalt' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2869$2061'.
No latch inferred for signal `\VexRiscv.\writeBack_arbitration_flushNext' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2855$2060'.
No latch inferred for signal `\VexRiscv.\writeBack_arbitration_removeIt' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2847$2059'.
No latch inferred for signal `\VexRiscv.\memory_arbitration_flushNext' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2832$2058'.
No latch inferred for signal `\VexRiscv.\memory_arbitration_flushIt' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2825$2057'.
No latch inferred for signal `\VexRiscv.\memory_arbitration_removeIt' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2815$2056'.
No latch inferred for signal `\VexRiscv.\memory_arbitration_haltItself' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2802$2046'.
No latch inferred for signal `\VexRiscv.\execute_arbitration_flushNext' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2795$2045'.
No latch inferred for signal `\VexRiscv.\execute_arbitration_removeIt' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2784$2044'.
No latch inferred for signal `\VexRiscv.\execute_arbitration_haltItself' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2771$2036'.
No latch inferred for signal `\VexRiscv.\decode_arbitration_flushNext' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2764$2035'.
No latch inferred for signal `\VexRiscv.\decode_arbitration_removeIt' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2756$2034'.
No latch inferred for signal `\VexRiscv.\decode_arbitration_haltByOther' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2743$2024'.
No latch inferred for signal `\VexRiscv.\decode_arbitration_haltItself' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2736$2021'.
No latch inferred for signal `\VexRiscv.\_zz_54_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2726$2020'.
No latch inferred for signal `\VexRiscv.\_zz_53_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2716$2019'.
No latch inferred for signal `\VexRiscv.\_zz_51__0' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2707$2018'.
No latch inferred for signal `\VexRiscv.\_zz_51_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2700$2017'.
No latch inferred for signal `\VexRiscv.\_zz_50_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2652$2007'.
No latch inferred for signal `\VexRiscv.\decode_REGFILE_WRITE_VALID' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2644$2005'.
No latch inferred for signal `\VexRiscv.\_zz_42_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2636$2003'.
No latch inferred for signal `\VexRiscv.\_zz_32_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2599$2002'.
No latch inferred for signal `\VexRiscv.\decode_RS1' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2568$2000'.
No latch inferred for signal `\VexRiscv.\decode_RS2' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2538$1998'.
No latch inferred for signal `\VexRiscv.\_zz_31_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2525$1997'.
No latch inferred for signal `\VexRiscv.\_zz_167_' from process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1765$1977'.
No latch inferred for signal `\InstructionCache.\lineLoader_wayToAllocate_willIncrement' from process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:219$1752'.
No latch inferred for signal `\InstructionCache.\io_cpu_prefetch_haltIt' from process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:203$1747'.
No latch inferred for signal `\InstructionCache.\lineLoader_fire' from process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:194$1745'.
No latch inferred for signal `\InstructionCache.\_zz_2_' from process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:186$1744'.
No latch inferred for signal `\InstructionCache.\_zz_1_' from process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:179$1743'.
No latch inferred for signal `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes.\shift_in[0]' from process `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4397'.
No latch inferred for signal `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes.\shift_out[0]' from process `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4397'.
No latch inferred for signal `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes.\fcap_in[0]' from process `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4397'.
No latch inferred for signal `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes.\fcap_out[0]' from process `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4397'.
No latch inferred for signal `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes.\fcap_out[1]' from process `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4397'.
No latch inferred for signal `\vid_top.\wb_rdata' from process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:307$1657'.
No latch inferred for signal `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes.\shift_in[0]' from process `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4376'.
No latch inferred for signal `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes.\shift_out[0]' from process `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4376'.
No latch inferred for signal `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes.\fcap_in[0]' from process `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4376'.
No latch inferred for signal `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes.\fcap_out[0]' from process `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4376'.
No latch inferred for signal `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes.\fcap_out[1]' from process `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4376'.
No latch inferred for signal `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes.\shift_in[0]' from process `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4355'.
No latch inferred for signal `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes.\shift_out[0]' from process `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4355'.
No latch inferred for signal `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes.\fcap_in[0]' from process `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4355'.
No latch inferred for signal `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes.\fcap_out[0]' from process `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4355'.
No latch inferred for signal `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes.\fcap_out[1]' from process `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4355'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_do_m[0]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:0$3673'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_do[0]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:0$3673'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_do[1]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:0$3673'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di[0]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:0$3673'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di[1]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:0$3673'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_dm[0]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:0$3673'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_dm[1]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:0$3673'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\rd_data' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\map.n' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\map.x' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\map.o' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93$3524' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:94$3525' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93$3526' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:94$3527' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93$3528' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:94$3529' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93$3530' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:94$3531' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93$3532' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:94$3533' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93$3534' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:94$3535' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93$3536' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:94$3537' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:93$3538' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
No latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$bitselwrite$rvalue$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:94$3539' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [0]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$13480
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [1]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$13691
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [2]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$13902
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [3]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$14113
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [4]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$14324
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [5]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$14535
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [6]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$14746
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [7]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$14957
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [8]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$15168
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [9]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$15379
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [10]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$15590
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [11]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$15801
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [12]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$16012
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [13]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$16223
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [14]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$16434
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [15]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$16645
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [16]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$16856
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [17]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$17067
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [18]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$17278
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [19]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$17489
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [20]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$17700
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [21]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$17911
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [22]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$18122
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [23]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$18333
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [24]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$18544
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [25]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$18755
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [26]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$18966
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [27]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$19177
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [28]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$19388
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [29]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$19599
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [30]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$19810
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_di_w [31]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$20021
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_dm_w [0]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$20088
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_dm_w [1]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$20155
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_dm_w [2]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$20222
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_dm_w [3]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$20289
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_dm_w [4]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$20356
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_dm_w [5]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$20423
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_dm_w [6]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$20490
Latch inferred for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\mem_dm_w [7]' from process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557': $auto$proc_dlatch.cc:433:proc_dlatch$20557
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.\rst_init.i' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4031_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4032_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4033_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4034_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4035_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4036_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4037_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4038_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4039_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4040_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4041_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4042_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4043_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4044_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4045_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$memwr$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4046_EN' from process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
No latch inferred for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\d_wb_ack' from process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:241$3428'.
No latch inferred for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\state_nxt' from process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:137$3390'.

63.3.9. Executing PROC_DFF pass (convert process syncs to FFs).
Creating register for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\resp_ack' using process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:503$4617'.
  created $adff cell `$procdff$20558' with positive edge clock and positive level reset.
Creating register for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\resp_nak' using process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:503$4617'.
  created $adff cell `$procdff$20559' with positive edge clock and positive level reset.
Creating register for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\ev_way_r' using process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:347$4556'.
  created $dff cell `$procdff$20560' with positive edge clock.
Creating register for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\ev_valid_r' using process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:347$4556'.
  created $dff cell `$procdff$20561' with positive edge clock.
Creating register for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\ev_tag_r' using process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:347$4556'.
  created $dff cell `$procdff$20562' with positive edge clock.
Creating register for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\req_addr' using process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:237$4532'.
  created $dff cell `$procdff$20563' with positive edge clock.
Creating register for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\cnt_ofs' using process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:220$4524'.
  created $dff cell `$procdff$20564' with positive edge clock.
Creating register for signal `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.\ctrl_state' using process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:167$4513'.
  created $adff cell `$procdff$20565' with positive edge clock and positive level reset.
Creating register for signal `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.\dl[3]' using process `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:63$4445'.
  created $dff cell `$procdff$20566' with positive edge clock.
Creating register for signal `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.\dl[2]' using process `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:63$4444'.
  created $dff cell `$procdff$20567' with positive edge clock.
Creating register for signal `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.\dl[1]' using process `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:63$4443'.
  created $dff cell `$procdff$20568' with positive edge clock.
Creating register for signal `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.\dl[0]' using process `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:58$4442'.
  created $dff cell `$procdff$20569' with positive edge clock.
Creating register for signal `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.\ack' using process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:67$4441'.
  created $dff cell `$procdff$20570' with positive edge clock.
Creating register for signal `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.\shift' using process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:58$4440'.
  created $adff cell `$procdff$20571' with positive edge clock and positive level reset.
Creating register for signal `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.\bit_cnt' using process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:51$4437'.
  created $dff cell `$procdff$20572' with positive edge clock.
Creating register for signal `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.\div_cnt' using process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:42$4433'.
  created $dff cell `$procdff$20573' with positive edge clock.
Creating register for signal `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.\active' using process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:35$4429'.
  created $adff cell `$procdff$20574' with positive edge clock and positive level reset.
Creating register for signal `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.\stb' using process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:102$4423'.
  created $dff cell `$procdff$20575' with positive edge clock.
Creating register for signal `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.\shift' using process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:95$4422'.
  created $dff cell `$procdff$20576' with positive edge clock.
Creating register for signal `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.\bit_cnt' using process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:88$4419'.
  created $dff cell `$procdff$20577' with positive edge clock.
Creating register for signal `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.\div_cnt' using process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:77$4415'.
  created $dff cell `$procdff$20578' with positive edge clock.
Creating register for signal `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.\active' using process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:70$4411'.
  created $adff cell `$procdff$20579' with positive edge clock and positive level reset.
Creating register for signal `$paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp.\rd_data' using process `$paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:39$4400'.
  created $dff cell `$procdff$20580' with positive edge clock.
Creating register for signal `$paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp.$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_ADDR' using process `$paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:39$4400'.
  created $dff cell `$procdff$20581' with positive edge clock.
Creating register for signal `$paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp.$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_DATA' using process `$paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:39$4400'.
  created $dff cell `$procdff$20582' with positive edge clock.
Creating register for signal `$paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp.$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN' using process `$paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:39$4400'.
  created $dff cell `$procdff$20583' with positive edge clock.
Creating register for signal `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.\rd_valid' using process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:116$3982'.
  created $adff cell `$procdff$20584' with positive edge clock and positive level reset.
Creating register for signal `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.\ram_rd_addr' using process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:108$3976'.
  created $adff cell `$procdff$20585' with positive edge clock and positive level reset.
Creating register for signal `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.\ram_wr_addr' using process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:95$3974'.
  created $adff cell `$procdff$20586' with positive edge clock and positive level reset.
Creating register for signal `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.\full' using process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:83$3965'.
  created $adff cell `$procdff$20587' with positive edge clock and positive level reset.
Creating register for signal `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.\level' using process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:67$3959'.
  created $adff cell `$procdff$20588' with positive edge clock and positive level reset.
Creating register for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\vid_hsync' using process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:179$3945'.
  created $adff cell `$procdff$20589' with positive edge clock and positive level reset.
Creating register for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\vid_vsync' using process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:179$3945'.
  created $adff cell `$procdff$20590' with positive edge clock and positive level reset.
Creating register for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\vid_active' using process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:179$3945'.
  created $adff cell `$procdff$20591' with positive edge clock and positive level reset.
Creating register for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\vid_h_first' using process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:179$3945'.
  created $adff cell `$procdff$20592' with positive edge clock and positive level reset.
Creating register for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\vid_h_last' using process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:179$3945'.
  created $adff cell `$procdff$20593' with positive edge clock and positive level reset.
Creating register for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\vid_v_first' using process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:179$3945'.
  created $adff cell `$procdff$20594' with positive edge clock and positive level reset.
Creating register for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\vid_v_last' using process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:179$3945'.
  created $adff cell `$procdff$20595' with positive edge clock and positive level reset.
Creating register for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\v_zone' using process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:141$3942'.
  created $adff cell `$procdff$20596' with positive edge clock and positive level reset.
Creating register for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\v_first' using process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:135$3941'.
  created $adff cell `$procdff$20597' with positive edge clock and positive level reset.
Creating register for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\v_ce_r' using process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:132$3940'.
  created $dff cell `$procdff$20598' with positive edge clock.
Creating register for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\h_cnt' using process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:121$3936'.
  created $adff cell `$procdff$20599' with positive edge clock and positive level reset.
Creating register for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\h_zone' using process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:102$3933'.
  created $adff cell `$procdff$20600' with positive edge clock and positive level reset.
Creating register for signal `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.\h_first' using process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:96$3932'.
  created $adff cell `$procdff$20601' with positive edge clock and positive level reset.
Creating register for signal `$paramod\delay_bit\DELAY=s32'00000000000000000000000000000100.\dl' using process `$paramod\delay_bit\DELAY=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:30$3930'.
  created $dff cell `$procdff$20602' with positive edge clock.
Creating register for signal `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.\stage[1].l_valid' using process `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:64$3884'.
  created $adff cell `$procdff$20603' with positive edge clock and positive level reset.
Creating register for signal `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.\stage[1].l_data' using process `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:57$3882'.
  created $adff cell `$procdff$20604' with positive edge clock and positive level reset.
Creating register for signal `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.\stage[1].l_valid' using process `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:64$3871'.
  created $adff cell `$procdff$20605' with positive edge clock and positive level reset.
Creating register for signal `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.\stage[1].l_data' using process `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:57$3869'.
  created $adff cell `$procdff$20606' with positive edge clock and positive level reset.
Creating register for signal `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.\sync' using process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:53$3514'.
  created $dff cell `$procdff$20607' with positive edge clock.
Creating register for signal `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.\rise' using process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:95$3509'.
  created $dff cell `$procdff$20608' with positive edge clock.
Creating register for signal `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.\fall' using process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:95$3509'.
  created $dff cell `$procdff$20609' with positive edge clock.
Creating register for signal `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.\state' using process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:80$3505'.
  created $dff cell `$procdff$20610' with positive edge clock.
Creating register for signal `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.\cnt' using process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:70$3501'.
  created $dff cell `$procdff$20611' with positive edge clock.
Creating register for signal `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.\rdata' using process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
  created $dff cell `$procdff$20612' with positive edge clock.
Creating register for signal `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_ADDR' using process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
  created $dff cell `$procdff$20613' with positive edge clock.
Creating register for signal `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_DATA' using process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
  created $dff cell `$procdff$20614' with positive edge clock.
Creating register for signal `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_EN' using process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
  created $dff cell `$procdff$20615' with positive edge clock.
Creating register for signal `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_ADDR' using process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
  created $dff cell `$procdff$20616' with positive edge clock.
Creating register for signal `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_DATA' using process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
  created $dff cell `$procdff$20617' with positive edge clock.
Creating register for signal `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_EN' using process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
  created $dff cell `$procdff$20618' with positive edge clock.
Creating register for signal `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_ADDR' using process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
  created $dff cell `$procdff$20619' with positive edge clock.
Creating register for signal `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_DATA' using process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
  created $dff cell `$procdff$20620' with positive edge clock.
Creating register for signal `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_EN' using process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
  created $dff cell `$procdff$20621' with positive edge clock.
Creating register for signal `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_ADDR' using process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
  created $dff cell `$procdff$20622' with positive edge clock.
Creating register for signal `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_DATA' using process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
  created $dff cell `$procdff$20623' with positive edge clock.
Creating register for signal `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_EN' using process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
  created $dff cell `$procdff$20624' with positive edge clock.
Creating register for signal `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.\w_addr_r' using process `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_ram.v:114$4450'.
  created $dff cell `$procdff$20625' with positive edge clock.
Creating register for signal `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.\w_val_r' using process `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_ram.v:114$4450'.
  created $dff cell `$procdff$20626' with positive edge clock.
Creating register for signal `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.\w_msk_r' using process `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_ram.v:114$4450'.
  created $dff cell `$procdff$20627' with positive edge clock.
Creating register for signal `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.\w_ena_r' using process `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_ram.v:114$4450'.
  created $dff cell `$procdff$20628' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\phy_cs_o' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:615$3181'.
  created $dff cell `$procdff$20629' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$bitselwrite$pos$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:625$2978' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:615$3181'.
  created $dff cell `$procdff$20630' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$bitselwrite$pos$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:627$2979' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:615$3181'.
  created $dff cell `$procdff$20631' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$lookahead\phy_cs_o$3180' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:615$3181'.
  created $dff cell `$procdff$20632' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\si_data_n' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
  created $dff cell `$procdff$20633' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.$result' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
  created $dff cell `$procdff$20634' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.prev' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
  created $dff cell `$procdff$20635' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.phy' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
  created $dff cell `$procdff$20636' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.chan' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
  created $dff cell `$procdff$20637' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.t' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
  created $dff cell `$procdff$20638' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\phy2shift_qpi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:779$2986.io' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
  created $dff cell `$procdff$20639' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\phy2shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:781$2987.$result' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
  created $dff cell `$procdff$20640' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\phy2shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:781$2987.prev' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
  created $dff cell `$procdff$20641' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\phy2shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:781$2987.phy' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
  created $dff cell `$procdff$20642' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\phy2shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:781$2987.chan' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
  created $dff cell `$procdff$20643' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\si_dst_1' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:758$3151'.
  created $dff cell `$procdff$20644' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\so_data' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:700$3085'.
  created $dff cell `$procdff$20645' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:703$2980.$result' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:700$3085'.
  created $dff cell `$procdff$20646' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:703$2980.shift' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:700$3085'.
  created $dff cell `$procdff$20647' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift_spi$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:703$2980.chan' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:700$3085'.
  created $dff cell `$procdff$20648' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:704$2981.$result' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:700$3085'.
  created $dff cell `$procdff$20649' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:704$2981.shift' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:700$3085'.
  created $dff cell `$procdff$20650' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift_qpi_data$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:704$2981.chan' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:700$3085'.
  created $dff cell `$procdff$20651' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:705$2982.$result' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:700$3085'.
  created $dff cell `$procdff$20652' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\shift_qpi_cmd$func$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:705$2982.shift' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:700$3085'.
  created $dff cell `$procdff$20653' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\so_cnt' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:691$3083'.
  created $dff cell `$procdff$20654' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\so_mode' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:684$3082'.
  created $dff cell `$procdff$20655' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\so_dst' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:684$3082'.
  created $dff cell `$procdff$20656' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\so_valid' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:677$3077'.
  created $dff cell `$procdff$20657' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\pause_cnt' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:515$3051'.
  created $dff cell `$procdff$20658' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\xfer_cnt' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:506$3043'.
  created $dff cell `$procdff$20659' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\state' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:459$3035'.
  created $dff cell `$procdff$20660' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\rf_overflow' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:447$3029'.
  created $dff cell `$procdff$20661' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\wb_rdata' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:373$3025'.
  created $dff cell `$procdff$20662' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\rf_rden_arm' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:363$3017'.
  created $dff cell `$procdff$20663' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\cf_wren' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:359$3010'.
  created $dff cell `$procdff$20664' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\rf_overflow_clr' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:344$3008'.
  created $dff cell `$procdff$20665' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\ectl_cs' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:337$3005'.
  created $dff cell `$procdff$20666' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\ectl_req' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:331$3001'.
  created $dff cell `$procdff$20667' with positive edge clock.
Creating register for signal `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.\wb_ack' using process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:314$2989'.
  created $dff cell `$procdff$20668' with positive edge clock.
Creating register for signal `$paramod$9a9e2282df54acafd6229f692355382480e5c2ad\qpi_phy_ice40_4x.\iob_cs_o' using process `$paramod$9a9e2282df54acafd6229f692355382480e5c2ad\qpi_phy_ice40_4x.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_phy_ice40_4x.v:163$2977'.
  created $dff cell `$procdff$20669' with positive edge clock.
Creating register for signal `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.\uart_div' using process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:193$2973'.
  created $dff cell `$procdff$20670' with positive edge clock.
Creating register for signal `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.\ub_rdata' using process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:185$2971'.
  created $dff cell `$procdff$20671' with positive edge clock.
Creating register for signal `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.\ub_ack' using process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:177$2961'.
  created $dff cell `$procdff$20672' with positive edge clock.
Creating register for signal `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.\ub_rd_data' using process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:164$2944'.
  created $dff cell `$procdff$20673' with positive edge clock.
Creating register for signal `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.\ub_rd_ctrl' using process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:164$2944'.
  created $dff cell `$procdff$20674' with positive edge clock.
Creating register for signal `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.\ub_wr_data' using process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:164$2944'.
  created $dff cell `$procdff$20675' with positive edge clock.
Creating register for signal `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.\ub_wr_div' using process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:164$2944'.
  created $dff cell `$procdff$20676' with positive edge clock.
Creating register for signal `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.\urf_overflow' using process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:154$2939'.
  created $adff cell `$procdff$20677' with positive edge clock and positive level reset.
Creating register for signal `$paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb.\led_ctrl' using process `$paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_rgb_wb.v:94$2932'.
  created $adff cell `$procdff$20678' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFNES.\Q' using process `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$2791'.
  created $adff cell `$procdff$20679' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNESS.\Q' using process `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$2786'.
  created $dff cell `$procdff$20680' with negative edge clock.
Creating register for signal `\SB_DFFNER.\Q' using process `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$2782'.
  created $adff cell `$procdff$20681' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNESR.\Q' using process `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$2777'.
  created $dff cell `$procdff$20682' with negative edge clock.
Creating register for signal `\SB_DFFNS.\Q' using process `\SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$2774'.
  created $adff cell `$procdff$20683' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNSS.\Q' using process `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$2771'.
  created $dff cell `$procdff$20684' with negative edge clock.
Creating register for signal `\SB_DFFNR.\Q' using process `\SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$2768'.
  created $adff cell `$procdff$20685' with negative edge clock and positive level reset.
Creating register for signal `\SB_DFFNSR.\Q' using process `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$2765'.
  created $dff cell `$procdff$20686' with negative edge clock.
Creating register for signal `\SB_DFFNE.\Q' using process `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$2763'.
  created $dff cell `$procdff$20687' with negative edge clock.
Creating register for signal `\SB_DFFN.\Q' using process `\SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$2761'.
  created $dff cell `$procdff$20688' with negative edge clock.
Creating register for signal `\SB_DFFES.\Q' using process `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$2757'.
  created $adff cell `$procdff$20689' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFESS.\Q' using process `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$2752'.
  created $dff cell `$procdff$20690' with positive edge clock.
Creating register for signal `\SB_DFFER.\Q' using process `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$2748'.
  created $adff cell `$procdff$20691' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFESR.\Q' using process `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$2743'.
  created $dff cell `$procdff$20692' with positive edge clock.
Creating register for signal `\SB_DFFS.\Q' using process `\SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$2740'.
  created $adff cell `$procdff$20693' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFSS.\Q' using process `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$2737'.
  created $dff cell `$procdff$20694' with positive edge clock.
Creating register for signal `\SB_DFFR.\Q' using process `\SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$2734'.
  created $adff cell `$procdff$20695' with positive edge clock and positive level reset.
Creating register for signal `\SB_DFFSR.\Q' using process `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$2731'.
  created $dff cell `$procdff$20696' with positive edge clock.
Creating register for signal `\SB_DFFE.\Q' using process `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$2729'.
  created $dff cell `$procdff$20697' with positive edge clock.
Creating register for signal `\SB_DFF.\Q' using process `\SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$2727'.
  created $dff cell `$procdff$20698' with positive edge clock.
Creating register for signal `\VexRiscv.\_zz_68_' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20699' with positive edge clock.
Creating register for signal `\VexRiscv.\IBusCachedPlugin_s1_tightlyCoupledHit' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20700' with positive edge clock.
Creating register for signal `\VexRiscv.\IBusCachedPlugin_s2_tightlyCoupledHit' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20701' with positive edge clock.
Creating register for signal `\VexRiscv.\_zz_114_' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20702' with positive edge clock.
Creating register for signal `\VexRiscv.\_zz_115_' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20703' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mtvec_mode' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20704' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mtvec_base' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20705' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mepc' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20706' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MEIP' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20707' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MTIP' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20708' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mip_MSIP' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20709' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mcause_interrupt' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20710' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mcause_exceptionCode' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20711' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mtval' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20712' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_mcycle' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20713' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_minstret' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20714' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_exceptionPortCtrl_exceptionContext_code' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20715' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20716' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_code' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20717' with positive edge clock.
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_targetPrivilege' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20718' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_DivPlugin_rs1' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20719' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_DivPlugin_rs2' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20720' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_DivPlugin_accumulator' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20721' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_DivPlugin_div_needRevert' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20722' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_DivPlugin_div_done' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20723' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_DivPlugin_div_result' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20724' with positive edge clock.
Creating register for signal `\VexRiscv.\externalInterruptArray_regNext' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20725' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_HH' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20726' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_MUL_HH' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20727' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_RS1' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20728' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_PREDICTION_HAD_BRANCHED2' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20729' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_STORE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20730' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_STORE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20731' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_STORE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20732' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_MEMORY_ENABLE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20733' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ENABLE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20734' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ENABLE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20735' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_IS_MUL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20736' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_IS_MUL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20737' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_IS_MUL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20738' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_CSR_READ_OPCODE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20739' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_SRC2_FORCE_ZERO' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20740' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_LL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20741' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MMU_RSP_physicalAddress' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20742' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MMU_RSP_isIoAccess' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20743' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MMU_RSP_allowRead' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20744' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MMU_RSP_allowWrite' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20745' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MMU_RSP_allowExecute' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20746' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MMU_RSP_exception' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20747' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MMU_RSP_refilling' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20748' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_SRC_USE_SUB_LESS' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20749' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_BRANCH_CTRL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20750' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_INSTRUCTION' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20751' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_INSTRUCTION' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20752' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_SHIFT_RIGHT' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20753' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20754' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20755' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_FORMAL_PC_NEXT' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20756' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_SHIFT_CTRL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20757' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_SHIFT_CTRL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20758' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_ALU_BITWISE_CTRL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20759' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_IS_DIV' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20760' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_IS_DIV' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20761' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_HL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20762' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20763' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20764' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_VALID' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20765' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_PC' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20766' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_PC' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20767' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_PC' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20768' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_CSR_WRITE_OPCODE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20769' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_SRC_LESS_UNSIGNED' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20770' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_ALU_CTRL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20771' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20772' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_BYPASSABLE_MEMORY_STAGE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20773' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20774' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_IS_CSR' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20775' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_CALC' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20776' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_ENV_CTRL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20777' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_ENV_CTRL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20778' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_ENV_CTRL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20779' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_BYPASSABLE_EXECUTE_STAGE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20780' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_MUL_LOW' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20781' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_BRANCH_DO' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20782' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MMU_FAULT' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20783' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_RS2' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20784' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_SRC1_CTRL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20785' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20786' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_ADDRESS_LOW' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20787' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_IS_RS1_SIGNED' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20788' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_IS_RS2_SIGNED' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20789' with positive edge clock.
Creating register for signal `\VexRiscv.\decode_to_execute_SRC2_CTRL' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20790' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_to_memory_MUL_LH' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20791' with positive edge clock.
Creating register for signal `\VexRiscv.\memory_to_writeBack_MEMORY_READ_DATA' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20792' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_1984' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20793' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_768' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20794' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_836' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20795' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_772' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20796' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_773' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20797' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_833' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20798' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_834' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20799' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_835' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20800' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_3008' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20801' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_csr_4032' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20802' with positive edge clock.
Creating register for signal `\VexRiscv.\dBus_cmd_halfPipe_regs_payload_wr' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20803' with positive edge clock.
Creating register for signal `\VexRiscv.\dBus_cmd_halfPipe_regs_payload_address' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20804' with positive edge clock.
Creating register for signal `\VexRiscv.\dBus_cmd_halfPipe_regs_payload_data' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20805' with positive edge clock.
Creating register for signal `\VexRiscv.\dBus_cmd_halfPipe_regs_payload_size' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
  created $dff cell `$procdff$20806' with positive edge clock.
Creating register for signal `\VexRiscv.\execute_arbitration_isValid' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20807' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\memory_arbitration_isValid' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20808' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\writeBack_arbitration_isValid' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20809' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusCachedPlugin_fetchPc_pcReg' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
Warning: Async reset value `\externalResetVector' is not constant!
  created $aldff cell `$procdff$20810' with positive edge clock and positive level non-const reset.
Creating register for signal `\VexRiscv.\IBusCachedPlugin_fetchPc_correctionReg' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20811' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusCachedPlugin_fetchPc_booted' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20812' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusCachedPlugin_fetchPc_inc' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20813' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\_zz_65_' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20814' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\_zz_67_' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20815' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusCachedPlugin_injector_nextPcCalc_valids_0' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20816' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusCachedPlugin_injector_nextPcCalc_valids_1' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20817' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusCachedPlugin_injector_nextPcCalc_valids_2' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20818' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusCachedPlugin_injector_nextPcCalc_valids_3' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20819' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusCachedPlugin_injector_nextPcCalc_valids_4' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20820' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\IBusCachedPlugin_rspCounter' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20821' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\RegFilePlugin_shadow_write' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20822' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\RegFilePlugin_shadow_read' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20823' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\RegFilePlugin_shadow_clear' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20824' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\_zz_101_' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20825' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\_zz_113_' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20826' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MIE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20827' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPIE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20828' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_mstatus_MPP' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20829' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MEIE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20830' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MTIE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20831' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_mie_MSIE' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20832' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_execute' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20833' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_memory' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20834' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20835' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_interrupt_valid' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20836' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_0' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20837' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_1' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20838' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_pipelineLiberator_pcValids_2' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20839' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\CsrPlugin_hadException' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20840' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\execute_CsrPlugin_wfiWake' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20841' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\memory_DivPlugin_div_counter_value' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20842' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\_zz_146_' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20843' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\memory_to_writeBack_INSTRUCTION' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20844' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\memory_to_writeBack_REGFILE_WRITE_DATA' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20845' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\dBus_cmd_halfPipe_regs_valid' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20846' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.\dBus_cmd_halfPipe_regs_ready' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
  created $adff cell `$procdff$20847' with positive edge clock and positive level reset.
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_ADDR' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1713$1970'.
  created $dff cell `$procdff$20848' with positive edge clock.
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_DATA' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1713$1970'.
  created $dff cell `$procdff$20849' with positive edge clock.
Creating register for signal `\VexRiscv.$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1713$1970'.
  created $dff cell `$procdff$20850' with positive edge clock.
Creating register for signal `\VexRiscv.\_zz_166_' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1707$1968'.
  created $dff cell `$procdff$20851' with positive edge clock.
Creating register for signal `\VexRiscv.\_zz_165_' using process `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1701$1966'.
  created $dff cell `$procdff$20852' with positive edge clock.
Creating register for signal `\InstructionCache.\lineLoader_address' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
  created $dff cell `$procdff$20853' with positive edge clock.
Creating register for signal `\InstructionCache.\lineLoader_flushCounter' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
  created $dff cell `$procdff$20854' with positive edge clock.
Creating register for signal `\InstructionCache.\_zz_3_' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
  created $dff cell `$procdff$20855' with positive edge clock.
Creating register for signal `\InstructionCache.\io_cpu_fetch_data_regNextWhen' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
  created $dff cell `$procdff$20856' with positive edge clock.
Creating register for signal `\InstructionCache.\decodeStage_mmuRsp_physicalAddress' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
  created $dff cell `$procdff$20857' with positive edge clock.
Creating register for signal `\InstructionCache.\decodeStage_mmuRsp_isIoAccess' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
  created $dff cell `$procdff$20858' with positive edge clock.
Creating register for signal `\InstructionCache.\decodeStage_mmuRsp_allowRead' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
  created $dff cell `$procdff$20859' with positive edge clock.
Creating register for signal `\InstructionCache.\decodeStage_mmuRsp_allowWrite' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
  created $dff cell `$procdff$20860' with positive edge clock.
Creating register for signal `\InstructionCache.\decodeStage_mmuRsp_allowExecute' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
  created $dff cell `$procdff$20861' with positive edge clock.
Creating register for signal `\InstructionCache.\decodeStage_mmuRsp_exception' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
  created $dff cell `$procdff$20862' with positive edge clock.
Creating register for signal `\InstructionCache.\decodeStage_mmuRsp_refilling' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
  created $dff cell `$procdff$20863' with positive edge clock.
Creating register for signal `\InstructionCache.\decodeStage_hit_valid' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
  created $dff cell `$procdff$20864' with positive edge clock.
Creating register for signal `\InstructionCache.\decodeStage_hit_error' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
  created $dff cell `$procdff$20865' with positive edge clock.
Creating register for signal `\InstructionCache.\lineLoader_valid' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:264$1773'.
  created $adff cell `$procdff$20866' with positive edge clock and positive level reset.
Creating register for signal `\InstructionCache.\lineLoader_hadError' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:264$1773'.
  created $adff cell `$procdff$20867' with positive edge clock and positive level reset.
Creating register for signal `\InstructionCache.\lineLoader_flushPending' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:264$1773'.
  created $adff cell `$procdff$20868' with positive edge clock and positive level reset.
Creating register for signal `\InstructionCache.\lineLoader_cmdSent' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:264$1773'.
  created $adff cell `$procdff$20869' with positive edge clock and positive level reset.
Creating register for signal `\InstructionCache.\lineLoader_wordIndex' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:264$1773'.
  created $adff cell `$procdff$20870' with positive edge clock and positive level reset.
Creating register for signal `\InstructionCache.\_zz_11_' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:173$1741'.
  created $dff cell `$procdff$20871' with positive edge clock.
Creating register for signal `\InstructionCache.$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_ADDR' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:167$1734'.
  created $dff cell `$procdff$20872' with positive edge clock.
Creating register for signal `\InstructionCache.$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_DATA' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:167$1734'.
  created $dff cell `$procdff$20873' with positive edge clock.
Creating register for signal `\InstructionCache.$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:167$1734'.
  created $dff cell `$procdff$20874' with positive edge clock.
Creating register for signal `\InstructionCache.\_zz_10_' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:161$1732'.
  created $dff cell `$procdff$20875' with positive edge clock.
Creating register for signal `\InstructionCache.$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_ADDR' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:155$1725'.
  created $dff cell `$procdff$20876' with positive edge clock.
Creating register for signal `\InstructionCache.$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_DATA' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:155$1725'.
  created $dff cell `$procdff$20877' with positive edge clock.
Creating register for signal `\InstructionCache.$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN' using process `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:155$1725'.
  created $dff cell `$procdff$20878' with positive edge clock.
Creating register for signal `\vid_top.\wb_ack' using process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:303$1651'.
  created $dff cell `$procdff$20879' with positive edge clock.
Creating register for signal `\vid_top.\pp_data_3' using process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:253$1644'.
  created $dff cell `$procdff$20880' with positive edge clock.
Creating register for signal `\vid_top.\pp_data_load_2' using process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:250$1643'.
  created $dff cell `$procdff$20881' with positive edge clock.
Creating register for signal `\vid_top.\pp_addr_cur_1' using process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:239$1636'.
  created $dff cell `$procdff$20882' with positive edge clock.
Creating register for signal `\vid_top.\pp_addr_base_1' using process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:231$1633'.
  created $dff cell `$procdff$20883' with positive edge clock.
Creating register for signal `\vid_top.\pp_active_1' using process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:224$1629'.
  created $dff cell `$procdff$20884' with positive edge clock.
Creating register for signal `\vid_top.\pp_xdbl_1' using process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:224$1629'.
  created $dff cell `$procdff$20885' with positive edge clock.
Creating register for signal `\vid_top.\pp_ydbl_1' using process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:200$1628'.
  created $dff cell `$procdff$20886' with positive edge clock.
Creating register for signal `\vid_top.\pp_yscale_state' using process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:200$1628'.
  created $dff cell `$procdff$20887' with positive edge clock.
Creating register for signal `\vid_top.\vs_frame_cnt' using process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:178$1625'.
  created $dff cell `$procdff$20888' with positive edge clock.
Creating register for signal `\vid_top.\vs_in_vbl' using process `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:175$1620'.
  created $dff cell `$procdff$20889' with positive edge clock.
Creating register for signal `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.\addr_r' using process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:73$3556'.
  created $dff cell `$procdff$20890' with positive edge clock.
Creating register for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.\clk_div' using process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:74$4053'.
  created $adff cell `$procdff$20891' with positive edge clock and negative level reset.
Creating register for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.\rst_i' using process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:57$4050'.
  created $adff cell `$procdff$20892' with positive edge clock and negative level reset.
Creating register for signal `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.\rst_cnt' using process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:50$4047'.
  created $adff cell `$procdff$20893' with positive edge clock and negative level reset.
Creating register for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\wb_cyc' using process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:294$3451'.
  created $dff cell `$procdff$20894' with positive edge clock.
Creating register for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\wb_cyc_proc.i' using process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:294$3451'.
  created $dff cell `$procdff$20895' with positive edge clock.
Creating register for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\wb_ack_i' using process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:291$3449'.
  created $dff cell `$procdff$20896' with positive edge clock.
Creating register for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\req_new' using process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:268$3436'.
  created $dff cell `$procdff$20897' with positive edge clock.
Creating register for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\ib_addr_cnt' using process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:221$3416'.
  created $dff cell `$procdff$20898' with positive edge clock.
Creating register for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\rdata_io' using process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:198$3408'.
  created $dff cell `$procdff$20899' with positive edge clock.
Creating register for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\rdata.i' using process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:198$3408'.
  created $dff cell `$procdff$20900' with positive edge clock.
Creating register for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\ctrl_is_ibus' using process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:175$3395'.
  created $dff cell `$procdff$20901' with positive edge clock.
Creating register for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\ctrl_is_dbus' using process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:175$3395'.
  created $dff cell `$procdff$20902' with positive edge clock.
Creating register for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\ctrl_is_cache' using process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:175$3395'.
  created $dff cell `$procdff$20903' with positive edge clock.
Creating register for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\ctrl_is_ram' using process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:175$3395'.
  created $dff cell `$procdff$20904' with positive edge clock.
Creating register for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\ctrl_is_io' using process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:175$3395'.
  created $dff cell `$procdff$20905' with positive edge clock.
Creating register for signal `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.\state' using process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:130$3389'.
  created $dff cell `$procdff$20906' with positive edge clock.

63.3.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

63.3.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Removing empty process `$paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4334'.
Removing empty process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4660'.
Removing empty process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4656'.
Removing empty process `$paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_ebr.v:0$4652'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4639'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4634'.
Found and cleaned up 1 empty switch in `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4631'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4631'.
Found and cleaned up 1 empty switch in `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4628'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4628'.
Found and cleaned up 1 empty switch in `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4625'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:0$4625'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:503$4617'.
Found and cleaned up 1 empty switch in `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:476$4615'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:476$4615'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:441$4602'.
Found and cleaned up 21 empty switches in `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:396$4577'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:396$4577'.
Found and cleaned up 1 empty switch in `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:364$4560'.
Found and cleaned up 1 empty switch in `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:347$4556'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:347$4556'.
Found and cleaned up 3 empty switches in `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:330$4546'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:330$4546'.
Found and cleaned up 3 empty switches in `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:309$4541'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:309$4541'.
Found and cleaned up 1 empty switch in `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:237$4532'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:237$4532'.
Found and cleaned up 2 empty switches in `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:220$4524'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:220$4524'.
Found and cleaned up 5 empty switches in `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:174$4514'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:174$4514'.
Removing empty process `$paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:167$4513'.
Removing empty process `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:63$4445'.
Removing empty process `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:63$4444'.
Removing empty process `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:63$4443'.
Removing empty process `$paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:58$4442'.
Removing empty process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:67$4441'.
Found and cleaned up 2 empty switches in `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:58$4440'.
Removing empty process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:58$4440'.
Found and cleaned up 2 empty switches in `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:51$4437'.
Removing empty process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:51$4437'.
Found and cleaned up 1 empty switch in `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:42$4433'.
Removing empty process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:42$4433'.
Removing empty process `$paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:35$4429'.
Removing empty process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:102$4423'.
Found and cleaned up 1 empty switch in `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:95$4422'.
Removing empty process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:95$4422'.
Found and cleaned up 2 empty switches in `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:88$4419'.
Removing empty process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:88$4419'.
Found and cleaned up 2 empty switches in `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:77$4415'.
Removing empty process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:77$4415'.
Removing empty process `$paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:70$4411'.
Found and cleaned up 2 empty switches in `$paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:39$4400'.
Removing empty process `$paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:39$4400'.
Found and cleaned up 1 empty switch in `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:116$3982'.
Removing empty process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:116$3982'.
Found and cleaned up 1 empty switch in `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:108$3976'.
Removing empty process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:108$3976'.
Found and cleaned up 1 empty switch in `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:95$3974'.
Removing empty process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:95$3974'.
Removing empty process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:83$3965'.
Removing empty process `$paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:67$3959'.
Removing empty process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:179$3945'.
Found and cleaned up 2 empty switches in `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:147$3944'.
Removing empty process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:147$3944'.
Found and cleaned up 1 empty switch in `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:141$3942'.
Removing empty process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:141$3942'.
Found and cleaned up 1 empty switch in `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:135$3941'.
Removing empty process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:135$3941'.
Removing empty process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:132$3940'.
Removing empty process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:121$3936'.
Found and cleaned up 2 empty switches in `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:108$3935'.
Removing empty process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:108$3935'.
Removing empty process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:102$3933'.
Removing empty process `$paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:96$3932'.
Removing empty process `$paramod\delay_bit\DELAY=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:30$3930'.
Removing empty process `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:0$3893'.
Found and cleaned up 1 empty switch in `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:64$3884'.
Removing empty process `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:64$3884'.
Found and cleaned up 1 empty switch in `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:57$3882'.
Removing empty process `$paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:57$3882'.
Removing empty process `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:0$3880'.
Found and cleaned up 1 empty switch in `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:64$3871'.
Removing empty process `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:64$3871'.
Found and cleaned up 1 empty switch in `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:57$3869'.
Removing empty process `$paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:57$3869'.
Removing empty process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:53$3514'.
Found and cleaned up 1 empty switch in `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:95$3509'.
Removing empty process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:95$3509'.
Found and cleaned up 3 empty switches in `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:80$3505'.
Removing empty process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:80$3505'.
Found and cleaned up 1 empty switch in `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:70$3501'.
Removing empty process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:70$3501'.
Found and cleaned up 2 empty switches in `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:60$3493'.
Removing empty process `$paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:60$3493'.
Removing empty process `top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/top.v:0$3492'.
Found and cleaned up 4 empty switches in `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
Removing empty process `$paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:31$3353'.
Removing empty process `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_ram.v:0$4452'.
Removing empty process `$paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_tag_ram.v:114$4450'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3212'.
Found and cleaned up 5 empty switches in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:615$3181'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:615$3181'.
Found and cleaned up 1 empty switch in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:773$3158'.
Found and cleaned up 1 empty switch in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:758$3151'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:758$3151'.
Found and cleaned up 4 empty switches in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:714$3105'.
Found and cleaned up 1 empty switch in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:700$3085'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:700$3085'.
Found and cleaned up 1 empty switch in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:691$3083'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:691$3083'.
Found and cleaned up 1 empty switch in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:684$3082'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:684$3082'.
Found and cleaned up 1 empty switch in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:677$3077'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:677$3077'.
Found and cleaned up 3 empty switches in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:544$3063'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:544$3063'.
Found and cleaned up 1 empty switch in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:515$3051'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:515$3051'.
Found and cleaned up 2 empty switches in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:506$3043'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:506$3043'.
Found and cleaned up 9 empty switches in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:466$3036'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:466$3036'.
Found and cleaned up 1 empty switch in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:459$3035'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:459$3035'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:447$3029'.
Found and cleaned up 1 empty switch in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:373$3025'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:373$3025'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:363$3017'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:359$3010'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:344$3008'.
Found and cleaned up 1 empty switch in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:337$3005'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:337$3005'.
Found and cleaned up 2 empty switches in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:331$3001'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:331$3001'.
Found and cleaned up 2 empty switches in `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:314$2989'.
Removing empty process `$paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:314$2989'.
Removing empty process `$paramod$9a9e2282df54acafd6229f692355382480e5c2ad\qpi_phy_ice40_4x.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_phy_ice40_4x.v:163$2977'.
Found and cleaned up 1 empty switch in `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:193$2973'.
Removing empty process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:193$2973'.
Found and cleaned up 1 empty switch in `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:185$2971'.
Removing empty process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:185$2971'.
Found and cleaned up 1 empty switch in `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:177$2961'.
Removing empty process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:177$2961'.
Found and cleaned up 1 empty switch in `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:164$2944'.
Removing empty process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:164$2944'.
Removing empty process `$paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:154$2939'.
Found and cleaned up 1 empty switch in `$paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_rgb_wb.v:94$2932'.
Removing empty process `$paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_rgb_wb.v:94$2932'.
Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2794'.
Found and cleaned up 1 empty switch in `\SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$2791'.
Removing empty process `SB_DFFNES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1414$2791'.
Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2790'.
Found and cleaned up 2 empty switches in `\SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$2786'.
Removing empty process `SB_DFFNESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1353$2786'.
Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2785'.
Found and cleaned up 1 empty switch in `\SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$2782'.
Removing empty process `SB_DFFNER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1273$2782'.
Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2781'.
Found and cleaned up 2 empty switches in `\SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$2777'.
Removing empty process `SB_DFFNESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1212$2777'.
Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2776'.
Removing empty process `SB_DFFNS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1138$2774'.
Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2773'.
Found and cleaned up 1 empty switch in `\SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$2771'.
Removing empty process `SB_DFFNSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1088$2771'.
Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2770'.
Removing empty process `SB_DFFNR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:1017$2768'.
Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2767'.
Found and cleaned up 1 empty switch in `\SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$2765'.
Removing empty process `SB_DFFNSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:967$2765'.
Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2764'.
Found and cleaned up 1 empty switch in `\SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$2763'.
Removing empty process `SB_DFFNE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:922$2763'.
Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2762'.
Removing empty process `SB_DFFN.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:882$2761'.
Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2760'.
Found and cleaned up 1 empty switch in `\SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$2757'.
Removing empty process `SB_DFFES.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:803$2757'.
Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2756'.
Found and cleaned up 2 empty switches in `\SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$2752'.
Removing empty process `SB_DFFESS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:742$2752'.
Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2751'.
Found and cleaned up 1 empty switch in `\SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$2748'.
Removing empty process `SB_DFFER.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:662$2748'.
Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2747'.
Found and cleaned up 2 empty switches in `\SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$2743'.
Removing empty process `SB_DFFESR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:601$2743'.
Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2742'.
Removing empty process `SB_DFFS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:527$2740'.
Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2739'.
Found and cleaned up 1 empty switch in `\SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$2737'.
Removing empty process `SB_DFFSS.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:477$2737'.
Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2736'.
Removing empty process `SB_DFFR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:406$2734'.
Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2733'.
Found and cleaned up 1 empty switch in `\SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$2731'.
Removing empty process `SB_DFFSR.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:356$2731'.
Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2730'.
Found and cleaned up 1 empty switch in `\SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$2729'.
Removing empty process `SB_DFFE.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:311$2729'.
Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:0$2728'.
Removing empty process `SB_DFF.$proc$/usr/bin/../share/yosys/ice40/cells_sim.v:271$2727'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1161$2551'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1160$2550'.
Found and cleaned up 97 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4563$2445'.
Found and cleaned up 61 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4303$2387'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4288$2381'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4288$2381'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4274$2380'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4274$2380'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4246$2369'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4246$2369'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4239$2368'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4239$2368'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4232$2367'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4232$2367'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4224$2366'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4224$2366'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4217$2365'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4217$2365'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4208$2364'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4208$2364'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4199$2363'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4199$2363'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4190$2362'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4190$2362'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4136$2305'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4117$2295'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4117$2295'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4108$2292'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4108$2292'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4099$2291'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4099$2291'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4077$2287'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4077$2287'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4063$2286'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4063$2286'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4049$2281'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4049$2281'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4029$2268'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4029$2268'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4022$2267'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4022$2267'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4013$2263'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4013$2263'.
Found and cleaned up 17 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3963$2258'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3963$2258'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3950$2256'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3950$2256'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3939$2255'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3939$2255'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3932$2254'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3932$2254'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3925$2253'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3925$2253'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3914$2249'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3914$2249'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3900$2245'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3900$2245'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3890$2244'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3890$2244'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3880$2243'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3880$2243'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3864$2237'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3864$2237'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3838$2233'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3823$2232'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3808$2229'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3808$2229'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3785$2228'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3773$2227'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3773$2227'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3758$2224'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3758$2224'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3736$2223'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3721$2222'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3697$2221'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3679$2220'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3679$2220'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3667$2213'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3667$2213'.
Found and cleaned up 10 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3631$2204'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3631$2204'.
Found and cleaned up 10 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3603$2202'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3603$2202'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3568$2201'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3532$2198'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3523$2194'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3523$2194'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3506$2193'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3506$2193'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3483$2192'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3459$2191'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3441$2190'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3441$2190'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3427$2189'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3427$2189'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3413$2185'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3413$2185'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3404$2183'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3404$2183'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3350$2167'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3350$2167'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3330$2166'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3301$2163'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3283$2160'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3283$2160'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3272$2159'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3272$2159'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3262$2156'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3262$2156'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3248$2155'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3248$2155'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3228$2150'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3228$2150'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3213$2149'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3213$2149'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3200$2138'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3200$2138'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3183$2134'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3183$2134'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3173$2133'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3173$2133'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3158$2123'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3134$2119'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3119$2118'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3106$2116'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3106$2116'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3084$2115'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3069$2114'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3061$2109'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3061$2109'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3039$2108'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3025$2105'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3025$2105'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3002$2090'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3002$2090'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2991$2086'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2991$2086'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2980$2082'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2980$2082'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2970$2081'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2970$2081'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2958$2078'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2958$2078'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2946$2076'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2946$2076'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2939$2075'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2939$2075'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2928$2073'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2928$2073'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2901$2066'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2901$2066'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2891$2065'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2891$2065'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2882$2063'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2882$2063'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2869$2061'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2869$2061'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2855$2060'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2855$2060'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2847$2059'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2847$2059'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2832$2058'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2832$2058'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2825$2057'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2825$2057'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2815$2056'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2815$2056'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2802$2046'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2802$2046'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2795$2045'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2795$2045'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2784$2044'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2784$2044'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2771$2036'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2771$2036'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2764$2035'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2764$2035'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2756$2034'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2756$2034'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2743$2024'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2743$2024'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2736$2021'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2736$2021'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2726$2020'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2726$2020'.
Found and cleaned up 2 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2716$2019'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2716$2019'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2707$2018'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2707$2018'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2700$2017'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2700$2017'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2652$2007'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2652$2007'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2644$2005'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2644$2005'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2636$2003'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2636$2003'.
Found and cleaned up 3 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2599$2002'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2599$2002'.
Found and cleaned up 11 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2568$2000'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2568$2000'.
Found and cleaned up 11 empty switches in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2538$1998'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2538$1998'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2525$1997'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2525$1997'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1765$1977'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1765$1977'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1713$1970'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1713$1970'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1707$1968'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1707$1968'.
Found and cleaned up 1 empty switch in `\VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1701$1966'.
Removing empty process `VexRiscv.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1701$1966'.
Found and cleaned up 7 empty switches in `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
Removing empty process `InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:302$1776'.
Found and cleaned up 9 empty switches in `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:264$1773'.
Removing empty process `InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:264$1773'.
Found and cleaned up 1 empty switch in `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:219$1752'.
Removing empty process `InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:219$1752'.
Found and cleaned up 3 empty switches in `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:203$1747'.
Removing empty process `InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:203$1747'.
Found and cleaned up 2 empty switches in `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:194$1745'.
Removing empty process `InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:194$1745'.
Found and cleaned up 1 empty switch in `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:186$1744'.
Removing empty process `InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:186$1744'.
Found and cleaned up 1 empty switch in `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:179$1743'.
Removing empty process `InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:179$1743'.
Found and cleaned up 1 empty switch in `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:173$1741'.
Removing empty process `InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:173$1741'.
Found and cleaned up 1 empty switch in `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:167$1734'.
Removing empty process `InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:167$1734'.
Found and cleaned up 1 empty switch in `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:161$1732'.
Removing empty process `InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:161$1732'.
Found and cleaned up 1 empty switch in `\InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:155$1725'.
Removing empty process `InstructionCache.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:155$1725'.
Removing empty process `$paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4397'.
Found and cleaned up 1 empty switch in `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:307$1657'.
Removing empty process `vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:307$1657'.
Removing empty process `vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:303$1651'.
Found and cleaned up 1 empty switch in `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:253$1644'.
Removing empty process `vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:253$1644'.
Removing empty process `vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:250$1643'.
Found and cleaned up 1 empty switch in `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:239$1636'.
Removing empty process `vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:239$1636'.
Found and cleaned up 2 empty switches in `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:231$1633'.
Removing empty process `vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:231$1633'.
Removing empty process `vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:224$1629'.
Found and cleaned up 3 empty switches in `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:200$1628'.
Removing empty process `vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:200$1628'.
Found and cleaned up 1 empty switch in `\vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:178$1625'.
Removing empty process `vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:178$1625'.
Removing empty process `vid_top.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:175$1620'.
Removing empty process `$paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4376'.
Removing empty process `$paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_iserdes.v:0$4355'.
Removing empty process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:0$3674'.
Removing empty process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:0$3673'.
Found and cleaned up 16 empty switches in `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
Removing empty process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:81$3557'.
Found and cleaned up 1 empty switch in `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:73$3556'.
Removing empty process `$paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_spram_gen.v:73$3556'.
Removing empty process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:0$4073'.
Removing empty process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:32$4072'.
Removing empty process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:74$4053'.
Removing empty process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:57$4050'.
Removing empty process `$paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:50$4047'.
Found and cleaned up 1 empty switch in `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:294$3451'.
Removing empty process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:294$3451'.
Removing empty process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:291$3449'.
Removing empty process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:268$3436'.
Found and cleaned up 1 empty switch in `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:241$3428'.
Removing empty process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:241$3428'.
Removing empty process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:221$3416'.
Removing empty process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:198$3408'.
Found and cleaned up 1 empty switch in `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:175$3395'.
Removing empty process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:175$3395'.
Found and cleaned up 7 empty switches in `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:137$3390'.
Removing empty process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:137$3390'.
Found and cleaned up 1 empty switch in `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:130$3389'.
Removing empty process `$paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.$proc$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:130$3389'.
Cleaned up 549 empty switches.

63.3.12. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000100.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000011.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010011.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000011.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010011.
Optimizing module $paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes.
<suppressed ~4 debug messages>
Optimizing module $paramod$d1350f99652fccfa0eca6f20eb458128402cb851\ice40_serdes_dff.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100001.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100010.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100011.
Optimizing module $paramod$9424c184a55595b25ce0f57bb97552df113fdbb7\ice40_serdes_dff.
Optimizing module $paramod$2797d931cd0954c5520f5806e7f1ebd82a03ad28\ice40_serdes_dff.
Optimizing module $paramod$e7ef2081568887628eb303394d34c9d8476d8a88\ice40_serdes_dff.
Optimizing module $paramod$4d8f22cf4ec64d0fb9f63f1c98686217b3799a7d\ice40_serdes_dff.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000011.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000100.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000011.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010011.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000100000.
Optimizing module $paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.
<suppressed ~24 debug messages>
Optimizing module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
<suppressed ~36 debug messages>
Optimizing module $paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.
Optimizing module $paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.
<suppressed ~1 debug messages>
Optimizing module $paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.
<suppressed ~2 debug messages>
Optimizing module $paramod$52fdd5761ec779f8f28128b640a08a8cc595d827\ice40_serdes_dff.
Optimizing module $paramod$3ad1583e0481d446cb74cb52afebc0dc3fce6746\ice40_serdes_dff.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000011.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010011.
Optimizing module $paramod$30ee323e18e10972cd7003a5025831d5a704d820\ice40_serdes_dff.
Optimizing module $paramod$681b594bc9ea94cf8d9a4c2606247a2c915777f4\ice40_serdes_dff.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100001.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100010.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100011.
Optimizing module $paramod$b32caa8ce454d2e243a8fb7a97f312acff133bb3\ice40_serdes_dff.
Optimizing module $paramod$7f62c438601400b211e700d756641d52d2e1073c\ice40_serdes_dff.
Optimizing module $paramod$e44b3f6b88bd9f13d1f900764c097b88a8073837\ice40_serdes_dff.
Optimizing module $paramod$692a90536143b3fec671d73677449145eabc3620\ice40_serdes_dff.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000011.
Optimizing module $paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp.
Optimizing module $paramod\dffer_n\WIDTH=s32'00000000000000000000000000001010.
Optimizing module $paramod$ee292efbb55924cacfdc6c8744bdb7148f59d2f1\ice40_serdes_sync.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000001.
Optimizing module $paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.
Optimizing module $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.
<suppressed ~2 debug messages>
Optimizing module $paramod\delay_bit\DELAY=s32'00000000000000000000000000000100.
Optimizing module $paramod\hdmi_phy_1x\DW=s32'00000000000000000000000000001100.
Optimizing module $paramod$9a9c4528a326fac997fd1fc463b8f4223e2e4501\ice40_oserdes.
Optimizing module $paramod$917d62ab073ab2caba68f39824d52335f3c1a5e3\ice40_oserdes.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000100.
Optimizing module $paramod$087675b5e9c65e52d59a156f0ccae4f673504c8c\ice40_oserdes.
Optimizing module $paramod$5c6db5a604a4655a57dfd9340bd964139a251510\ice40_oserdes.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100000.
Optimizing module $paramod$a13561ec4a4d594cc35622ccd91582314db7bb43\ice40_oserdes.
Optimizing module $paramod$fe37dab75e68305ee07af1db6f0f96490b9fdc39\ice40_oserdes.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100000.
Optimizing module $paramod$75c621542c1e9767613d02b1f3511b93ee44cfa1\ice40_oserdes.
Optimizing module $paramod$863b677bc445782f1534bda513d3ab7f02676b5c\ice40_oserdes.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100000.
Optimizing module $paramod$ee5fa83b1ca770f4f834672f5d772cff0c2d7889\ice40_oserdes.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000011.
Optimizing module $paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.
<suppressed ~3 debug messages>
Optimizing module $paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.
<suppressed ~3 debug messages>
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010010.
Optimizing module $paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100.
Optimizing module $paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.
<suppressed ~6 debug messages>
Optimizing module top.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010011.
Optimizing module $paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.
Optimizing module $paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.
Optimizing module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
<suppressed ~42 debug messages>
Optimizing module $paramod$9a9e2282df54acafd6229f692355382480e5c2ad\qpi_phy_ice40_4x.
Optimizing module $paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.
<suppressed ~2 debug messages>
Optimizing module $paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb.
Optimizing module VexRiscv.
<suppressed ~373 debug messages>
Optimizing module InstructionCache.
<suppressed ~20 debug messages>
Optimizing module sysmgr.
Optimizing module $paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes.
<suppressed ~4 debug messages>
Optimizing module vid_framebuf.
Optimizing module vid_palette.
Optimizing module vid_top.
<suppressed ~2 debug messages>
Optimizing module $paramod$728f7da6b691d49936b0c3bda28a068249eab591\ice40_serdes_dff.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000011.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010011.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000011.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010011.
Optimizing module $paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes.
<suppressed ~4 debug messages>
Optimizing module $paramod$152f54a12eb3ca1dd5881a1a75733b2cc275300e\ice40_serdes_dff.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100001.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100010.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100011.
Optimizing module $paramod$287ed5c83870694bd6af0f98e8abdcf9f10a3b0d\ice40_serdes_dff.
Optimizing module $paramod$609ef96eefd5f217e59829af7272b2c75ca4270a\ice40_serdes_dff.
Optimizing module $paramod$cc9a6e6bf39368ff82a94c2c06971bb1433935c4\ice40_serdes_dff.
Optimizing module $paramod$585d871e3f028093b352aaf4a6a5ed67b111fc87\ice40_serdes_dff.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000011.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000100.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000011.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010011.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000011.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010011.
Optimizing module $paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes.
<suppressed ~4 debug messages>
Optimizing module $paramod$eddda7c69c5b1281f2431cd4e70f1617a655638d\ice40_serdes_dff.
Optimizing module $paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.
<suppressed ~5042 debug messages>
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100001.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100010.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100011.
Optimizing module $paramod$4f4cafaa8e148481ffc96bfe5f39236edef69b27\ice40_serdes_dff.
Optimizing module $paramod$c937d5e4376f8f2580c5fe8fd2426ef1292329e8\ice40_serdes_dff.
Optimizing module $paramod$3b1dc861a4d0285a9c0e28e86e84bf3f3bf78af8\ice40_serdes_dff.
Optimizing module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100000.
Optimizing module $paramod$8364285540c9e5de4006551b06ee5b25c31d3ac4\ice40_serdes_dff.
Optimizing module $paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000000.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000001.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000010.
Optimizing module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000011.
Optimizing module $paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.
<suppressed ~11 debug messages>

63.4. Executing FLATTEN pass (flatten design).
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000100.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000000011.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011001000010011.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000000011.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011000000010011.
Deleting now unused module $paramod$0e9701ec0ff3618e82c6b3c7773f21bce1c1aa12\ice40_iserdes.
Deleting now unused module $paramod$d1350f99652fccfa0eca6f20eb458128402cb851\ice40_serdes_dff.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100001.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100010.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100011.
Deleting now unused module $paramod$9424c184a55595b25ce0f57bb97552df113fdbb7\ice40_serdes_dff.
Deleting now unused module $paramod$2797d931cd0954c5520f5806e7f1ebd82a03ad28\ice40_serdes_dff.
Deleting now unused module $paramod$e7ef2081568887628eb303394d34c9d8476d8a88\ice40_serdes_dff.
Deleting now unused module $paramod$4d8f22cf4ec64d0fb9f63f1c98686217b3799a7d\ice40_serdes_dff.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000011.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000011011010000100.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000000011.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000010011.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000100000000100000.
Deleting now unused module $paramod$f1ce7771bad0baf70eccc6d92471271ce6f4b9b5\ice40_ebr.
Deleting now unused module $paramod$a8a608399bdc7898dc3bb0c8613f1d43404870fb\mc_core.
Deleting now unused module $paramod$1becf43d58396d216852697b52a37807eb7ec9e3\delay_bus.
Deleting now unused module $paramod\uart_tx\DIV_WIDTH=s32'00000000000000000000000000001100.
Deleting now unused module $paramod$cae5572c97b54b153bd196ca558b9ddbfed34bda\uart_rx.
Deleting now unused module $paramod$52fdd5761ec779f8f28128b640a08a8cc595d827\ice40_serdes_dff.
Deleting now unused module $paramod$3ad1583e0481d446cb74cb52afebc0dc3fce6746\ice40_serdes_dff.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000000011.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000000000010011.
Deleting now unused module $paramod$30ee323e18e10972cd7003a5025831d5a704d820\ice40_serdes_dff.
Deleting now unused module $paramod$681b594bc9ea94cf8d9a4c2606247a2c915777f4\ice40_serdes_dff.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100001.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100010.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100011.
Deleting now unused module $paramod$b32caa8ce454d2e243a8fb7a97f312acff133bb3\ice40_serdes_dff.
Deleting now unused module $paramod$7f62c438601400b211e700d756641d52d2e1073c\ice40_serdes_dff.
Deleting now unused module $paramod$e44b3f6b88bd9f13d1f900764c097b88a8073837\ice40_serdes_dff.
Deleting now unused module $paramod$692a90536143b3fec671d73677449145eabc3620\ice40_serdes_dff.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000011.
Deleting now unused module $paramod$3ebcb2129805027011086c045e6bb4ce235a9e88\ram_sdp.
Deleting now unused module $paramod\dffer_n\WIDTH=s32'00000000000000000000000000001010.
Deleting now unused module $paramod$ee292efbb55924cacfdc6c8744bdb7148f59d2f1\ice40_serdes_sync.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000001.
Deleting now unused module $paramod$c32249f57cf18aae6c3720d875a1d87207eed63c\fifo_sync_ram.
Deleting now unused module $paramod$cbe8fcb6b70e4a368054085d17602501503282a1\vid_tgen.
Deleting now unused module $paramod\delay_bit\DELAY=s32'00000000000000000000000000000100.
Deleting now unused module $paramod\hdmi_phy_1x\DW=s32'00000000000000000000000000001100.
Deleting now unused module $paramod$9a9c4528a326fac997fd1fc463b8f4223e2e4501\ice40_oserdes.
Deleting now unused module $paramod$917d62ab073ab2caba68f39824d52335f3c1a5e3\ice40_oserdes.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000011010000100.
Deleting now unused module $paramod$087675b5e9c65e52d59a156f0ccae4f673504c8c\ice40_oserdes.
Deleting now unused module $paramod$5c6db5a604a4655a57dfd9340bd964139a251510\ice40_oserdes.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100000.
Deleting now unused module $paramod$a13561ec4a4d594cc35622ccd91582314db7bb43\ice40_oserdes.
Deleting now unused module $paramod$fe37dab75e68305ee07af1db6f0f96490b9fdc39\ice40_oserdes.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100000.
Deleting now unused module $paramod$75c621542c1e9767613d02b1f3511b93ee44cfa1\ice40_oserdes.
Deleting now unused module $paramod$863b677bc445782f1534bda513d3ab7f02676b5c\ice40_oserdes.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000011010010100000.
Deleting now unused module $paramod$ee5fa83b1ca770f4f834672f5d772cff0c2d7889\ice40_oserdes.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000000011.
Deleting now unused module $paramod$8b22e2c4b4d1e8b8ca3524a85d03e9beac836863\fifo_sync_shift.
Deleting now unused module $paramod$dafc3a7f4a5bcc8b3adb4c007b6f574c47147813\fifo_sync_shift.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010010.
Deleting now unused module $paramod\mc_tag_match\TAG_WIDTH=s32'00000000000000000000000000001100.
Deleting now unused module $paramod$3dde714f422b83739ea51939bb54a1d4747be207\glitch_filter.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000000001000010011.
Deleting now unused module $paramod$7b7d084455f833cfdede68301d832939818fdbc1\soc_bram.
Deleting now unused module $paramod$8cc0a9cf304a487149b7985624e92ee239a362b6\mc_tag_ram.
Deleting now unused module $paramod$59a1d02c57d05f4d466ea9b0891b874c69f2b914\qpi_memctrl.
Deleting now unused module $paramod$9a9e2282df54acafd6229f692355382480e5c2ad\qpi_phy_ice40_4x.
Deleting now unused module $paramod$6b84e3fabbb4b753fd7ae6545e97cd268400ab72\uart_wb.
Deleting now unused module $paramod$cfcaad11b8c62f8a1e1624a27a246465a59e45e7\ice40_rgb_wb.
Deleting now unused module VexRiscv.
Deleting now unused module InstructionCache.
Deleting now unused module sysmgr.
Deleting now unused module $paramod$c937df4c258ba3feed83404fb87e6cc4fb9fbffd\ice40_iserdes.
Deleting now unused module vid_framebuf.
Deleting now unused module vid_palette.
Deleting now unused module vid_top.
Deleting now unused module $paramod$728f7da6b691d49936b0c3bda28a068249eab591\ice40_serdes_dff.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000000011.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001001000010011.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000000011.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001000000010011.
Deleting now unused module $paramod$14e5d95e036b4742363dfea0c94e50791839025a\ice40_iserdes.
Deleting now unused module $paramod$152f54a12eb3ca1dd5881a1a75733b2cc275300e\ice40_serdes_dff.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100001.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100010.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000001010010100011.
Deleting now unused module $paramod$287ed5c83870694bd6af0f98e8abdcf9f10a3b0d\ice40_serdes_dff.
Deleting now unused module $paramod$609ef96eefd5f217e59829af7272b2c75ca4270a\ice40_serdes_dff.
Deleting now unused module $paramod$cc9a6e6bf39368ff82a94c2c06971bb1433935c4\ice40_serdes_dff.
Deleting now unused module $paramod$585d871e3f028093b352aaf4a6a5ed67b111fc87\ice40_serdes_dff.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000011.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000001011010000100.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000000011.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010001000010011.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000000011.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010000000010011.
Deleting now unused module $paramod$67159177885044a3572460fa032eb51bd80cf94f\ice40_iserdes.
Deleting now unused module $paramod$eddda7c69c5b1281f2431cd4e70f1617a655638d\ice40_serdes_dff.
Deleting now unused module $paramod$9febc798f0ace58d1e05d1c8fc5ca0bae9faad8b\ice40_spram_gen.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100001.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100010.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000010010010100011.
Deleting now unused module $paramod$4f4cafaa8e148481ffc96bfe5f39236edef69b27\ice40_serdes_dff.
Deleting now unused module $paramod$c937d5e4376f8f2580c5fe8fd2426ef1292329e8\ice40_serdes_dff.
Deleting now unused module $paramod$3b1dc861a4d0285a9c0e28e86e84bf3f3bf78af8\ice40_serdes_dff.
Deleting now unused module $paramod\ice40_serdes_dff\NEG=1'0\SERDES_GRP=32'00000000000000000000010010100000.
Deleting now unused module $paramod$8364285540c9e5de4006551b06ee5b25c31d3ac4\ice40_serdes_dff.
Deleting now unused module $paramod\ice40_serdes_crg\NO_CLOCK_2X=s32'00000000000000000000000000000001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000000.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000001.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000010.
Deleting now unused module $paramod\ice40_serdes_dff\SERDES_GRP=32'00000000000000000010011010000011.
Deleting now unused module $paramod\mc_bus_vex\WB_N=s32'00000000000000000000000000000100.
<suppressed ~188 debug messages>

63.5. Executing TRIBUF pass.

63.6. Executing DEMINOUT pass (demote inout ports to input or output).

63.7. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~54 debug messages>

63.8. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 507 unused cells and 9005 unused wires.
<suppressed ~854 debug messages>

63.9. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

63.10. Executing OPT pass (performing simple optimizations).

63.10.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~4 debug messages>

63.10.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~924 debug messages>
Removed a total of 309 cells.

63.10.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port B of cell $flatten\cpu_I.\IBusCachedPlugin_cache.$procmux$7125: \cpu_I.IBusCachedPlugin_cache.lineLoader_flushCounter -> { 1'1 \cpu_I.IBusCachedPlugin_cache.lineLoader_flushCounter [5:0] }
  Analyzing evaluation results.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10033.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10033.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10033.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10033.
    dead port 5/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10033.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10055.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10055.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10055.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10055.
    dead port 5/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10055.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10085.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10085.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10085.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10085.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10093.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10093.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10093.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10093.
    dead port 5/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10093.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10111.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10111.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10111.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10111.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10145.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10145.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10145.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10145.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10157.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10157.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10157.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10157.
    dead port 5/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10157.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10183.
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    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9529.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9529.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9529.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9546.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9546.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9546.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9546.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9565.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9565.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9565.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9565.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9586.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9586.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9586.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9586.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9609.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9609.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9609.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9609.
    dead port 5/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9609.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9634.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9634.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9634.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9634.
    dead port 5/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9634.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9661.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9661.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9661.
    dead port 5/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9661.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9690.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9690.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9690.
    dead port 5/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9690.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9721.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9721.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9721.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9721.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9754.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9754.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9754.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9754.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9789.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9789.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9789.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9789.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9826.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9826.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9826.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9826.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9833.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9833.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9833.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9833.
    dead port 5/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9833.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9843.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9843.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9843.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9843.
    dead port 5/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9843.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9857.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9857.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9857.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9857.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9873.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9873.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9873.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9873.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9893.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9893.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9893.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9893.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9917.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9917.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9917.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9917.
    dead port 5/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9917.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9945.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9945.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9945.
    dead port 5/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9945.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9977.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9977.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9977.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$9977.
    dead port 2/2 on $mux $flatten\cache_bus_I.$procmux$13189.
    dead port 2/2 on $mux $flatten\cache_bus_I.$procmux$13197.
    dead port 2/2 on $mux $flatten\cache_bus_I.$procmux$13207.
    dead port 2/2 on $mux $flatten\cache_bus_I.$procmux$13218.
    dead port 1/2 on $mux $flatten\cache_bus_I.$procmux$13231.
    dead port 2/2 on $mux $flatten\cache_bus_I.$procmux$13233.
    dead port 2/2 on $mux $flatten\cache_bus_I.$procmux$13245.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4735.
    dead port 1/2 on $mux $flatten\cache_I.$procmux$4738.
    dead port 1/2 on $mux $flatten\cache_I.$procmux$4744.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4750.
    dead port 1/2 on $mux $flatten\cache_I.$procmux$4753.
    dead port 1/2 on $mux $flatten\cache_I.$procmux$4759.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4765.
    dead port 1/2 on $mux $flatten\cache_I.$procmux$4768.
    dead port 1/2 on $mux $flatten\cache_I.$procmux$4774.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4780.
    dead port 1/2 on $mux $flatten\cache_I.$procmux$4783.
    dead port 1/2 on $mux $flatten\cache_I.$procmux$4789.
    dead port 1/2 on $mux $flatten\cache_I.$procmux$4796.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4799.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4801.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4808.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4810.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4816.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6384.
    dead port 1/2 on $mux $flatten\cache_I.$procmux$4823.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6404.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4826.
    dead port 1/2 on $mux $flatten\cpu_I.$procmux$6526.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4828.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4835.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4837.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4843.
    dead port 1/2 on $mux $flatten\cpu_I.$procmux$6547.
    dead port 1/2 on $mux $flatten\cpu_I.$procmux$6550.
    dead port 1/2 on $mux $flatten\cpu_I.$procmux$6556.
    dead port 1/2 on $mux $flatten\cpu_I.$procmux$6569.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6571.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6577.
    dead port 1/2 on $mux $flatten\cpu_I.$procmux$6587.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6589.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6595.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6613.
    dead port 1/2 on $mux $flatten\cpu_I.$procmux$6626.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6628.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6634.
    dead port 1/2 on $mux $flatten\cpu_I.$procmux$6644.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6646.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6652.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6670.
    dead port 1/2 on $mux $flatten\cpu_I.$procmux$6722.
    dead port 1/2 on $mux $flatten\cpu_I.$procmux$6734.
    dead port 1/2 on $mux $flatten\cache_I.$procmux$4850.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4853.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4855.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6808.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6865.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6886.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6931.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6953.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6963.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6965.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6971.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6981.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6983.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$6989.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$7001.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$7007.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$7016.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$7026.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$7028.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$7034.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$7044.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$7046.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$7052.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$7064.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$7070.
    dead port 2/2 on $mux $flatten\cpu_I.$procmux$7079.
    dead port 2/2 on $mux $flatten\cpu_I.\IBusCachedPlugin_cache.$procmux$7167.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4862.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4864.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4870.
    dead port 1/2 on $mux $flatten\cache_I.$procmux$4877.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4880.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4882.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4889.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4891.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4897.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5170.
    dead port 1/2 on $mux $flatten\memctrl_I.$procmux$5173.
    dead port 1/2 on $mux $flatten\memctrl_I.$procmux$5182.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5184.
    dead port 1/2 on $mux $flatten\memctrl_I.$procmux$5187.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5209.
    dead port 1/2 on $mux $flatten\memctrl_I.$procmux$5212.
    dead port 1/2 on $mux $flatten\memctrl_I.$procmux$5242.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5333.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5504.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5510.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5513.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5516.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5519.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5534.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5548.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5646.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5657.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5718.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$4997.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5725.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5733.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5742.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$5003.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5752.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5763.
    dead port 1/2 on $mux $flatten\memctrl_I.$procmux$5776.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5778.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$5010.
    dead port 2/2 on $mux $flatten\memctrl_I.$procmux$5790.
    dead port 2/2 on $mux $flatten\cache_I.$procmux$5018.
    dead port 1/2 on $mux $flatten\uart_I.\uart_rx_I.\genblk1.gf_I.$procmux$5124.
    dead port 2/2 on $mux $flatten\vid_I.\tgen_I.$procmux$5074.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10013.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10013.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10013.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10013.
    dead port 1/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10022.
    dead port 2/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10022.
    dead port 3/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10022.
    dead port 4/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10022.
    dead port 5/5 on $pmux $flatten\cache_I.\data_ram_I.$procmux$10022.
    dead port 2/2 on $mux $flatten\vid_I.\tgen_I.$procmux$5089.
Removed 1259 multiplexer ports.
<suppressed ~415 debug messages>

63.10.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\cache_bus_I.$procmux$13248: { $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:177$3396_Y $flatten\cache_bus_I.$procmux$13219_CMP $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:230$3426_Y $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:264$3433_Y $auto$opt_reduce.cc:134:opt_pmux$21106 $flatten\cache_bus_I.$procmux$13167_CMP }
    New ctrl vector for $pmux cell $flatten\cpu_I.$procmux$6394: $auto$opt_reduce.cc:134:opt_pmux$21108
    New ctrl vector for $pmux cell $flatten\cpu_I.$procmux$6539: { $flatten\cpu_I.$procmux$6542_CMP $auto$opt_reduce.cc:134:opt_pmux$21110 }
    Consolidated identical input bits for $mux cell $flatten\bram_I.$procmux$5130:
      Old ports: A=0, B=32'11111111000000000000000000000000, Y=$flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_EN[31:0]$3365
      New ports: A=1'0, B=1'1, Y=$flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_EN[31:0]$3365 [24]
      New connections: { $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_EN[31:0]$3365 [31:25] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_EN[31:0]$3365 [23:0] } = { $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_EN[31:0]$3365 [24] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_EN[31:0]$3365 [24] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_EN[31:0]$3365 [24] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_EN[31:0]$3365 [24] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_EN[31:0]$3365 [24] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_EN[31:0]$3365 [24] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_EN[31:0]$3365 [24] 24'000000000000000000000000 }
    Consolidated identical input bits for $mux cell $flatten\bram_I.$procmux$5139:
      Old ports: A=0, B=16711680, Y=$flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_EN[31:0]$3362
      New ports: A=1'0, B=1'1, Y=$flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_EN[31:0]$3362 [16]
      New connections: { $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_EN[31:0]$3362 [31:17] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_EN[31:0]$3362 [15:0] } = { 8'00000000 $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_EN[31:0]$3362 [16] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_EN[31:0]$3362 [16] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_EN[31:0]$3362 [16] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_EN[31:0]$3362 [16] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_EN[31:0]$3362 [16] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_EN[31:0]$3362 [16] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_EN[31:0]$3362 [16] 16'0000000000000000 }
    Consolidated identical input bits for $mux cell $flatten\bram_I.$procmux$5148:
      Old ports: A=0, B=65280, Y=$flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_EN[31:0]$3359
      New ports: A=1'0, B=1'1, Y=$flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_EN[31:0]$3359 [8]
      New connections: { $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_EN[31:0]$3359 [31:9] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_EN[31:0]$3359 [7:0] } = { 16'0000000000000000 $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_EN[31:0]$3359 [8] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_EN[31:0]$3359 [8] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_EN[31:0]$3359 [8] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_EN[31:0]$3359 [8] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_EN[31:0]$3359 [8] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_EN[31:0]$3359 [8] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_EN[31:0]$3359 [8] 8'00000000 }
    Consolidated identical input bits for $mux cell $flatten\bram_I.$procmux$5157:
      Old ports: A=0, B=255, Y=$flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_EN[31:0]$3356
      New ports: A=1'0, B=1'1, Y=$flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_EN[31:0]$3356 [0]
      New connections: $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_EN[31:0]$3356 [31:1] = { 24'000000000000000000000000 $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_EN[31:0]$3356 [0] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_EN[31:0]$3356 [0] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_EN[31:0]$3356 [0] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_EN[31:0]$3356 [0] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_EN[31:0]$3356 [0] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_EN[31:0]$3356 [0] $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_EN[31:0]$3356 [0] }
    Consolidated identical input bits for $mux cell $flatten\cpu_I.$procmux$7093:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973
      New ports: A=1'0, B=1'1, Y=$flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0]
      New connections: $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [31:1] = { $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] $flatten\cpu_I.$0$memwr$\RegFilePlugin_regFile$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1715$1782_EN[31:0]$1973 [0] }
    Consolidated identical input bits for $mux cell $flatten\cpu_I.\IBusCachedPlugin_cache.$procmux$7181:
      Old ports: A=0, B=32'11111111111111111111111111111111, Y=$flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737
      New ports: A=1'0, B=1'1, Y=$flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0]
      New connections: $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [31:1] = { $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:169$1720_EN[31:0]$1737 [0] }
    Consolidated identical input bits for $mux cell $flatten\cpu_I.\IBusCachedPlugin_cache.$procmux$7192:
      Old ports: A=23'00000000000000000000000, B=23'11111111111111111111111, Y=$flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728
      New ports: A=1'0, B=1'1, Y=$flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0]
      New connections: $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [22:1] = { $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] $flatten\cpu_I.\IBusCachedPlugin_cache.$0$memwr$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:157$1719_EN[22:0]$1728 [0] }
    New ctrl vector for $pmux cell $flatten\memctrl_I.$procmux$5499: { $flatten\memctrl_I.$procmux$5503_CMP $flatten\memctrl_I.$procmux$5502_CMP $auto$opt_reduce.cc:134:opt_pmux$21112 }
    New ctrl vector for $pmux cell $flatten\memctrl_I.$procmux$5551: { $flatten\memctrl_I.$procmux$5557_CMP $auto$opt_reduce.cc:134:opt_pmux$21114 $flatten\memctrl_I.$procmux$5554_CMP $flatten\memctrl_I.$procmux$5553_CMP $flatten\memctrl_I.$procmux$5552_CMP }
    New ctrl vector for $pmux cell $flatten\memctrl_I.$procmux$5629: { $flatten\memctrl_I.$procmux$5644_CMP $flatten\memctrl_I.$procmux$5643_CMP $flatten\memctrl_I.$procmux$5642_CMP $auto$opt_reduce.cc:134:opt_pmux$21122 $auto$opt_reduce.cc:134:opt_pmux$21120 $auto$opt_reduce.cc:134:opt_pmux$21118 $auto$opt_reduce.cc:134:opt_pmux$21116 }
    New ctrl vector for $pmux cell $flatten\memctrl_I.$procmux$5667: { \memctrl_I.ectl_grant $flatten\memctrl_I.$procmux$5669_CMP $auto$opt_reduce.cc:134:opt_pmux$21124 }
    New ctrl vector for $pmux cell $flatten\memctrl_I.$procmux$5674: { \memctrl_I.ectl_grant $auto$opt_reduce.cc:134:opt_pmux$21126 $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:509$3047_Y }
    New ctrl vector for $pmux cell $flatten\memctrl_I.$procmux$5681: { \memctrl_I.ectl_idle \memctrl_I.ectl_grant $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:509$3046_Y $auto$opt_reduce.cc:134:opt_pmux$21128 }
    New ctrl vector for $pmux cell $flatten\memctrl_I.$procmux$5688: { \memctrl_I.ectl_idle \memctrl_I.ectl_grant $auto$opt_reduce.cc:134:opt_pmux$21130 }
    Consolidated identical input bits for $mux cell $flatten\uart_I.\uart_rx_fifo_I.\ram_I.$procmux$5052:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403
      New ports: A=1'0, B=1'1, Y=$flatten\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0]
      New connections: $flatten\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [7:1] = { $flatten\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0] $flatten\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0] $flatten\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0] $flatten\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0] $flatten\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0] $flatten\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0] $flatten\uart_I.\uart_rx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0] }
    Consolidated identical input bits for $mux cell $flatten\uart_I.\uart_tx_fifo_I.\ram_I.$procmux$5052:
      Old ports: A=8'00000000, B=8'11111111, Y=$flatten\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403
      New ports: A=1'0, B=1'1, Y=$flatten\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0]
      New connections: $flatten\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [7:1] = { $flatten\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0] $flatten\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0] $flatten\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0] $flatten\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0] $flatten\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0] $flatten\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0] $flatten\uart_I.\uart_tx_fifo_I.\ram_I.$0$memwr$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:47$4399_EN[7:0]$4403 [0] }
  Optimizing cells in module \top.
Performed a total of 21 changes.

63.10.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~42 debug messages>
Removed a total of 14 cells.

63.10.6. Executing OPT_DFF pass (perform DFF optimizations).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$20356 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$20289 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$20222 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$20155 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$20088 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$20021 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$19810 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$19599 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$19388 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$19177 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$18966 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$18755 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$18544 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$18333 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$18122 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$17911 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$17700 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$17489 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$17278 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$17067 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$16856 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$16645 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$16434 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$16223 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$16012 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$15801 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$15590 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$15379 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$15168 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$14957 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$14746 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$14535 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$14324 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$14113 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$13902 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$13691 ($dlatch) from module top (changing to combinatorial circuit).
Handling always-active async load on $flatten\cache_I.\data_ram_I.$auto$proc_dlatch.cc:433:proc_dlatch$13480 ($dlatch) from module top (changing to combinatorial circuit).
Changing const-value async load to async reset on $flatten\cpu_I.$procdff$20810 ($aldff) from module top.
Setting constant 0-bit at position 12 on $flatten\cache_I.\genblk1[0].tag_ram_I.$procdff$20627 ($dff) from module top.
Setting constant 0-bit at position 13 on $flatten\cache_I.\genblk1[0].tag_ram_I.$procdff$20627 ($dff) from module top.
Setting constant 0-bit at position 0 on $flatten\cpu_I.$procdff$20708 ($dff) from module top.
Setting constant 0-bit at position 0 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 1 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 2 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 3 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 4 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 5 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 6 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 7 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 8 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 9 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 10 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 11 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 12 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 13 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 14 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 15 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 16 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 17 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 18 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 19 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 20 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 21 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 22 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 23 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 24 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 25 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 26 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 27 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 28 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 29 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 30 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 31 on $flatten\cpu_I.$procdff$20725 ($dff) from module top.
Setting constant 0-bit at position 12 on $flatten\cache_I.\genblk1[1].tag_ram_I.$procdff$20627 ($dff) from module top.
Setting constant 0-bit at position 13 on $flatten\cache_I.\genblk1[1].tag_ram_I.$procdff$20627 ($dff) from module top.
Setting constant 0-bit at position 12 on $flatten\cache_I.\genblk1[2].tag_ram_I.$procdff$20627 ($dff) from module top.
Setting constant 0-bit at position 13 on $flatten\cache_I.\genblk1[2].tag_ram_I.$procdff$20627 ($dff) from module top.
Setting constant 0-bit at position 12 on $flatten\cache_I.\genblk1[3].tag_ram_I.$procdff$20627 ($dff) from module top.
Setting constant 0-bit at position 13 on $flatten\cache_I.\genblk1[3].tag_ram_I.$procdff$20627 ($dff) from module top.

63.10.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 409 unused wires.
<suppressed ~47 debug messages>

63.10.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~9 debug messages>

63.10.9. Rerunning OPT passes. (Maybe there is more to do..)

63.10.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~370 debug messages>

63.10.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New ctrl vector for $pmux cell $flatten\memctrl_I.$procmux$5793: { \cache_I.mi_ready \memctrl_I.ectl_grant $flatten\memctrl_I.$procmux$5669_CMP $auto$opt_reduce.cc:134:opt_pmux$21136 $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:765$3156_Y $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:516$3052_Y }
  Optimizing cells in module \top.
Performed a total of 1 changes.

63.10.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.10.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $flatten\cpu_I.$procdff$20707 ($dff) from module top.

63.10.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 3 unused cells and 7 unused wires.
<suppressed ~5 debug messages>

63.10.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

63.10.16. Rerunning OPT passes. (Maybe there is more to do..)

63.10.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~368 debug messages>

63.10.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

63.10.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.10.20. Executing OPT_DFF pass (perform DFF optimizations).

63.10.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
<suppressed ~1 debug messages>

63.10.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.10.23. Rerunning OPT passes. (Maybe there is more to do..)

63.10.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~368 debug messages>

63.10.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

63.10.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.10.27. Executing OPT_DFF pass (perform DFF optimizations).

63.10.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.10.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.10.30. Finished OPT passes. (There is nothing left to do.)

63.11. Executing FSM pass (extract and optimize FSM).

63.11.1. Executing FSM_DETECT pass (finding FSMs in design).
Not marking top.cache_I.ctrl_state as FSM state register:
    Circuit seems to be self-resetting.
Not marking top.cache_I.ev_way_r as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register top.cache_bus_I.state.
Not marking top.cpu_I.CsrPlugin_exceptionPortCtrl_exceptionContext_code as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking top.cpu_I.CsrPlugin_interrupt_code as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking top.cpu_I.CsrPlugin_interrupt_targetPrivilege as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking top.memctrl_I.so_dst as FSM state register:
    Users of register don't seem to benefit from recoding.
Not marking top.memctrl_I.so_mode as FSM state register:
    Users of register don't seem to benefit from recoding.
Found FSM state register top.memctrl_I.state.

63.11.2. Executing FSM_EXTRACT pass (extracting FSM from design).
Extracting FSM `\cache_bus_I.state' from module `\top'.
  found $dff cell for state register: $flatten\cache_bus_I.$procdff$20906
  root of input selection tree: $flatten\cache_bus_I.$0\state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \cache_I.rst
  found ctrl input: $flatten\cache_bus_I.$procmux$13167_CMP
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$21106
  found ctrl input: $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:264$3433_Y
  found ctrl input: $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:230$3426_Y
  found ctrl input: $flatten\cache_bus_I.$procmux$13219_CMP
  found ctrl input: $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:177$3396_Y
  found ctrl input: \cache_bus_I.wb_ack_i
  found state code: 3'000
  found ctrl input: \cache_I.resp_ack
  found ctrl input: \cache_bus_I.ib_addr_last
  found ctrl input: \cache_bus_I.ctrl_is_cache
  found state code: 3'110
  found state code: 3'101
  found ctrl input: \cache_bus_I.i_axi_ar_valid
  found ctrl input: \cpu_I.dBus_cmd_halfPipe_regs_valid
  found ctrl input: \cpu_I.dBus_cmd_halfPipe_regs_payload_address [31]
  found ctrl input: \cpu_I.dBus_cmd_halfPipe_regs_payload_address [30]
  found state code: 3'010
  found state code: 3'001
  found state code: 3'011
  found ctrl input: \cpu_I.IBusCachedPlugin_cache.lineLoader_address [30]
  found state code: 3'100
  found ctrl output: $flatten\cache_bus_I.$procmux$13219_CMP
  found ctrl output: $flatten\cache_bus_I.$procmux$13167_CMP
  found ctrl output: $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:278$3443_Y
  found ctrl output: $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:264$3433_Y
  found ctrl output: $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:230$3426_Y
  found ctrl output: $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:227$3423_Y
  found ctrl output: $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:177$3396_Y
  ctrl inputs: { $auto$opt_reduce.cc:134:opt_pmux$21106 \cache_I.resp_ack \cache_I.rst \cache_bus_I.i_axi_ar_valid \cache_bus_I.ctrl_is_cache \cache_bus_I.ib_addr_last \cache_bus_I.wb_ack_i \cpu_I.dBus_cmd_halfPipe_regs_valid \cpu_I.dBus_cmd_halfPipe_regs_payload_address [31:30] \cpu_I.IBusCachedPlugin_cache.lineLoader_address [30] }
  ctrl outputs: { $flatten\cache_bus_I.$0\state[2:0] $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:177$3396_Y $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:227$3423_Y $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:230$3426_Y $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:264$3433_Y $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:278$3443_Y $flatten\cache_bus_I.$procmux$13167_CMP $flatten\cache_bus_I.$procmux$13219_CMP }
  transition:      3'000 11'--00---0--- ->      3'000 10'0001000000
  transition:      3'000 11'--00---100- ->      3'010 10'0101000000
  transition:      3'000 11'--00---101- ->      3'001 10'0011000000
  transition:      3'000 11'--00---11-- ->      3'011 10'0111000000
  transition:      3'000 11'--01------0 ->      3'101 10'1011000000
  transition:      3'000 11'--01------1 ->      3'100 10'1001000000
  transition:      3'000 11'--1-------- ->      3'000 10'0001000000
  transition:      3'100 11'-00-------- ->      3'100 10'1000000001
  transition:      3'100 11'-10-------- ->      3'101 10'1010000001
  transition:      3'100 11'--1-------- ->      3'000 10'0000000001
  transition:      3'010 11'--0-------- ->      3'000 10'0000000100
  transition:      3'010 11'--1-------- ->      3'000 10'0000000100
  transition:      3'110 11'--0-------- ->      3'000 10'0000100000
  transition:      3'110 11'--1-------- ->      3'000 10'0000100000
  transition:      3'001 11'-00-------- ->      3'001 10'0010001000
  transition:      3'001 11'-10-------- ->      3'000 10'0000001000
  transition:      3'001 11'--1-------- ->      3'000 10'0000001000
  transition:      3'101 11'--0--0----- ->      3'101 10'1010010000
  transition:      3'101 11'--0-01----- ->      3'000 10'0000010000
  transition:      3'101 11'--0-11----- ->      3'110 10'1100010000
  transition:      3'101 11'--1-------- ->      3'000 10'0000010000
  transition:      3'011 11'--0---0---- ->      3'011 10'0110000010
  transition:      3'011 11'--0---1---- ->      3'000 10'0000000010
  transition:      3'011 11'--1-------- ->      3'000 10'0000000010
Extracting FSM `\memctrl_I.state' from module `\top'.
  found $dff cell for state register: $flatten\memctrl_I.$procdff$20660
  root of input selection tree: $flatten\memctrl_I.$0\state[2:0]
  found reset state: 3'000 (guessed from mux tree)
  found ctrl input: \cache_I.rst
  found ctrl input: $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:516$3052_Y
  found ctrl input: $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:765$3156_Y
  found ctrl input: $auto$opt_reduce.cc:134:opt_pmux$21136
  found ctrl input: $flatten\memctrl_I.$procmux$5669_CMP
  found ctrl input: \memctrl_I.ectl_grant
  found ctrl input: \cache_I.mi_ready
  found ctrl input: \memctrl_I.pause_cnt [3]
  found state code: 3'000
  found ctrl input: \memctrl_I.so_valid
  found state code: 3'110
  found ctrl input: $flatten\memctrl_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:484$3040_Y
  found state code: 3'101
  found ctrl input: \memctrl_I.so_ld_now
  found state code: 3'100
  found ctrl input: $flatten\memctrl_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:480$3039_Y
  found ctrl input: \memctrl_I.mi_valid
  found ctrl input: \memctrl_I.ectl_req
  found state code: 3'001
  found ctrl input: \memctrl_I.mi_rw
  found state code: 3'010
  found state code: 3'011
  found ctrl output: $flatten\memctrl_I.$procmux$5669_CMP
  found ctrl output: $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:765$3156_Y
  found ctrl output: $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:516$3052_Y
  found ctrl output: $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:509$3047_Y
  found ctrl output: $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:509$3046_Y
  found ctrl output: \memctrl_I.ectl_grant
  found ctrl output: \cache_I.mi_ready
  ctrl inputs: { \memctrl_I.mi_rw \memctrl_I.mi_valid \memctrl_I.ectl_req \memctrl_I.pause_cnt [3] \memctrl_I.so_ld_now \memctrl_I.so_valid $flatten\memctrl_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:480$3039_Y $flatten\memctrl_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:484$3040_Y \cache_I.rst $auto$opt_reduce.cc:134:opt_pmux$21136 }
  ctrl outputs: { \memctrl_I.ectl_grant $flatten\memctrl_I.$0\state[2:0] $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:509$3046_Y $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:509$3047_Y $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:516$3052_Y $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:765$3156_Y $flatten\memctrl_I.$procmux$5669_CMP \cache_I.mi_ready }
  transition:      3'000 10'-00-----0- ->      3'000 10'0000000001
  transition:      3'000 10'-01-----0- ->      3'001 10'0001000001
  transition:      3'000 10'01------0- ->      3'010 10'0010000001
  transition:      3'000 10'11------0- ->      3'011 10'0011000001
  transition:      3'000 10'--------1- ->      3'000 10'0000000001
  transition:      3'100 10'-------00- ->      3'100 10'0100010000
  transition:      3'100 10'-------10- ->      3'101 10'0101010000
  transition:      3'100 10'--------1- ->      3'000 10'0000010000
  transition:      3'010 10'-------00- ->      3'010 10'0010100000
  transition:      3'010 10'-------10- ->      3'101 10'0101100000
  transition:      3'010 10'--------1- ->      3'000 10'0000100000
  transition:      3'110 10'---0----0- ->      3'110 10'0110001000
  transition:      3'110 10'---1----0- ->      3'000 10'0000001000
  transition:      3'110 10'--------1- ->      3'000 10'0000001000
  transition:      3'001 10'------0-0- ->      3'001 10'1001000000
  transition:      3'001 10'------1-0- ->      3'110 10'1110000000
  transition:      3'001 10'--------1- ->      3'000 10'1000000000
  transition:      3'101 10'-----0--0- ->      3'110 10'0110000100
  transition:      3'101 10'-----1--0- ->      3'101 10'0101000100
  transition:      3'101 10'--------1- ->      3'000 10'0000000100
  transition:      3'011 10'----0---0- ->      3'011 10'0011000010
  transition:      3'011 10'----1---0- ->      3'100 10'0100000010
  transition:      3'011 10'--------1- ->      3'000 10'0000000010

63.11.3. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\memctrl_I.state$21146' from module `\top'.
  Removing unused input signal $auto$opt_reduce.cc:134:opt_pmux$21136.
Optimizing FSM `$fsm$\cache_bus_I.state$21137' from module `\top'.
  Merging pattern 11'--0-------- and 11'--1-------- from group (2 0 10'0000000100).
  Merging pattern 11'--1-------- and 11'--0-------- from group (2 0 10'0000000100).
  Merging pattern 11'--0-------- and 11'--1-------- from group (3 0 10'0000100000).
  Merging pattern 11'--1-------- and 11'--0-------- from group (3 0 10'0000100000).
  Removing unused input signal $auto$opt_reduce.cc:134:opt_pmux$21106.

63.11.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 27 unused cells and 27 unused wires.
<suppressed ~29 debug messages>

63.11.5. Executing FSM_OPT pass (simple optimizations of FSMs).
Optimizing FSM `$fsm$\cache_bus_I.state$21137' from module `\top'.
Optimizing FSM `$fsm$\memctrl_I.state$21146' from module `\top'.
  Removing unused output signal $flatten\memctrl_I.$0\state[2:0] [0].
  Removing unused output signal $flatten\memctrl_I.$0\state[2:0] [1].
  Removing unused output signal $flatten\memctrl_I.$0\state[2:0] [2].

63.11.6. Executing FSM_RECODE pass (re-assigning FSM state encoding).
Recoding FSM `$fsm$\cache_bus_I.state$21137' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ------1
  100 -> -----1-
  010 -> ----1--
  110 -> ---1---
  001 -> --1----
  101 -> -1-----
  011 -> 1------
Recoding FSM `$fsm$\memctrl_I.state$21146' from module `\top' using `auto' encoding:
  mapping auto encoding to `one-hot` for this FSM.
  000 -> ------1
  100 -> -----1-
  010 -> ----1--
  110 -> ---1---
  001 -> --1----
  101 -> -1-----
  011 -> 1------

63.11.7. Executing FSM_INFO pass (dumping all available information on FSM cells).

FSM `$fsm$\cache_bus_I.state$21137' from module `top':
-------------------------------------

  Information on FSM $fsm$\cache_bus_I.state$21137 (\cache_bus_I.state):

  Number of input signals:   10
  Number of output signals:  10
  Number of state bits:       7

  Input signals:
    0: \cpu_I.IBusCachedPlugin_cache.lineLoader_address [30]
    1: \cpu_I.dBus_cmd_halfPipe_regs_payload_address [30]
    2: \cpu_I.dBus_cmd_halfPipe_regs_payload_address [31]
    3: \cpu_I.dBus_cmd_halfPipe_regs_valid
    4: \cache_bus_I.wb_ack_i
    5: \cache_bus_I.ib_addr_last
    6: \cache_bus_I.ctrl_is_cache
    7: \cache_bus_I.i_axi_ar_valid
    8: \cache_I.rst
    9: \cache_I.resp_ack

  Output signals:
    0: $flatten\cache_bus_I.$procmux$13219_CMP
    1: $flatten\cache_bus_I.$procmux$13167_CMP
    2: $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:278$3443_Y
    3: $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:264$3433_Y
    4: $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:230$3426_Y
    5: $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:227$3423_Y
    6: $flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:177$3396_Y
    7: $flatten\cache_bus_I.$0\state[2:0] [0]
    8: $flatten\cache_bus_I.$0\state[2:0] [1]
    9: $flatten\cache_bus_I.$0\state[2:0] [2]

  State encoding:
    0:  7'------1  <RESET STATE>
    1:  7'-----1-
    2:  7'----1--
    3:  7'---1---
    4:  7'--1----
    5:  7'-1-----
    6:  7'1------

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 10'-00---0---   ->     0 10'0001000000
      1:     0 10'-1--------   ->     0 10'0001000000
      2:     0 10'-01------1   ->     1 10'1001000000
      3:     0 10'-00---100-   ->     2 10'0101000000
      4:     0 10'-00---101-   ->     4 10'0011000000
      5:     0 10'-01------0   ->     5 10'1011000000
      6:     0 10'-00---11--   ->     6 10'0111000000
      7:     1 10'-1--------   ->     0 10'0000000001
      8:     1 10'00--------   ->     1 10'1000000001
      9:     1 10'10--------   ->     5 10'1010000001
     10:     2 10'----------   ->     0 10'0000000100
     11:     3 10'----------   ->     0 10'0000100000
     12:     4 10'10--------   ->     0 10'0000001000
     13:     4 10'-1--------   ->     0 10'0000001000
     14:     4 10'00--------   ->     4 10'0010001000
     15:     5 10'-0-01-----   ->     0 10'0000010000
     16:     5 10'-1--------   ->     0 10'0000010000
     17:     5 10'-0-11-----   ->     3 10'1100010000
     18:     5 10'-0--0-----   ->     5 10'1010010000
     19:     6 10'-0---1----   ->     0 10'0000000010
     20:     6 10'-1--------   ->     0 10'0000000010
     21:     6 10'-0---0----   ->     6 10'0110000010

-------------------------------------

FSM `$fsm$\memctrl_I.state$21146' from module `top':
-------------------------------------

  Information on FSM $fsm$\memctrl_I.state$21146 (\memctrl_I.state):

  Number of input signals:    9
  Number of output signals:   7
  Number of state bits:       7

  Input signals:
    0: \cache_I.rst
    1: $flatten\memctrl_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:484$3040_Y
    2: $flatten\memctrl_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:480$3039_Y
    3: \memctrl_I.so_valid
    4: \memctrl_I.so_ld_now
    5: \memctrl_I.pause_cnt [3]
    6: \memctrl_I.ectl_req
    7: \memctrl_I.mi_valid
    8: \memctrl_I.mi_rw

  Output signals:
    0: \cache_I.mi_ready
    1: $flatten\memctrl_I.$procmux$5669_CMP
    2: $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:765$3156_Y
    3: $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:516$3052_Y
    4: $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:509$3047_Y
    5: $flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:509$3046_Y
    6: \memctrl_I.ectl_grant

  State encoding:
    0:  7'------1  <RESET STATE>
    1:  7'-----1-
    2:  7'----1--
    3:  7'---1---
    4:  7'--1----
    5:  7'-1-----
    6:  7'1------

  Transition Table (state_in, ctrl_in, state_out, ctrl_out):
      0:     0 9'-00-----0   ->     0 7'0000001
      1:     0 9'--------1   ->     0 7'0000001
      2:     0 9'01------0   ->     2 7'0000001
      3:     0 9'-01-----0   ->     4 7'0000001
      4:     0 9'11------0   ->     6 7'0000001
      5:     1 9'--------1   ->     0 7'0010000
      6:     1 9'-------00   ->     1 7'0010000
      7:     1 9'-------10   ->     5 7'0010000
      8:     2 9'--------1   ->     0 7'0100000
      9:     2 9'-------00   ->     2 7'0100000
     10:     2 9'-------10   ->     5 7'0100000
     11:     3 9'---1----0   ->     0 7'0001000
     12:     3 9'--------1   ->     0 7'0001000
     13:     3 9'---0----0   ->     3 7'0001000
     14:     4 9'--------1   ->     0 7'1000000
     15:     4 9'------1-0   ->     3 7'1000000
     16:     4 9'------0-0   ->     4 7'1000000
     17:     5 9'--------1   ->     0 7'0000100
     18:     5 9'-----0--0   ->     3 7'0000100
     19:     5 9'-----1--0   ->     5 7'0000100
     20:     6 9'--------1   ->     0 7'0000010
     21:     6 9'----1---0   ->     1 7'0000010
     22:     6 9'----0---0   ->     6 7'0000010

-------------------------------------

63.11.8. Executing FSM_MAP pass (mapping FSMs to basic logic).
Mapping FSM `$fsm$\cache_bus_I.state$21137' from module `\top'.
Mapping FSM `$fsm$\memctrl_I.state$21146' from module `\top'.

63.12. Executing OPT pass (performing simple optimizations).

63.12.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~20 debug messages>

63.12.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~111 debug messages>
Removed a total of 37 cells.

63.12.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~366 debug messages>

63.12.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

63.12.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.12.6. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\vid_I.\tgen_I.$procdff$20597 ($adff) from module top (D = \vid_I.tgen_I.v_last, Q = \vid_I.tgen_I.v_first).
Adding EN signal on $flatten\vid_I.\tgen_I.$procdff$20596 ($adff) from module top (D = $flatten\vid_I.\tgen_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:145$3943_Y, Q = \vid_I.tgen_I.v_zone).
Adding SRST signal on $flatten\vid_I.$procdff$20888 ($dff) from module top (D = $flatten\vid_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:182$1627_Y, Q = \vid_I.vs_frame_cnt, rval = 16'0000000000000000).
Adding EN signal on $flatten\vid_I.$procdff$20887 ($dff) from module top (D = $flatten\vid_I.$procmux$7221_Y, Q = \vid_I.pp_yscale_state).
Adding SRST signal on $auto$ff.cc:266:slice$21375 ($dffe) from module top (D = $flatten\vid_I.$auto$proc_rom.cc:154:do_switch$4697 [3:0], Q = \vid_I.pp_yscale_state, rval = 4'0000).
Adding EN signal on $flatten\vid_I.$procdff$20886 ($dff) from module top (D = $flatten\vid_I.$procmux$7215_Y, Q = \vid_I.pp_ydbl_1).
Adding SRST signal on $auto$ff.cc:266:slice$21377 ($dffe) from module top (D = $flatten\vid_I.$auto$proc_rom.cc:154:do_switch$4697 [4], Q = \vid_I.pp_ydbl_1, rval = 1'0).
Adding EN signal on $flatten\vid_I.$procdff$20883 ($dff) from module top (D = $flatten\vid_I.$procmux$7209_Y, Q = \vid_I.pp_addr_base_1).
Adding SRST signal on $auto$ff.cc:266:slice$21379 ($dffe) from module top (D = $flatten\vid_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:236$1635_Y, Q = \vid_I.pp_addr_base_1, rval = 16'0000000000000000).
Adding EN signal on $flatten\vid_I.$procdff$20880 ($dff) from module top (D = $flatten\vid_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:255$1645_Y, Q = \vid_I.pp_data_3).
Adding SRST signal on $auto$ff.cc:266:slice$21381 ($dffe) from module top (D = \vid_I.fb_I.ram_rdata [31:24], Q = \vid_I.pp_data_3 [31:24], rval = 8'00000000).
Adding EN signal on $flatten\uart_I.\uart_tx_fifo_I.\ram_I.$procdff$20580 ($dff) from module top (D = $flatten\uart_I.\uart_tx_fifo_I.\ram_I.$memrd$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:43$4404_DATA, Q = \uart_I.uart_tx_fifo_I.ram_I.rd_data).
Adding EN signal on $flatten\uart_I.\uart_tx_fifo_I.$procdff$20586 ($adff) from module top (D = $flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:99$3975_Y [8:0], Q = \uart_I.uart_tx_fifo_I.ram_wr_addr).
Adding EN signal on $flatten\uart_I.\uart_tx_fifo_I.$procdff$20585 ($adff) from module top (D = $flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:112$3977_Y [8:0], Q = \uart_I.uart_tx_fifo_I.ram_rd_addr).
Adding EN signal on $flatten\uart_I.\uart_tx_fifo_I.$procdff$20584 ($adff) from module top (D = $flatten\uart_I.\uart_tx_fifo_I.$not$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:114$3980_Y, Q = \uart_I.uart_tx_fifo_I.rd_valid).
Adding SRST signal on $flatten\uart_I.\uart_tx_I.$procdff$20573 ($dff) from module top (D = $flatten\uart_I.\uart_tx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:46$4436_Y [12], Q = \uart_I.uart_tx_I.div_cnt [12], rval = 1'0).
Adding SRST signal on $flatten\uart_I.\uart_tx_I.$procdff$20572 ($dff) from module top (D = $flatten\uart_I.\uart_tx_I.$procmux$5030_Y, Q = \uart_I.uart_tx_I.bit_cnt, rval = 5'01000).
Adding EN signal on $auto$ff.cc:266:slice$21390 ($sdff) from module top (D = $flatten\uart_I.\uart_tx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:55$4439_Y [4:0], Q = \uart_I.uart_tx_I.bit_cnt).
Adding EN signal on $flatten\uart_I.\uart_tx_I.$procdff$20571 ($adff) from module top (D = $flatten\uart_I.\uart_tx_I.$0\shift[9:0], Q = \uart_I.uart_tx_I.shift).
Adding EN signal on $flatten\uart_I.\uart_rx_fifo_I.\ram_I.$procdff$20580 ($dff) from module top (D = $flatten\uart_I.\uart_rx_fifo_I.\ram_I.$memrd$\ram$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/ram_sdp.v:43$4404_DATA, Q = \uart_I.uart_rx_fifo_I.ram_I.rd_data).
Adding EN signal on $flatten\uart_I.\uart_rx_fifo_I.$procdff$20586 ($adff) from module top (D = $flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:99$3975_Y [8:0], Q = \uart_I.uart_rx_fifo_I.ram_wr_addr).
Adding EN signal on $flatten\uart_I.\uart_rx_fifo_I.$procdff$20585 ($adff) from module top (D = $flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:112$3977_Y [8:0], Q = \uart_I.uart_rx_fifo_I.ram_rd_addr).
Adding EN signal on $flatten\uart_I.\uart_rx_fifo_I.$procdff$20584 ($adff) from module top (D = $flatten\uart_I.\uart_rx_fifo_I.$not$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:114$3980_Y, Q = \uart_I.uart_rx_fifo_I.rd_valid).
Adding SRST signal on $flatten\uart_I.\uart_rx_I.\genblk1.gf_I.$procdff$20611 ($dff) from module top (D = $flatten\uart_I.\uart_rx_I.\genblk1.gf_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:74$3502_Y, Q = \uart_I.uart_rx_I.genblk1.gf_I.cnt, rval = 2'11).
Adding SRST signal on $flatten\uart_I.\uart_rx_I.\genblk1.gf_I.$procdff$20610 ($dff) from module top (D = $flatten\uart_I.\uart_rx_I.\genblk1.gf_I.$procmux$5112_Y, Q = \uart_I.uart_rx_I.genblk1.gf_I.state, rval = 1'1).
Adding EN signal on $auto$ff.cc:266:slice$21400 ($sdff) from module top (D = $flatten\uart_I.\uart_rx_I.\genblk1.gf_I.$procmux$5112_Y, Q = \uart_I.uart_rx_I.genblk1.gf_I.state).
Adding SRST signal on $flatten\uart_I.\uart_rx_I.$procdff$20577 ($dff) from module top (D = $flatten\uart_I.\uart_rx_I.$procmux$5040_Y, Q = \uart_I.uart_rx_I.bit_cnt, rval = 5'01000).
Adding EN signal on $auto$ff.cc:266:slice$21404 ($sdff) from module top (D = $flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:92$4421_Y [4:0], Q = \uart_I.uart_rx_I.bit_cnt).
Adding EN signal on $flatten\uart_I.\uart_rx_I.$procdff$20576 ($dff) from module top (D = { \uart_I.uart_rx_I.genblk1.gf_I.state \uart_I.uart_rx_I.shift [8:1] }, Q = \uart_I.uart_rx_I.shift).
Adding SRST signal on $flatten\uart_I.$procdff$20676 ($dff) from module top (D = $flatten\uart_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:174$2960_Y, Q = \uart_I.ub_wr_div, rval = 1'0).
Adding SRST signal on $flatten\uart_I.$procdff$20675 ($dff) from module top (D = $flatten\uart_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:173$2957_Y, Q = \uart_I.ub_wr_data, rval = 1'0).
Adding SRST signal on $flatten\uart_I.$procdff$20674 ($dff) from module top (D = $flatten\uart_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:172$2952_Y, Q = \uart_I.ub_rd_ctrl, rval = 1'0).
Adding SRST signal on $flatten\uart_I.$procdff$20673 ($dff) from module top (D = $flatten\uart_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:171$2948_Y, Q = \uart_I.ub_rd_data, rval = 1'0).
Adding SRST signal on $flatten\uart_I.$procdff$20672 ($dff) from module top (D = $flatten\uart_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:181$2967_Y, Q = \uart_I.ub_ack, rval = 1'0).
Adding SRST signal on $flatten\uart_I.$procdff$20671 ($dff) from module top (D = { \uart_I.urf_overflow \uart_I.utf_empty \uart_I.uart_tx_fifo_I.full \uart_I.uart_div [11:8] }, Q = { \uart_I.ub_rdata [30:28] \uart_I.ub_rdata [11:8] }, rval = 7'0000000).
Adding SRST signal on $flatten\uart_I.$procdff$20671 ($dff) from module top (D = { $flatten\uart_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:189$2972_Y [31] $flatten\uart_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:189$2972_Y [27:12] $flatten\uart_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:189$2972_Y [7:0] }, Q = { \uart_I.ub_rdata [31] \uart_I.ub_rdata [27:12] \uart_I.ub_rdata [7:0] }, rval = 25'0000000000000000000000000).
Adding EN signal on $flatten\uart_I.$procdff$20670 ($dff) from module top (D = \cpu_I.dBus_cmd_halfPipe_regs_payload_data [11:0], Q = \uart_I.uart_div).
Adding EN signal on $flatten\rgb_I.$procdff$20678 ($adff) from module top (D = \cpu_I.dBus_cmd_halfPipe_regs_payload_data [4:0], Q = \rgb_I.led_ctrl).
Adding EN signal on $flatten\memctrl_I.\genblk1.rsp_fifo_I.$procdff$20606 ($adff) from module top (D = \memctrl_I.si_data_n, Q = \memctrl_I.genblk1.rsp_fifo_I.stage[1].l_data).
Adding EN signal on $flatten\memctrl_I.\genblk1.rsp_fifo_I.$procdff$20605 ($adff) from module top (D = $flatten\memctrl_I.\genblk1.rsp_fifo_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:68$3875_Y, Q = \memctrl_I.genblk1.rsp_fifo_I.stage[1].l_valid).
Adding EN signal on $flatten\memctrl_I.\genblk1.cmd_fifo_I.$procdff$20604 ($adff) from module top (D = { \cpu_I.dBus_cmd_halfPipe_regs_payload_address [5:2] \cpu_I.dBus_cmd_halfPipe_regs_payload_data }, Q = \memctrl_I.genblk1.cmd_fifo_I.stage[1].l_data).
Adding EN signal on $flatten\memctrl_I.\genblk1.cmd_fifo_I.$procdff$20603 ($adff) from module top (D = $flatten\memctrl_I.\genblk1.cmd_fifo_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:68$3888_Y, Q = \memctrl_I.genblk1.cmd_fifo_I.stage[1].l_valid).
Adding SRST signal on $flatten\memctrl_I.$procdff$20668 ($dff) from module top (D = $flatten\cache_bus_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:301$3453_Y, Q = \memctrl_I.wb_ack, rval = 1'0).
Adding SRST signal on $flatten\memctrl_I.$procdff$20667 ($dff) from module top (D = $flatten\memctrl_I.$procmux$5809_Y, Q = \memctrl_I.ectl_req, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$21427 ($sdff) from module top (D = $flatten\memctrl_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:335$3004_Y, Q = \memctrl_I.ectl_req).
Adding EN signal on $flatten\memctrl_I.$procdff$20666 ($dff) from module top (D = \cpu_I.dBus_cmd_halfPipe_regs_payload_data [5:4], Q = \memctrl_I.ectl_cs).
Adding SRST signal on $flatten\memctrl_I.$procdff$20662 ($dff) from module top (D = { \memctrl_I.genblk1.rsp_fifo_I.stage[1].l_data [31:16] \memctrl_I.genblk1.rsp_fifo_I.stage[1].l_data [12] \memctrl_I.genblk1.rsp_fifo_I.stage[1].l_data [9:6] \memctrl_I.genblk1.rsp_fifo_I.stage[1].l_data [3] }, Q = { \memctrl_I.wb_rdata [31:16] \memctrl_I.wb_rdata [12] \memctrl_I.wb_rdata [9:6] \memctrl_I.wb_rdata [3] }, rval = 22'0000000000000000000000).
Adding SRST signal on $flatten\memctrl_I.$procdff$20662 ($dff) from module top (D = { $flatten\memctrl_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:377$3026_Y [15:13] $flatten\memctrl_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:377$3026_Y [11:10] $flatten\memctrl_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:377$3026_Y [5:4] $flatten\memctrl_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:377$3026_Y [2:0] }, Q = { \memctrl_I.wb_rdata [15:13] \memctrl_I.wb_rdata [11:10] \memctrl_I.wb_rdata [5:4] \memctrl_I.wb_rdata [2:0] }, rval = 10'0000000000).
Adding SRST signal on $flatten\memctrl_I.$procdff$20659 ($dff) from module top (D = $flatten\memctrl_I.$procmux$5709_Y, Q = \memctrl_I.xfer_cnt, rval = 8'00000110).
Adding EN signal on $auto$ff.cc:266:slice$21436 ($sdff) from module top (D = $flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:510$3050_Y [7:0], Q = \memctrl_I.xfer_cnt).
Adding SRST signal on $flatten\memctrl_I.$procdff$20658 ($dff) from module top (D = $flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:517$3053_Y [3:0], Q = \memctrl_I.pause_cnt, rval = 4'0110).
Adding SRST signal on $flatten\memctrl_I.$procdff$20657 ($dff) from module top (D = $flatten\memctrl_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:681$3081_Y, Q = \memctrl_I.so_valid, rval = 1'0).
Adding EN signal on $flatten\memctrl_I.$procdff$20656 ($dff) from module top (D = \memctrl_I.so_ld_dst, Q = \memctrl_I.so_dst).
Adding EN signal on $flatten\memctrl_I.$procdff$20655 ($dff) from module top (D = \memctrl_I.so_ld_mode, Q = \memctrl_I.so_mode).
Adding SRST signal on $flatten\memctrl_I.$procdff$20644 ($dff) from module top (D = $flatten\memctrl_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:765$3157_Y, Q = \memctrl_I.si_dst_1, rval = 2'00).
Adding SRST signal on $flatten\memctrl_I.$procdff$20629 ($dff) from module top (D = $flatten\memctrl_I.$2$lookahead\phy_cs_o$3180[1:0]$3190, Q = \memctrl_I.phy_cs_o, rval = 2'11).
Adding EN signal on $auto$ff.cc:266:slice$21443 ($sdff) from module top (D = $flatten\memctrl_I.$2$lookahead\phy_cs_o$3180[1:0]$3190, Q = \memctrl_I.phy_cs_o).
Adding EN signal on $flatten\cpu_I.\IBusCachedPlugin_cache.$procdff$20875 ($dff) from module top (D = $flatten\cpu_I.\IBusCachedPlugin_cache.$memrd$\ways_0_tags$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:163$1733_DATA, Q = \cpu_I.IBusCachedPlugin_cache._zz_10_).
Adding EN signal on $flatten\cpu_I.\IBusCachedPlugin_cache.$procdff$20871 ($dff) from module top (D = $flatten\cpu_I.\IBusCachedPlugin_cache.$memrd$\ways_0_datas$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:175$1742_DATA, Q = \cpu_I.IBusCachedPlugin_cache._zz_11_).
Adding EN signal on $flatten\cpu_I.\IBusCachedPlugin_cache.$procdff$20870 ($adff) from module top (D = $flatten\cpu_I.\IBusCachedPlugin_cache.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:294$1775_Y, Q = \cpu_I.IBusCachedPlugin_cache.lineLoader_wordIndex).
Adding EN signal on $flatten\cpu_I.\IBusCachedPlugin_cache.$procdff$20869 ($adff) from module top (D = $flatten\cpu_I.\IBusCachedPlugin_cache.$0\lineLoader_cmdSent[0:0], Q = \cpu_I.IBusCachedPlugin_cache.lineLoader_cmdSent).
Adding EN signal on $flatten\cpu_I.\IBusCachedPlugin_cache.$procdff$20868 ($adff) from module top (D = $flatten\cpu_I.\IBusCachedPlugin_cache.$0\lineLoader_flushPending[0:0], Q = \cpu_I.IBusCachedPlugin_cache.lineLoader_flushPending).
Adding EN signal on $flatten\cpu_I.\IBusCachedPlugin_cache.$procdff$20867 ($adff) from module top (D = 1'0, Q = \cpu_I.IBusCachedPlugin_cache.lineLoader_hadError).
Adding EN signal on $flatten\cpu_I.\IBusCachedPlugin_cache.$procdff$20866 ($adff) from module top (D = $flatten\cpu_I.\IBusCachedPlugin_cache.$0\lineLoader_valid[0:0], Q = \cpu_I.IBusCachedPlugin_cache.lineLoader_valid).
Adding EN signal on $flatten\cpu_I.\IBusCachedPlugin_cache.$procdff$20864 ($dff) from module top (D = \cpu_I.IBusCachedPlugin_cache.fetchStage_hit_hits_0, Q = \cpu_I.IBusCachedPlugin_cache.decodeStage_hit_valid).
Adding EN signal on $flatten\cpu_I.\IBusCachedPlugin_cache.$procdff$20863 ($dff) from module top (D = 1'0, Q = \cpu_I.IBusCachedPlugin_cache.decodeStage_mmuRsp_refilling).
Adding EN signal on $flatten\cpu_I.\IBusCachedPlugin_cache.$procdff$20857 ($dff) from module top (D = \cpu_I.IBusCachedPlugin_fetchPc_pcReg, Q = \cpu_I.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress).
Adding EN signal on $flatten\cpu_I.\IBusCachedPlugin_cache.$procdff$20856 ($dff) from module top (D = \cpu_I.IBusCachedPlugin_cache._zz_11_, Q = \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen).
Adding SRST signal on $flatten\cpu_I.\IBusCachedPlugin_cache.$procdff$20854 ($dff) from module top (D = $flatten\cpu_I.\IBusCachedPlugin_cache.$procmux$7125_Y, Q = \cpu_I.IBusCachedPlugin_cache.lineLoader_flushCounter, rval = 7'0000000).
Adding EN signal on $auto$ff.cc:266:slice$21468 ($sdff) from module top (D = $flatten\cpu_I.\IBusCachedPlugin_cache.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:307$1777_Y [5:0], Q = \cpu_I.IBusCachedPlugin_cache.lineLoader_flushCounter [5:0]).
Adding EN signal on $flatten\cpu_I.\IBusCachedPlugin_cache.$procdff$20853 ($dff) from module top (D = \cpu_I.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress, Q = \cpu_I.IBusCachedPlugin_cache.lineLoader_address).
Adding EN signal on $flatten\cpu_I.$procdff$20843 ($adff) from module top (D = \cpu_I.execute_CsrPlugin_writeData, Q = \cpu_I._zz_146_).
Adding EN signal on $flatten\cpu_I.$procdff$20839 ($adff) from module top (D = $flatten\cpu_I.$0\CsrPlugin_pipelineLiberator_pcValids_2[0:0], Q = \cpu_I.CsrPlugin_pipelineLiberator_pcValids_2).
Adding EN signal on $flatten\cpu_I.$procdff$20838 ($adff) from module top (D = $flatten\cpu_I.$0\CsrPlugin_pipelineLiberator_pcValids_1[0:0], Q = \cpu_I.CsrPlugin_pipelineLiberator_pcValids_1).
Adding EN signal on $flatten\cpu_I.$procdff$20837 ($adff) from module top (D = $flatten\cpu_I.$0\CsrPlugin_pipelineLiberator_pcValids_0[0:0], Q = \cpu_I.CsrPlugin_pipelineLiberator_pcValids_0).
Adding EN signal on $flatten\cpu_I.$procdff$20832 ($adff) from module top (D = \cpu_I.execute_CsrPlugin_writeData [3], Q = \cpu_I.CsrPlugin_mie_MSIE).
Adding EN signal on $flatten\cpu_I.$procdff$20831 ($adff) from module top (D = \cpu_I.execute_CsrPlugin_writeData [7], Q = \cpu_I.CsrPlugin_mie_MTIE).
Adding EN signal on $flatten\cpu_I.$procdff$20830 ($adff) from module top (D = \cpu_I.execute_CsrPlugin_writeData [11], Q = \cpu_I.CsrPlugin_mie_MEIE).
Adding EN signal on $flatten\cpu_I.$procdff$20824 ($adff) from module top (D = \cpu_I.execute_CsrPlugin_writeData [2], Q = \cpu_I.RegFilePlugin_shadow_clear).
Adding EN signal on $flatten\cpu_I.$procdff$20815 ($adff) from module top (D = $flatten\cpu_I.$0\_zz_67_[0:0], Q = \cpu_I._zz_67_).
Adding EN signal on $flatten\cpu_I.$procdff$20814 ($adff) from module top (D = $flatten\cpu_I.$0\_zz_65_[0:0], Q = \cpu_I._zz_65_).
Adding EN signal on $flatten\cpu_I.$procdff$20813 ($adff) from module top (D = $flatten\cpu_I.$0\IBusCachedPlugin_fetchPc_inc[0:0], Q = \cpu_I.IBusCachedPlugin_fetchPc_inc).
Adding EN signal on $flatten\cpu_I.$procdff$20810 ($adff) from module top (D = { \cpu_I.IBusCachedPlugin_fetchPc_pc [31:11] \cpu_I.IBusCachedPlugin_cache._zz_5_ \cpu_I.IBusCachedPlugin_cache._zz_8_ [2:0] 2'00 }, Q = \cpu_I.IBusCachedPlugin_fetchPc_pcReg).
Adding EN signal on $flatten\cpu_I.$procdff$20808 ($adff) from module top (D = $flatten\cpu_I.$0\memory_arbitration_isValid[0:0], Q = \cpu_I.memory_arbitration_isValid).
Adding EN signal on $flatten\cpu_I.$procdff$20807 ($adff) from module top (D = $flatten\cpu_I.$0\execute_arbitration_isValid[0:0], Q = \cpu_I.execute_arbitration_isValid).
Adding EN signal on $flatten\cpu_I.$procdff$20806 ($dff) from module top (D = \cpu_I.decode_to_execute_INSTRUCTION [13:12], Q = \cpu_I.dBus_cmd_halfPipe_regs_payload_size).
Adding EN signal on $flatten\cpu_I.$procdff$20805 ($dff) from module top (D = \cpu_I._zz_82_, Q = \cpu_I.dBus_cmd_halfPipe_regs_payload_data).
Adding EN signal on $flatten\cpu_I.$procdff$20804 ($dff) from module top (D = \cpu_I.execute_SrcPlugin_addSub, Q = \cpu_I.dBus_cmd_halfPipe_regs_payload_address).
Adding EN signal on $flatten\cpu_I.$procdff$20803 ($dff) from module top (D = \cpu_I.decode_to_execute_MEMORY_STORE, Q = \cpu_I.dBus_cmd_halfPipe_regs_payload_wr).
Adding EN signal on $flatten\cpu_I.$procdff$20801 ($dff) from module top (D = $flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4874$2547_Y, Q = \cpu_I.execute_CsrPlugin_csr_3008).
Adding EN signal on $flatten\cpu_I.$procdff$20800 ($dff) from module top (D = $flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4871$2545_Y, Q = \cpu_I.execute_CsrPlugin_csr_835).
Adding EN signal on $flatten\cpu_I.$procdff$20799 ($dff) from module top (D = $flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4868$2543_Y, Q = \cpu_I.execute_CsrPlugin_csr_834).
Adding EN signal on $flatten\cpu_I.$procdff$20798 ($dff) from module top (D = $flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4865$2541_Y, Q = \cpu_I.execute_CsrPlugin_csr_833).
Adding EN signal on $flatten\cpu_I.$procdff$20797 ($dff) from module top (D = $flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4862$2539_Y, Q = \cpu_I.execute_CsrPlugin_csr_773).
Adding EN signal on $flatten\cpu_I.$procdff$20796 ($dff) from module top (D = $flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4859$2537_Y, Q = \cpu_I.execute_CsrPlugin_csr_772).
Adding EN signal on $flatten\cpu_I.$procdff$20795 ($dff) from module top (D = $flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4856$2535_Y, Q = \cpu_I.execute_CsrPlugin_csr_836).
Adding EN signal on $flatten\cpu_I.$procdff$20794 ($dff) from module top (D = $flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4853$2533_Y, Q = \cpu_I.execute_CsrPlugin_csr_768).
Adding EN signal on $flatten\cpu_I.$procdff$20793 ($dff) from module top (D = $flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4850$2531_Y, Q = \cpu_I.execute_CsrPlugin_csr_1984).
Adding EN signal on $flatten\cpu_I.$procdff$20791 ($dff) from module top (D = \cpu_I.execute_MUL_LH, Q = \cpu_I.execute_to_memory_MUL_LH).
Adding EN signal on $flatten\cpu_I.$procdff$20790 ($dff) from module top (D = \cpu_I._zz_1_, Q = \cpu_I.decode_to_execute_SRC2_CTRL).
Adding EN signal on $flatten\cpu_I.$procdff$20789 ($dff) from module top (D = \cpu_I._zz_198_, Q = \cpu_I.decode_to_execute_IS_RS2_SIGNED).
Adding EN signal on $flatten\cpu_I.$procdff$20788 ($dff) from module top (D = \cpu_I._zz_198_, Q = \cpu_I.decode_to_execute_IS_RS1_SIGNED).
Adding EN signal on $flatten\cpu_I.$procdff$20786 ($dff) from module top (D = \cpu_I.execute_SrcPlugin_addSub [1:0], Q = \cpu_I.execute_to_memory_MEMORY_ADDRESS_LOW).
Adding EN signal on $flatten\cpu_I.$procdff$20785 ($dff) from module top (D = { \cpu_I._zz_302_ [24] \cpu_I._zz_313_ }, Q = \cpu_I.decode_to_execute_SRC1_CTRL).
Adding EN signal on $flatten\cpu_I.$procdff$20784 ($dff) from module top (D = \cpu_I.decode_RS2, Q = \cpu_I.decode_to_execute_RS2).
Adding EN signal on $flatten\cpu_I.$procdff$20783 ($dff) from module top (D = 1'0, Q = \cpu_I.execute_to_memory_MMU_FAULT).
Adding EN signal on $flatten\cpu_I.$procdff$20782 ($dff) from module top (D = \cpu_I.execute_BRANCH_DO, Q = \cpu_I.execute_to_memory_BRANCH_DO).
Adding EN signal on $flatten\cpu_I.$procdff$20780 ($dff) from module top (D = \cpu_I._zz_209_, Q = \cpu_I.decode_to_execute_BYPASSABLE_EXECUTE_STAGE).
Adding EN signal on $flatten\cpu_I.$procdff$20778 ($dff) from module top (D = \cpu_I.decode_to_execute_ENV_CTRL, Q = \cpu_I.execute_to_memory_ENV_CTRL).
Adding EN signal on $flatten\cpu_I.$procdff$20777 ($dff) from module top (D = { \cpu_I._zz_389_ \cpu_I._zz_391_ }, Q = \cpu_I.decode_to_execute_ENV_CTRL).
Adding EN signal on $flatten\cpu_I.$procdff$20776 ($dff) from module top (D = { \cpu_I.execute_BranchPlugin_branchAdder [31:1] 1'0 }, Q = \cpu_I.execute_to_memory_BRANCH_CALC).
Adding EN signal on $flatten\cpu_I.$procdff$20775 ($dff) from module top (D = \cpu_I._zz_210_, Q = \cpu_I.decode_to_execute_IS_CSR).
Adding EN signal on $flatten\cpu_I.$procdff$20774 ($dff) from module top (D = \cpu_I._zz_31_, Q = \cpu_I.execute_to_memory_REGFILE_WRITE_DATA).
Adding EN signal on $flatten\cpu_I.$procdff$20773 ($dff) from module top (D = \cpu_I.decode_to_execute_BYPASSABLE_MEMORY_STAGE, Q = \cpu_I.execute_to_memory_BYPASSABLE_MEMORY_STAGE).
Adding EN signal on $flatten\cpu_I.$procdff$20772 ($dff) from module top (D = \cpu_I._zz_211_, Q = \cpu_I.decode_to_execute_BYPASSABLE_MEMORY_STAGE).
Adding EN signal on $flatten\cpu_I.$procdff$20771 ($dff) from module top (D = { \cpu_I._zz_408_ \cpu_I._zz_372_ }, Q = \cpu_I.decode_to_execute_ALU_CTRL).
Adding EN signal on $flatten\cpu_I.$procdff$20770 ($dff) from module top (D = \cpu_I._zz_212_, Q = \cpu_I.decode_to_execute_SRC_LESS_UNSIGNED).
Adding EN signal on $flatten\cpu_I.$procdff$20769 ($dff) from module top (D = \cpu_I.decode_CSR_WRITE_OPCODE, Q = \cpu_I.decode_to_execute_CSR_WRITE_OPCODE).
Adding EN signal on $flatten\cpu_I.$procdff$20768 ($dff) from module top (D = \cpu_I.execute_to_memory_PC, Q = \cpu_I.memory_to_writeBack_PC).
Adding EN signal on $flatten\cpu_I.$procdff$20767 ($dff) from module top (D = \cpu_I.decode_to_execute_PC, Q = \cpu_I.execute_to_memory_PC).
Adding EN signal on $flatten\cpu_I.$procdff$20766 ($dff) from module top (D = \cpu_I._zz_68_, Q = \cpu_I.decode_to_execute_PC).
Adding EN signal on $flatten\cpu_I.$procdff$20764 ($dff) from module top (D = \cpu_I.decode_to_execute_REGFILE_WRITE_VALID, Q = \cpu_I.execute_to_memory_REGFILE_WRITE_VALID).
Adding EN signal on $flatten\cpu_I.$procdff$20763 ($dff) from module top (D = \cpu_I.decode_REGFILE_WRITE_VALID, Q = \cpu_I.decode_to_execute_REGFILE_WRITE_VALID).
Adding SRST signal on $auto$ff.cc:266:slice$21557 ($dffe) from module top (D = \cpu_I._zz_223_, Q = \cpu_I.decode_to_execute_REGFILE_WRITE_VALID, rval = 1'0).
Adding EN signal on $flatten\cpu_I.$procdff$20762 ($dff) from module top (D = \cpu_I.execute_MUL_HL, Q = \cpu_I.execute_to_memory_MUL_HL).
Adding EN signal on $flatten\cpu_I.$procdff$20761 ($dff) from module top (D = \cpu_I.decode_to_execute_IS_DIV, Q = \cpu_I.execute_to_memory_IS_DIV).
Adding EN signal on $flatten\cpu_I.$procdff$20760 ($dff) from module top (D = \cpu_I._zz_213_, Q = \cpu_I.decode_to_execute_IS_DIV).
Adding EN signal on $flatten\cpu_I.$procdff$20759 ($dff) from module top (D = { \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [12] \cpu_I._zz_407_ }, Q = \cpu_I.decode_to_execute_ALU_BITWISE_CTRL).
Adding EN signal on $flatten\cpu_I.$procdff$20758 ($dff) from module top (D = \cpu_I.decode_to_execute_SHIFT_CTRL, Q = \cpu_I.execute_to_memory_SHIFT_CTRL).
Adding EN signal on $flatten\cpu_I.$procdff$20757 ($dff) from module top (D = { \cpu_I._zz_415_ \cpu_I._zz_416_ }, Q = \cpu_I.decode_to_execute_SHIFT_CTRL).
Adding EN signal on $flatten\cpu_I.$procdff$20753 ($dff) from module top (D = \cpu_I._zz_214_ [31:0], Q = \cpu_I.execute_to_memory_SHIFT_RIGHT).
Adding EN signal on $flatten\cpu_I.$procdff$20752 ($dff) from module top (D = \cpu_I.decode_to_execute_INSTRUCTION, Q = \cpu_I.execute_to_memory_INSTRUCTION).
Adding EN signal on $flatten\cpu_I.$procdff$20751 ($dff) from module top (D = \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen, Q = \cpu_I.decode_to_execute_INSTRUCTION).
Adding EN signal on $flatten\cpu_I.$procdff$20750 ($dff) from module top (D = { \cpu_I.decode_BRANCH_CTRL [1] \cpu_I._zz_300_ }, Q = \cpu_I.decode_to_execute_BRANCH_CTRL).
Adding EN signal on $flatten\cpu_I.$procdff$20749 ($dff) from module top (D = \cpu_I.decode_SRC_USE_SUB_LESS, Q = \cpu_I.decode_to_execute_SRC_USE_SUB_LESS).
Adding EN signal on $flatten\cpu_I.$procdff$20748 ($dff) from module top (D = 1'0, Q = \cpu_I.execute_to_memory_MMU_RSP_refilling).
Adding EN signal on $flatten\cpu_I.$procdff$20741 ($dff) from module top (D = \cpu_I.execute_MUL_LL, Q = \cpu_I.execute_to_memory_MUL_LL).
Adding EN signal on $flatten\cpu_I.$procdff$20740 ($dff) from module top (D = \cpu_I.decode_SRC2_FORCE_ZERO, Q = \cpu_I.decode_to_execute_SRC2_FORCE_ZERO).
Adding EN signal on $flatten\cpu_I.$procdff$20737 ($dff) from module top (D = \cpu_I.decode_to_execute_IS_MUL, Q = \cpu_I.execute_to_memory_IS_MUL).
Adding EN signal on $flatten\cpu_I.$procdff$20736 ($dff) from module top (D = \cpu_I._zz_217_, Q = \cpu_I.decode_to_execute_IS_MUL).
Adding EN signal on $flatten\cpu_I.$procdff$20734 ($dff) from module top (D = \cpu_I.decode_to_execute_MEMORY_ENABLE, Q = \cpu_I.execute_to_memory_MEMORY_ENABLE).
Adding EN signal on $flatten\cpu_I.$procdff$20733 ($dff) from module top (D = \cpu_I._zz_224_, Q = \cpu_I.decode_to_execute_MEMORY_ENABLE).
Adding EN signal on $flatten\cpu_I.$procdff$20731 ($dff) from module top (D = \cpu_I.decode_to_execute_MEMORY_STORE, Q = \cpu_I.execute_to_memory_MEMORY_STORE).
Adding EN signal on $flatten\cpu_I.$procdff$20730 ($dff) from module top (D = \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [5], Q = \cpu_I.decode_to_execute_MEMORY_STORE).
Adding EN signal on $flatten\cpu_I.$procdff$20729 ($dff) from module top (D = \cpu_I.IBusCachedPlugin_decodePrediction_cmd_hadBranch, Q = \cpu_I.decode_to_execute_PREDICTION_HAD_BRANCHED2).
Adding EN signal on $flatten\cpu_I.$procdff$20728 ($dff) from module top (D = \cpu_I.decode_RS1, Q = \cpu_I.decode_to_execute_RS1).
Adding EN signal on $flatten\cpu_I.$procdff$20726 ($dff) from module top (D = \cpu_I.execute_MUL_HH, Q = \cpu_I.execute_to_memory_MUL_HH).
Adding EN signal on $flatten\cpu_I.$procdff$20724 ($dff) from module top (D = \cpu_I._zz_269_ [31:0], Q = \cpu_I.memory_DivPlugin_div_result).
Adding SRST signal on $flatten\cpu_I.$procdff$20723 ($dff) from module top (D = $flatten\cpu_I.$procmux$6062_Y, Q = \cpu_I.memory_DivPlugin_div_done, rval = 1'0).
Adding EN signal on $auto$ff.cc:266:slice$21587 ($sdff) from module top (D = 1'1, Q = \cpu_I.memory_DivPlugin_div_done).
Adding EN signal on $flatten\cpu_I.$procdff$20722 ($dff) from module top (D = $flatten\cpu_I.$logic_and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4657$2466_Y, Q = \cpu_I.memory_DivPlugin_div_needRevert).
Adding SRST signal on $flatten\cpu_I.$procdff$20721 ($dff) from module top (D = $flatten\cpu_I.$procmux$5888_Y, Q = \cpu_I.memory_DivPlugin_accumulator [31:0], rval = 0).
Adding EN signal on $flatten\cpu_I.$procdff$20721 ($dff) from module top (D = 33'000000000000000000000000000000000, Q = \cpu_I.memory_DivPlugin_accumulator [64:32]).
Adding EN signal on $auto$ff.cc:266:slice$21590 ($sdff) from module top (D = \cpu_I.memory_DivPlugin_div_stage_0_outRemainder, Q = \cpu_I.memory_DivPlugin_accumulator [31:0]).
Adding EN signal on $flatten\cpu_I.$procdff$20720 ($dff) from module top (D = $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4656$2457_Y, Q = \cpu_I.memory_DivPlugin_rs2).
Adding EN signal on $flatten\cpu_I.$procdff$20719 ($dff) from module top (D = $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4655$2454_Y [32], Q = \cpu_I.memory_DivPlugin_rs1 [32]).
Adding EN signal on $flatten\cpu_I.$procdff$20719 ($dff) from module top (D = $flatten\cpu_I.$0\memory_DivPlugin_rs1[32:0] [31:0], Q = \cpu_I.memory_DivPlugin_rs1 [31:0]).
Adding EN signal on $flatten\cpu_I.$procdff$20718 ($dff) from module top (D = 2'11, Q = \cpu_I.CsrPlugin_interrupt_targetPrivilege).
Adding EN signal on $flatten\cpu_I.$procdff$20717 ($dff) from module top (D = 4'0011, Q = \cpu_I.CsrPlugin_interrupt_code).
Adding EN signal on $flatten\cpu_I.$procdff$20716 ($dff) from module top (D = $flatten\cpu_I.$0\CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr[31:0], Q = \cpu_I.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr).
Adding EN signal on $flatten\cpu_I.$procdff$20715 ($dff) from module top (D = $flatten\cpu_I.$0\CsrPlugin_exceptionPortCtrl_exceptionContext_code[3:0], Q = \cpu_I.CsrPlugin_exceptionPortCtrl_exceptionContext_code).
Adding EN signal on $flatten\cpu_I.$procdff$20712 ($dff) from module top (D = \cpu_I.CsrPlugin_exceptionPortCtrl_exceptionContext_badAddr, Q = \cpu_I.CsrPlugin_mtval).
Adding EN signal on $flatten\cpu_I.$procdff$20711 ($dff) from module top (D = \cpu_I.CsrPlugin_trapCause, Q = \cpu_I.CsrPlugin_mcause_exceptionCode).
Adding EN signal on $flatten\cpu_I.$procdff$20710 ($dff) from module top (D = $flatten\cpu_I.$logic_not$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4627$2448_Y, Q = \cpu_I.CsrPlugin_mcause_interrupt).
Adding SRST signal on $flatten\cpu_I.$procdff$20709 ($dff) from module top (D = \cpu_I.execute_CsrPlugin_writeData [3], Q = \cpu_I.CsrPlugin_mip_MSIP, rval = 1'0).
Adding EN signal on $flatten\cpu_I.$procdff$20705 ($dff) from module top (D = \cpu_I.execute_CsrPlugin_writeData [31:2], Q = \cpu_I.CsrPlugin_mtvec_base).
Adding EN signal on $flatten\cpu_I.$procdff$20701 ($dff) from module top (D = \cpu_I.IBusCachedPlugin_s1_tightlyCoupledHit, Q = \cpu_I.IBusCachedPlugin_s2_tightlyCoupledHit).
Adding EN signal on $flatten\cpu_I.$procdff$20700 ($dff) from module top (D = 1'0, Q = \cpu_I.IBusCachedPlugin_s1_tightlyCoupledHit).
Adding EN signal on $flatten\cpu_I.$procdff$20699 ($dff) from module top (D = \cpu_I.IBusCachedPlugin_fetchPc_pcReg, Q = \cpu_I._zz_68_).
Adding EN signal on $flatten\cache_bus_I.$procdff$20905 ($dff) from module top (D = $flatten\cache_bus_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:182$3404_Y, Q = \cache_bus_I.ctrl_is_io).
Adding SRST signal on $auto$ff.cc:266:slice$21637 ($dffe) from module top (D = \cpu_I.dBus_cmd_halfPipe_regs_payload_address [31], Q = \cache_bus_I.ctrl_is_io, rval = 1'0).
Adding EN signal on $flatten\cache_bus_I.$procdff$20904 ($dff) from module top (D = $flatten\cache_bus_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:181$3403_Y, Q = \cache_bus_I.ctrl_is_ram).
Adding EN signal on $flatten\cache_bus_I.$procdff$20903 ($dff) from module top (D = $flatten\cache_bus_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:180$3400_Y, Q = \cache_bus_I.ctrl_is_cache).
Adding EN signal on $flatten\cache_bus_I.$procdff$20902 ($dff) from module top (D = $flatten\cache_bus_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:179$3398_Y, Q = \cache_bus_I.ctrl_is_dbus).
Adding EN signal on $flatten\cache_bus_I.$procdff$20901 ($dff) from module top (D = \cache_bus_I.i_axi_ar_valid, Q = \cache_bus_I.ctrl_is_ibus).
Adding SRST signal on $flatten\cache_bus_I.$procdff$20894 ($dff) from module top (D = { $flatten\cache_bus_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:301$3470_Y $flatten\cache_bus_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:301$3466_Y $flatten\cache_bus_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:301$3461_Y $flatten\cache_bus_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:301$3456_Y }, Q = \cache_bus_I.wb_cyc, rval = 4'0000).
Adding SRST signal on $flatten\cache_I.$procdff$20564 ($dff) from module top (D = $flatten\cache_I.$procmux$4989_Y, Q = \cache_I.cnt_ofs, rval = 3'000).
Adding EN signal on $auto$ff.cc:266:slice$21644 ($sdff) from module top (D = $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:224$4525_Y [2:0], Q = \cache_I.cnt_ofs).
Adding EN signal on $flatten\cache_I.$procdff$20563 ($dff) from module top (D = \cache_bus_I.addr_mux [23:0], Q = \cache_I.req_addr).
Adding EN signal on $flatten\cache_I.$procdff$20562 ($dff) from module top (D = \cache_I.ev_tag, Q = \cache_I.ev_tag_r).
Adding EN signal on $flatten\cache_I.$procdff$20561 ($dff) from module top (D = \cache_I.ev_valid, Q = \cache_I.ev_valid_r).
Adding EN signal on $flatten\cache_I.$procdff$20560 ($dff) from module top (D = \cache_I.ev_way, Q = \cache_I.ev_way_r).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$21635 ($dffe) from module top.
Setting constant 1-bit at position 0 on $auto$ff.cc:266:slice$21610 ($dffe) from module top.
Setting constant 1-bit at position 1 on $auto$ff.cc:266:slice$21610 ($dffe) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$21610 ($dffe) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$21610 ($dffe) from module top.
Setting constant 1-bit at position 0 on $auto$ff.cc:266:slice$21607 ($dffe) from module top.
Setting constant 1-bit at position 1 on $auto$ff.cc:266:slice$21607 ($dffe) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 3 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 4 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 5 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 6 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 7 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 24 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 25 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 26 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 27 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 28 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 29 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 30 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 31 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 32 on $auto$ff.cc:266:slice$21592 ($dffe) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$21570 ($dffe) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$21545 ($dffe) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$21540 ($dffe) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$21513 ($adffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$21513 ($adffe) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$21465 ($dffe) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$21460 ($adffe) from module top.

63.12.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 183 unused cells and 233 unused wires.
<suppressed ~185 debug messages>

63.12.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~51 debug messages>

63.12.9. Rerunning OPT passes. (Maybe there is more to do..)

63.12.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/2 on $mux $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3266$2158.
    dead port 2/2 on $mux $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3266$2158.
Removed 2 multiplexer ports.
<suppressed ~228 debug messages>

63.12.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_and cell $auto$opt_dff.cc:220:make_patterns_logic$21621: { \cpu_I._zz_176_ \cpu_I.CsrPlugin_hadException }
  Optimizing cells in module \top.
Performed a total of 1 changes.

63.12.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~27 debug messages>
Removed a total of 9 cells.

63.12.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$21622 ($dffe) from module top (D = \cpu_I.CsrPlugin_exceptionPortCtrl_exceptionContext_code, Q = \cpu_I.CsrPlugin_mcause_exceptionCode, rval = 4'0011).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$21466 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$21466 ($dffe) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$21634 ($dffe) from module top.

63.12.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 34 unused wires.
<suppressed ~3 debug messages>

63.12.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

63.12.16. Rerunning OPT passes. (Maybe there is more to do..)

63.12.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~228 debug messages>

63.12.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

63.12.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.12.20. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$21471 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$21471 ($dffe) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$21555 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$21555 ($dffe) from module top.

63.12.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

63.12.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.12.23. Rerunning OPT passes. (Maybe there is more to do..)

63.12.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~228 debug messages>

63.12.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

63.12.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.12.27. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$21554 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$21554 ($dffe) from module top.

63.12.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.12.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.12.30. Rerunning OPT passes. (Maybe there is more to do..)

63.12.31. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~228 debug messages>

63.12.32. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

63.12.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.12.34. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$21553 ($dffe) from module top.
Setting constant 0-bit at position 1 on $auto$ff.cc:266:slice$21553 ($dffe) from module top.

63.12.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.12.36. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.12.37. Rerunning OPT passes. (Maybe there is more to do..)

63.12.38. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~228 debug messages>

63.12.39. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

63.12.40. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.12.41. Executing OPT_DFF pass (perform DFF optimizations).

63.12.42. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.12.43. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.12.44. Finished OPT passes. (There is nothing left to do.)

63.13. Executing WREDUCE pass (reducing word size of cells).
Removed top 24 address bits (of 32) from memory init port top.$flatten\bram_I.$meminit$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:0$3387 (bram_I.mem).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4056 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4057 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4058 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4059 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4060 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4061 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4062 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4063 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4064 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4065 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4066 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4067 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4068 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4069 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4070 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\sys_mgr_I.\crg_I.$meminit$\rst_cnt_nxt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:47$4071 (sys_mgr_I.crg_I.rst_cnt_nxt).
Removed top 28 address bits (of 32) from memory init port top.$flatten\vid_I.$auto$mem.cc:328:emit$4700 ($flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698).
Removed top 1 bits (of 2) from port B of cell top.$auto$opt_dff.cc:195:make_patterns_logic$21604 ($ne).
Removed top 2 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$21168 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$21231 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\cpu_I.\IBusCachedPlugin_cache.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:294$1775 ($add).
Removed top 6 bits (of 7) from port B of cell top.$flatten\cpu_I.\IBusCachedPlugin_cache.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:307$1777 ($add).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$procmux$6952_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$procmux$6711_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$procmux$6701_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$procmux$6694_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$procmux$6690_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$procmux$6685_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$procmux$6681_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$procmux$6392_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$procmux$6324_CMP0 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4871$2545 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4868$2543 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4865$2541 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4862$2539 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4859$2537 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4856$2535 ($eq).
Removed top 2 bits (of 12) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4853$2533 ($eq).
Removed top 1 bits (of 12) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4850$2531 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4656$2457 ($add).
Removed top 32 bits (of 33) from port B of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4655$2454 ($add).
Removed top 1 bits (of 33) from port Y of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4655$2454 ($add).
Removed top 1 bits (of 33) from port A of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4655$2454 ($add).
Removed top 1 bits (of 33) from mux cell top.$flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4655$2453 ($mux).
Removed top 1 bits (of 33) from port Y of cell top.$flatten\cpu_I.$not$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4655$2452 ($not).
Removed top 1 bits (of 33) from port A of cell top.$flatten\cpu_I.$not$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4655$2452 ($not).
Removed top 20 bits (of 32) from port A of cell top.$flatten\cpu_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4253$2371 ($or).
Removed top 19 bits (of 32) from port A of cell top.$flatten\cpu_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4253$2370 ($or).
Removed top 28 bits (of 32) from port B of cell top.$flatten\cpu_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4253$2370 ($or).
Removed top 19 bits (of 32) from port Y of cell top.$flatten\cpu_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4253$2370 ($or).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$procmux$7090_CMP0 ($eq).
Removed top 1 bits (of 33) from port B of cell top.$flatten\cpu_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4130$2297 ($sub).
Removed top 5 bits (of 6) from port B of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4121$2296 ($add).
Removed top 14 bits (of 66) from port A of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4097$2290 ($add).
Removed top 2 bits (of 66) from port Y of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4097$2290 ($add).
Removed top 2 bits (of 66) from port B of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4097$2290 ($add).
Removed top 1 bits (of 2) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$21164 ($eq).
Removed top 12 bits (of 32) from mux cell top.$flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3814$2231 ($mux).
Removed top 2 bits (of 3) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3670$2215 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3567$2199 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3381$2171 ($eq).
Removed top 12 bits (of 32) from mux cell top.$flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3156$2121 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3062$2111 ($eq).
Removed top 29 bits (of 32) from port B of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2947$2077 ($add).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2751$2029 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2751$2027 ($eq).
Removed top 7 bits (of 32) from mux cell top.$flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2643$2004 ($mux).
Removed top 17 bits (of 34) from port A of cell top.$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996 ($mul).
Removed top 17 bits (of 34) from port B of cell top.$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996 ($mul).
Removed top 17 bits (of 34) from port A of cell top.$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990 ($mul).
Removed top 17 bits (of 34) from port B of cell top.$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990 ($mul).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2476$1982 ($eq).
Removed top 2 bits (of 52) from port B of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2461$1981 ($add).
Removed top 17 bits (of 34) from port A of cell top.$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978 ($mul).
Removed top 17 bits (of 34) from port B of cell top.$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978 ($mul).
Removed top 1 bits (of 3) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1686$1962 ($eq).
Removed top 3 bits (of 7) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1684$1959 ($eq).
Removed top 2 bits (of 6) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1683$1957 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1677$1951 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1676$1949 ($eq).
Removed top 1 bits (of 7) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1671$1939 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1660$1926 ($eq).
Removed top 2 bits (of 32) from FF cell top.$flatten\cpu_I.$procdff$20844 ($adff).
Removed top 3 bits (of 5) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1645$1917 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1640$1910 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1640$1909 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1639$1908 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1629$1899 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1615$1890 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1597$1880 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1589$1872 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1579$1865 ($eq).
Removed top 2 bits (of 32) from FF cell top.$auto$ff.cc:266:slice$21566 ($dffe).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1575$1862 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1567$1855 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1554$1847 ($eq).
Removed top 3 bits (of 7) from port A of cell top.$flatten\cpu_I.$sshl$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1543$1841 ($sshl).
Removed top 3 bits (of 7) from port Y of cell top.$flatten\cpu_I.$sshl$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1543$1841 ($sshl).
Removed top 1 bits (of 33) from port A of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1527$1840 ($add).
Removed top 32 bits (of 33) from port B of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1527$1840 ($add).
Removed top 1 bits (of 33) from port Y of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1527$1840 ($add).
Removed top 31 bits (of 32) from mux cell top.$flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1502$1835 ($mux).
Removed top 30 bits (of 32) from port B of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1498$1831 ($add).
Removed top 3 bits (of 4) from port B of cell top.$flatten\cpu_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1482$1830 ($sub).
Removed top 1 bits (of 33) from port Y of cell top.$flatten\cpu_I.$sshr$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1470$1827 ($sshr).
Removed top 19 bits (of 52) from port A of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1456$1823 ($add).
Removed top 2 bits (of 52) from port B of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1456$1823 ($add).
Removed top 1 bits (of 52) from port Y of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1456$1823 ($add).
Removed top 2 bits (of 34) from FF cell top.$flatten\cpu_I.$procdff$20727 ($dff).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cpu_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1433$1795 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$21348 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:301$3469 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:301$3464 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:301$3459 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:289$3447 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:269$3439 ($eq).
Removed top 2 bits (of 3) from port B of cell top.$flatten\cache_bus_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:224$3419 ($or).
Removed top 2 bits (of 3) from port Y of cell top.$flatten\cache_bus_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:224$3419 ($or).
Removed top 6 bits (of 30) from mux cell top.$flatten\cache_bus_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:214$3415 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:180$3399 ($eq).
Removed top 29 bits (of 32) from mux cell top.$flatten\cache_bus_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:156$3394 ($mux).
Removed top 29 bits (of 32) from mux cell top.$flatten\cache_bus_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:148$3393 ($mux).
Removed top 30 bits (of 32) from mux cell top.$flatten\cache_bus_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:148$3392 ($mux).
Removed top 31 bits (of 32) from mux cell top.$flatten\cache_bus_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:146$3391 ($mux).
Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$21326 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$21285 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$21277 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$21273 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$21260 ($eq).
Removed top 2 bits (of 5) from port B of cell top.$auto$fsm_map.cc:77:implement_pattern_cache$21256 ($eq).
Removed top 1 bits (of 2) from mux cell top.$flatten\cache_I.$procmux$4985 ($mux).
Removed top 1 bits (of 2) from mux cell top.$flatten\cache_I.$procmux$4976 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cache_I.$procmux$4704_CMP0 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4589 ($add).
Removed top 30 bits (of 32) from port Y of cell top.$flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4589 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4586 ($add).
Removed top 30 bits (of 32) from port Y of cell top.$flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4586 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4583 ($add).
Removed top 30 bits (of 32) from port Y of cell top.$flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4583 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4580 ($add).
Removed top 30 bits (of 32) from port Y of cell top.$flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4580 ($add).
Removed top 1 bits (of 2) from port A of cell top.$flatten\cache_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:385$4571 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:224$4525 ($add).
Removed top 29 bits (of 32) from port Y of cell top.$flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:224$4525 ($add).
Removed top 1 bits (of 2) from port B of cell top.$flatten\cache_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:208$4518 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\memctrl_I.$procmux$5655_CMP0 ($eq).
Removed top 3 bits (of 4) from port B of cell top.$flatten\memctrl_I.$procmux$5644_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\memctrl_I.$procmux$5643_CMP0 ($eq).
Removed top 2 bits (of 4) from port B of cell top.$flatten\memctrl_I.$procmux$5642_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\memctrl_I.$procmux$5641_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\memctrl_I.$procmux$5640_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\memctrl_I.$procmux$5639_CMP0 ($eq).
Removed top 1 bits (of 4) from port B of cell top.$flatten\memctrl_I.$procmux$5638_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\memctrl_I.$procmux$5549_CMP0 ($eq).
Removed top 1 bits (of 3) from port B of cell top.$flatten\memctrl_I.$procmux$5535_CMP0 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\memctrl_I.$procmux$5502_CMP0 ($eq).
Removed top 12 bits (of 16) from mux cell top.$flatten\memctrl_I.$procmux$5365 ($mux).
Converting cell top.$flatten\memctrl_I.$neg$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3203 ($neg) from signed to unsigned.
Removed top 1 bits (of 3) from port A of cell top.$flatten\memctrl_I.$neg$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3203 ($neg).
Converting cell top.$flatten\memctrl_I.$neg$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3194 ($neg) from signed to unsigned.
Removed top 1 bits (of 3) from port A of cell top.$flatten\memctrl_I.$neg$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3194 ($neg).
Removed top 30 bits (of 32) from port A of cell top.$flatten\memctrl_I.$ge$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3134 ($ge).
Removed top 30 bits (of 32) from port A of cell top.$flatten\memctrl_I.$ge$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3130 ($ge).
Removed top 31 bits (of 32) from port A of cell top.$flatten\memctrl_I.$ge$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3126 ($ge).
Removed top 31 bits (of 32) from port A of cell top.$flatten\memctrl_I.$ge$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3122 ($ge).
Removed top 30 bits (of 32) from port A of cell top.$flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3121 ($sub).
Removed top 29 bits (of 32) from port Y of cell top.$flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3121 ($sub).
Removed top 29 bits (of 32) from port B of cell top.$flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:695$3084 ($sub).
Removed top 26 bits (of 32) from port Y of cell top.$flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:695$3084 ($sub).
Removed top 26 bits (of 32) from port B of cell top.$flatten\memctrl_I.$shiftx$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3059 ($shiftx).
Removed top 26 bits (of 32) from port B of cell top.$flatten\memctrl_I.$shiftx$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3056 ($shiftx).
Removed top 31 bits (of 32) from port B of cell top.$flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:517$3053 ($sub).
Removed top 28 bits (of 32) from port Y of cell top.$flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:517$3053 ($sub).
Removed top 31 bits (of 32) from port B of cell top.$flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:510$3050 ($sub).
Removed top 24 bits (of 32) from port Y of cell top.$flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:510$3050 ($sub).
Removed top 1 bits (of 2) from port B of cell top.$flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:452$3034 ($eq).
Removed top 16 bits (of 32) from mux cell top.$flatten\memctrl_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:377$3026 ($mux).
Removed top 3 bits (of 5) from port B of cell top.$flatten\memctrl_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:324$2995 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\vid_I.\tgen_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:128$3937 ($sub).
Removed top 22 bits (of 32) from port Y of cell top.$flatten\vid_I.\tgen_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:128$3937 ($sub).
Removed top 1 bits (of 2) from port B of cell top.$flatten\vid_I.\tgen_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:189$3946 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\vid_I.\tgen_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:190$3947 ($eq).
Removed top 1 bits (of 2) from port B of cell top.$flatten\vid_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:323$1666 ($eq).
Removed top 8 bits (of 32) from mux cell top.$flatten\vid_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:255$1645 ($mux).
Removed top 7 bits (of 16) from mux cell top.$flatten\vid_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:236$1634 ($mux).
Removed top 15 bits (of 16) from port Y of cell top.$flatten\vid_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:182$1626 ($and).
Removed top 31 bits (of 32) from port B of cell top.$flatten\vid_I.\tgen_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:93$3931 ($sub).
Removed top 21 bits (of 32) from port Y of cell top.$flatten\vid_I.\tgen_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:93$3931 ($sub).
Removed top 1 bits (of 10) from port B of cell top.$flatten\uart_I.\uart_rx_fifo_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:81$3964 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:99$3975 ($add).
Removed top 23 bits (of 32) from port Y of cell top.$flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:99$3975 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:112$3977 ($add).
Removed top 23 bits (of 32) from port Y of cell top.$flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:112$3977 ($add).
Removed top 21 bits (of 32) from port A of cell top.$flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:79$4417 ($sub).
Removed top 31 bits (of 32) from port B of cell top.$flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:79$4417 ($sub).
Removed top 20 bits (of 32) from port Y of cell top.$flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:79$4417 ($sub).
Removed top 31 bits (of 32) from port B of cell top.$flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:83$4418 ($sub).
Removed top 19 bits (of 32) from port Y of cell top.$flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:83$4418 ($sub).
Removed top 31 bits (of 32) from port B of cell top.$flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:92$4421 ($sub).
Removed top 27 bits (of 32) from port Y of cell top.$flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:92$4421 ($sub).
Removed top 1 bits (of 10) from port B of cell top.$flatten\uart_I.\uart_tx_fifo_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:81$3964 ($eq).
Removed top 31 bits (of 32) from port B of cell top.$flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:99$3975 ($add).
Removed top 23 bits (of 32) from port Y of cell top.$flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:99$3975 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:112$3977 ($add).
Removed top 23 bits (of 32) from port Y of cell top.$flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:112$3977 ($add).
Removed top 31 bits (of 32) from port B of cell top.$flatten\uart_I.\uart_tx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:46$4436 ($sub).
Removed top 19 bits (of 32) from port Y of cell top.$flatten\uart_I.\uart_tx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:46$4436 ($sub).
Removed top 31 bits (of 32) from port B of cell top.$flatten\uart_I.\uart_tx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:55$4439 ($sub).
Removed top 27 bits (of 32) from port Y of cell top.$flatten\uart_I.\uart_tx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:55$4439 ($sub).
Removed top 1 bits (of 13) from mux cell top.$flatten\uart_I.\uart_tx_I.$procmux$5036 ($mux).
Removed top 1 bits (of 5) from FF cell top.$auto$ff.cc:266:slice$21419 ($adffe).
Removed top 24 bits (of 32) from mux cell top.$flatten\uart_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:189$2972 ($mux).
Removed top 1 bits (of 2) from port B of cell top.$flatten\uart_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_wb.v:172$2951 ($eq).
Removed top 1 bits (of 52) from port A of cell top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2461$1981 ($add).
Removed top 2 bits (of 34) from FF cell top.$auto$ff.cc:266:slice$21581 ($dffe).
Removed top 1 bits (of 3) from mux cell top.$flatten\cache_bus_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:148$3393 ($mux).
Removed top 2 bits (of 34) from port Y of cell top.$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996 ($mul).
Removed top 24 bits (of 32) from wire top.$flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:33$3349_EN[31:0]$3356.
Removed top 16 bits (of 32) from wire top.$flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:34$3350_EN[31:0]$3359.
Removed top 8 bits (of 32) from wire top.$flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:35$3351_EN[31:0]$3362.
Removed top 1 bits (of 2) from wire top.$flatten\cache_I.$1\ev_way[1:0].
Removed top 1 bits (of 2) from wire top.$flatten\cache_I.$1\lu_hit_way[1:0].
Removed top 29 bits (of 32) from wire top.$flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:224$4525_Y.
Removed top 30 bits (of 32) from wire top.$flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4580_Y.
Removed top 30 bits (of 32) from wire top.$flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4583_Y.
Removed top 30 bits (of 32) from wire top.$flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4586_Y.
Removed top 2 bits (of 3) from wire top.$flatten\cache_bus_I.$eq$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:224$3418_Y.
Removed top 2 bits (of 3) from wire top.$flatten\cache_bus_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:224$3419_Y.
Removed top 31 bits (of 32) from wire top.$flatten\cache_bus_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:146$3391_Y.
Removed top 30 bits (of 32) from wire top.$flatten\cache_bus_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:148$3392_Y.
Removed top 30 bits (of 32) from wire top.$flatten\cache_bus_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:148$3393_Y.
Removed top 29 bits (of 32) from wire top.$flatten\cache_bus_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:156$3394_Y.
Removed top 1 bits (of 33) from wire top.$flatten\cpu_I.$0\memory_DivPlugin_rs1[32:0].
Removed top 1 bits (of 33) from wire top.$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4655$2454_Y.
Removed top 1 bits (of 33) from wire top.$flatten\cpu_I.$not$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4655$2452_Y.
Removed top 19 bits (of 32) from wire top.$flatten\cpu_I.$or$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4253$2370_Y.
Removed top 1 bits (of 33) from wire top.$flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4655$2453_Y.
Removed top 24 bits (of 32) from wire top.$flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:510$3050_Y.
Removed top 16 bits (of 32) from wire top.$flatten\memctrl_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:377$3026_Y.
Removed top 19 bits (of 32) from wire top.$flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:79$4417_Y.
Removed top 19 bits (of 32) from wire top.$flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:83$4418_Y.
Removed top 27 bits (of 32) from wire top.$flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:92$4421_Y.
Removed top 23 bits (of 32) from wire top.$flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:112$3977_Y.
Removed top 1 bits (of 13) from wire top.$flatten\uart_I.\uart_tx_I.$0\div_cnt[12:0].
Removed top 19 bits (of 32) from wire top.$flatten\uart_I.\uart_tx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:46$4436_Y.
Removed top 27 bits (of 32) from wire top.$flatten\uart_I.\uart_tx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:55$4439_Y.
Removed top 23 bits (of 32) from wire top.$flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:112$3977_Y.
Removed top 28 bits (of 32) from wire top.$flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:99$3975_Y.
Removed top 15 bits (of 16) from wire top.$flatten\vid_I.$and$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:182$1626_Y.
Removed top 7 bits (of 16) from wire top.$flatten\vid_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:236$1634_Y.
Removed top 8 bits (of 32) from wire top.$flatten\vid_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:255$1645_Y.
Removed top 22 bits (of 32) from wire top.wb_rdata[1].
Removed top 32 bits (of 128) from wire top.wb_rdata_flat.

63.14. Executing PEEPOPT pass (run peephole optimizers).

63.15. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 38 unused wires.
<suppressed ~2 debug messages>

63.16. Executing SHARE pass (SAT-based resource sharing).

63.17. Executing TECHMAP pass (map to technology primitives).

63.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/cmp2lut.v
Parsing Verilog input from `/usr/bin/../share/yosys/cmp2lut.v' to AST representation.
Generating RTLIL representation for module `\_90_lut_cmp_'.
Successfully finished Verilog frontend.

63.17.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~140 debug messages>

63.18. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.19. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.20. Executing MEMORY_DFF pass (merging $dff cells to $memrd).
Checking read port `$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698'[0] in module `\top': merging output FF to cell.
Checking read port `\bram_I.mem'[0] in module `\top': merging output FF to cell.
    Write port 0: don't care on collision.
    Write port 1: don't care on collision.
    Write port 2: don't care on collision.
    Write port 3: don't care on collision.
Checking read port `\cpu_I.IBusCachedPlugin_cache.ways_0_datas'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\cpu_I.IBusCachedPlugin_cache.ways_0_tags'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\cpu_I.RegFilePlugin_regFile'[0] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\cpu_I.RegFilePlugin_regFile'[1] in module `\top': merging output FF to cell.
    Write port 0: non-transparent.
Checking read port `\sys_mgr_I.crg_I.rst_cnt_nxt'[0] in module `\top': merging output FF to cell.
Checking read port `\uart_I.uart_rx_fifo_I.ram_I.ram'[0] in module `\top': merging output FF to cell.
    Write port 0: don't care on collision.
Checking read port `\uart_I.uart_tx_fifo_I.ram_I.ram'[0] in module `\top': merging output FF to cell.
    Write port 0: don't care on collision.

63.21. Executing WREDUCE pass (reducing word size of cells).

63.22. Executing TECHMAP pass (map to technology primitives).

63.22.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/mul2dsp.v
Parsing Verilog input from `/usr/bin/../share/yosys/mul2dsp.v' to AST representation.
Generating RTLIL representation for module `\_80_mul'.
Generating RTLIL representation for module `\_90_soft_mul'.
Successfully finished Verilog frontend.

63.22.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/dsp_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/dsp_map.v' to AST representation.
Generating RTLIL representation for module `\$__MUL16X16'.
Successfully finished Verilog frontend.

63.22.3. Continuing TECHMAP pass.
Using template $paramod$db92b6ce7390ae2cad7a93c07bad8126ba118608\_80_mul for cells of type $mul.
Using template $paramod$0918209bb5c6f08b2ecd7ae36d3d7f82c80ec9f5\_80_mul for cells of type $mul.
Using template $paramod$0910e2344b2d36624760245c86bb61f4bc3ddcd6\_80_mul for cells of type $mul.
Using template $paramod$89b47b3b03079ae827ef72992fb433a02767e696\_80_mul for cells of type $__mul.
Using template $paramod$a19312d7f427efc0aa1e2a110ea5a3ab36da06e8\_90_soft_mul for cells of type $__mul.
Using template $paramod$e0bf24ff28f216f530a4f8f71562f6bd1c62dd0a\_80_mul for cells of type $__mul.
Using template $paramod$883b16feea3db6c21c52460379fab8bbe7f97d65\$__MUL16X16 for cells of type $__MUL16X16.
Using template $paramod$92398c55cd62669b28876c227b4269e3610ebe7b\_80_mul for cells of type $__mul.
Using template $paramod$04102eddbb25e3003f2ea9d39f38ce53d47fc2f5\_90_soft_mul for cells of type $__mul.
No more expansions possible.
<suppressed ~622 debug messages>

63.23. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6 debug messages>

63.24. Executing WREDUCE pass (reducing word size of cells).
Removed top 1 bits (of 17) from port B of cell top.$techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/bin/../share/yosys/mul2dsp.v:230$21891 ($add).
Removed top 1 bits (of 18) from port B of cell top.$techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.$add$/usr/bin/../share/yosys/mul2dsp.v:173$21888 ($add).
Removed top 1 bits (of 18) from port B of cell top.$techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.$add$/usr/bin/../share/yosys/mul2dsp.v:173$21888 ($add).
Removed top 1 bits (of 17) from port B of cell top.$techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/bin/../share/yosys/mul2dsp.v:230$21891 ($add).

63.25. Executing ICE40_DSP pass (map multipliers).
Checking top.$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceB[0].mul for iCE40 DSP inference.
  clock: \bram_I.clk (posedge) ffA:$auto$ff.cc:266:slice$21580 ffB:$auto$ff.cc:266:slice$21539 ffO:$auto$ff.cc:266:slice$21533
Checking top.$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceB[0].mul for iCE40 DSP inference.
  clock: \bram_I.clk (posedge) ffA:$auto$ff.cc:266:slice$21580 ffB:$auto$ff.cc:266:slice$21539 ffO:$auto$ff.cc:266:slice$21581
Checking top.$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceB[0].mul for iCE40 DSP inference.
  clock: \bram_I.clk (posedge) ffA:$auto$ff.cc:266:slice$21580 ffB:$auto$ff.cc:266:slice$21539 ffO:$auto$ff.cc:266:slice$21559
Checking top.$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2490$1992 for iCE40 DSP inference.
  clock: \bram_I.clk (posedge) ffA:$auto$ff.cc:266:slice$21580 ffB:$auto$ff.cc:266:slice$21539 ffO:$auto$ff.cc:266:slice$21571
<suppressed ~40 debug messages>

63.26. Executing ALUMACC pass (create $alu and $macc cells).
Extracting $alu and $macc cells in module top:
  creating $macc model for $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/bin/../share/yosys/mul2dsp.v:230$21891 ($add).
  creating $macc model for $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last ($mul).
  creating $macc model for $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/bin/../share/yosys/mul2dsp.v:230$21895 ($add).
  creating $macc model for $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last ($mul).
  creating $macc model for $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/bin/../share/yosys/mul2dsp.v:230$21891 ($add).
  creating $macc model for $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.mul_sliceB_last ($mul).
  creating $macc model for $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.$add$/usr/bin/../share/yosys/mul2dsp.v:173$21888 ($add).
  creating $macc model for $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.$add$/usr/bin/../share/yosys/mul2dsp.v:173$21888 ($add).
  creating $macc model for $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last ($mul).
  creating $macc model for $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996.$add$/usr/bin/../share/yosys/mul2dsp.v:173$21884 ($add).
  creating $macc model for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:224$4525 ($add).
  creating $macc model for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4580 ($add).
  creating $macc model for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4583 ($add).
  creating $macc model for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4586 ($add).
  creating $macc model for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4589 ($add).
  creating $macc model for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:420$4592 ($add).
  creating $macc model for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:420$4595 ($add).
  creating $macc model for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:420$4598 ($add).
  creating $macc model for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:420$4601 ($add).
  creating $macc model for $flatten\cache_bus_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:224$3420 ($add).
  creating $macc model for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1456$1823 ($add).
  creating $macc model for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1498$1831 ($add).
  creating $macc model for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1499$1832 ($add).
  creating $macc model for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1527$1840 ($add).
  creating $macc model for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2461$1981 ($add).
  creating $macc model for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2947$2077 ($add).
  creating $macc model for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3156$2122 ($add).
  creating $macc model for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3860$2234 ($add).
  creating $macc model for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4097$2290 ($add).
  creating $macc model for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4121$2296 ($add).
  creating $macc model for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4655$2454 ($add).
  creating $macc model for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4656$2457 ($add).
  creating $macc model for $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.mul_sliceB_last ($mul).
  creating $macc model for $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.mul_sliceB_last ($mul).
  creating $macc model for $flatten\cpu_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1482$1830 ($sub).
  creating $macc model for $flatten\cpu_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4130$2297 ($sub).
  creating $macc model for $flatten\cpu_I.\IBusCachedPlugin_cache.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:294$1775 ($add).
  creating $macc model for $flatten\cpu_I.\IBusCachedPlugin_cache.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:307$1777 ($add).
  creating $macc model for $flatten\memctrl_I.$neg$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3194 ($neg).
  creating $macc model for $flatten\memctrl_I.$neg$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3203 ($neg).
  creating $macc model for $flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:510$3050 ($sub).
  creating $macc model for $flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:517$3053 ($sub).
  creating $macc model for $flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:695$3084 ($sub).
  creating $macc model for $flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3121 ($sub).
  creating $macc model for $flatten\sys_mgr_I.\crg_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:78$4055 ($add).
  creating $macc model for $flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:79$4417 ($sub).
  creating $macc model for $flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:83$4418 ($sub).
  creating $macc model for $flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:92$4421 ($sub).
  creating $macc model for $flatten\uart_I.\uart_rx_I.\genblk1.gf_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:74$3502 ($add).
  creating $macc model for $flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:112$3977 ($add).
  creating $macc model for $flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:71$3960 ($add).
  creating $macc model for $flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:99$3975 ($add).
  creating $macc model for $flatten\uart_I.\uart_tx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:46$4436 ($sub).
  creating $macc model for $flatten\uart_I.\uart_tx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:55$4439 ($sub).
  creating $macc model for $flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:112$3977 ($add).
  creating $macc model for $flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:71$3960 ($add).
  creating $macc model for $flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:99$3975 ($add).
  creating $macc model for $flatten\vid_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:182$1627 ($add).
  creating $macc model for $flatten\vid_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:236$1635 ($add).
  creating $macc model for $flatten\vid_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:243$1638 ($add).
  creating $macc model for $flatten\vid_I.\tgen_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:106$3934 ($add).
  creating $macc model for $flatten\vid_I.\tgen_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:145$3943 ($add).
  creating $macc model for $flatten\vid_I.\tgen_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:128$3937 ($sub).
  creating $macc model for $flatten\vid_I.\tgen_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:93$3931 ($sub).
  merging $macc model for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1456$1823 into $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2461$1981.
  merging $macc model for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1499$1832 into $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1498$1831.
  merging $macc model for $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/bin/../share/yosys/mul2dsp.v:230$21895 into $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996.$add$/usr/bin/../share/yosys/mul2dsp.v:173$21884.
  merging $macc model for $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last into $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.$add$/usr/bin/../share/yosys/mul2dsp.v:173$21888.
  merging $macc model for $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last into $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.$add$/usr/bin/../share/yosys/mul2dsp.v:173$21888.
  merging $macc model for $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.mul_sliceB_last into $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/bin/../share/yosys/mul2dsp.v:230$21891.
  merging $macc model for $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.mul_sliceB_last into $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/bin/../share/yosys/mul2dsp.v:230$21891.
  creating $alu model for $macc $flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:99$3975.
  creating $alu model for $macc $flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:71$3960.
  creating $alu model for $macc $flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:112$3977.
  creating $alu model for $macc $flatten\uart_I.\uart_tx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:55$4439.
  creating $alu model for $macc $flatten\uart_I.\uart_tx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:46$4436.
  creating $alu model for $macc $flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:99$3975.
  creating $alu model for $macc $flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:71$3960.
  creating $alu model for $macc $flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:112$3977.
  creating $alu model for $macc $flatten\uart_I.\uart_rx_I.\genblk1.gf_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:74$3502.
  creating $alu model for $macc $flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:92$4421.
  creating $alu model for $macc $flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:83$4418.
  creating $alu model for $macc $flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:79$4417.
  creating $alu model for $macc $flatten\sys_mgr_I.\crg_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:78$4055.
  creating $alu model for $macc $flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3121.
  creating $alu model for $macc $flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:695$3084.
  creating $alu model for $macc $flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:517$3053.
  creating $alu model for $macc $flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:510$3050.
  creating $alu model for $macc $flatten\memctrl_I.$neg$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3203.
  creating $alu model for $macc $flatten\memctrl_I.$neg$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3194.
  creating $alu model for $macc $flatten\cpu_I.\IBusCachedPlugin_cache.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:307$1777.
  creating $alu model for $macc $flatten\cpu_I.\IBusCachedPlugin_cache.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:294$1775.
  creating $alu model for $macc $flatten\cpu_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4130$2297.
  creating $alu model for $macc $flatten\cpu_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1482$1830.
  creating $alu model for $macc $flatten\vid_I.\tgen_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:93$3931.
  creating $alu model for $macc $flatten\vid_I.\tgen_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:128$3937.
  creating $alu model for $macc $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4656$2457.
  creating $alu model for $macc $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4655$2454.
  creating $alu model for $macc $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4121$2296.
  creating $alu model for $macc $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4097$2290.
  creating $alu model for $macc $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3860$2234.
  creating $alu model for $macc $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3156$2122.
  creating $alu model for $macc $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2947$2077.
  creating $alu model for $macc $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1527$1840.
  creating $alu model for $macc $flatten\vid_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:236$1635.
  creating $alu model for $macc $flatten\vid_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:182$1627.
  creating $alu model for $macc $flatten\cache_bus_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:224$3420.
  creating $alu model for $macc $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:420$4601.
  creating $alu model for $macc $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:420$4598.
  creating $alu model for $macc $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:420$4595.
  creating $alu model for $macc $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:420$4592.
  creating $alu model for $macc $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4589.
  creating $alu model for $macc $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4586.
  creating $alu model for $macc $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4583.
  creating $alu model for $macc $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4580.
  creating $alu model for $macc $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:224$4525.
  creating $alu model for $macc $flatten\vid_I.\tgen_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:106$3934.
  creating $alu model for $macc $flatten\vid_I.\tgen_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:145$3943.
  creating $alu model for $macc $flatten\vid_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:243$1638.
  creating $macc cell for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1498$1831: $auto$alumacc.cc:365:replace_macc$21924
  creating $macc cell for $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.$add$/usr/bin/../share/yosys/mul2dsp.v:173$21888: $auto$alumacc.cc:365:replace_macc$21925
  creating $macc cell for $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.$add$/usr/bin/../share/yosys/mul2dsp.v:173$21888: $auto$alumacc.cc:365:replace_macc$21926
  creating $macc cell for $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.mul_sliceB_last: $auto$alumacc.cc:365:replace_macc$21927
  creating $macc cell for $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/bin/../share/yosys/mul2dsp.v:230$21891: $auto$alumacc.cc:365:replace_macc$21928
  creating $macc cell for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2461$1981: $auto$alumacc.cc:365:replace_macc$21929
  creating $macc cell for $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996.$add$/usr/bin/../share/yosys/mul2dsp.v:173$21884: $auto$alumacc.cc:365:replace_macc$21930
  creating $macc cell for $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA.last: $auto$alumacc.cc:365:replace_macc$21931
  creating $macc cell for $techmap$flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.$add$/usr/bin/../share/yosys/mul2dsp.v:230$21891: $auto$alumacc.cc:365:replace_macc$21932
  creating $alu model for $flatten\cache_I.$lt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:409$4579 ($lt): new $alu
  creating $alu model for $flatten\cache_I.$lt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:409$4582 ($lt): new $alu
  creating $alu model for $flatten\cache_I.$lt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:409$4585 ($lt): new $alu
  creating $alu model for $flatten\cache_I.$lt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:409$4588 ($lt): new $alu
  creating $alu model for $flatten\memctrl_I.$ge$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3122 ($ge): new $alu
  creating $alu model for $flatten\memctrl_I.$ge$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3126 ($ge): new $alu
  creating $alu model for $flatten\memctrl_I.$ge$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3130 ($ge): new $alu
  creating $alu model for $flatten\memctrl_I.$ge$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3134 ($ge): new $alu
  creating $alu cell for $flatten\memctrl_I.$ge$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3134: $auto$alumacc.cc:485:replace_alu$21941
  creating $alu cell for $flatten\memctrl_I.$ge$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3130: $auto$alumacc.cc:485:replace_alu$21954
  creating $alu cell for $flatten\memctrl_I.$ge$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3126: $auto$alumacc.cc:485:replace_alu$21967
  creating $alu cell for $flatten\memctrl_I.$ge$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3122: $auto$alumacc.cc:485:replace_alu$21980
  creating $alu cell for $flatten\cache_I.$lt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:409$4588: $auto$alumacc.cc:485:replace_alu$21993
  creating $alu cell for $flatten\cache_I.$lt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:409$4585: $auto$alumacc.cc:485:replace_alu$22004
  creating $alu cell for $flatten\cache_I.$lt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:409$4582: $auto$alumacc.cc:485:replace_alu$22015
  creating $alu cell for $flatten\cache_I.$lt$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:409$4579: $auto$alumacc.cc:485:replace_alu$22026
  creating $alu cell for $flatten\vid_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:243$1638: $auto$alumacc.cc:485:replace_alu$22037
  creating $alu cell for $flatten\vid_I.\tgen_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:145$3943: $auto$alumacc.cc:485:replace_alu$22040
  creating $alu cell for $flatten\vid_I.\tgen_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:106$3934: $auto$alumacc.cc:485:replace_alu$22043
  creating $alu cell for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:224$4525: $auto$alumacc.cc:485:replace_alu$22046
  creating $alu cell for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4580: $auto$alumacc.cc:485:replace_alu$22049
  creating $alu cell for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4583: $auto$alumacc.cc:485:replace_alu$22052
  creating $alu cell for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4586: $auto$alumacc.cc:485:replace_alu$22055
  creating $alu cell for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:410$4589: $auto$alumacc.cc:485:replace_alu$22058
  creating $alu cell for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:420$4592: $auto$alumacc.cc:485:replace_alu$22061
  creating $alu cell for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:420$4595: $auto$alumacc.cc:485:replace_alu$22064
  creating $alu cell for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:420$4598: $auto$alumacc.cc:485:replace_alu$22067
  creating $alu cell for $flatten\cache_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_core.v:420$4601: $auto$alumacc.cc:485:replace_alu$22070
  creating $alu cell for $flatten\cache_bus_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:224$3420: $auto$alumacc.cc:485:replace_alu$22073
  creating $alu cell for $flatten\vid_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:182$1627: $auto$alumacc.cc:485:replace_alu$22076
  creating $alu cell for $flatten\vid_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:236$1635: $auto$alumacc.cc:485:replace_alu$22079
  creating $alu cell for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1527$1840: $auto$alumacc.cc:485:replace_alu$22082
  creating $alu cell for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2947$2077: $auto$alumacc.cc:485:replace_alu$22085
  creating $alu cell for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3156$2122: $auto$alumacc.cc:485:replace_alu$22088
  creating $alu cell for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3860$2234: $auto$alumacc.cc:485:replace_alu$22091
  creating $alu cell for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4097$2290: $auto$alumacc.cc:485:replace_alu$22094
  creating $alu cell for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4121$2296: $auto$alumacc.cc:485:replace_alu$22097
  creating $alu cell for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4655$2454: $auto$alumacc.cc:485:replace_alu$22100
  creating $alu cell for $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4656$2457: $auto$alumacc.cc:485:replace_alu$22103
  creating $alu cell for $flatten\vid_I.\tgen_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:128$3937: $auto$alumacc.cc:485:replace_alu$22106
  creating $alu cell for $flatten\vid_I.\tgen_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/video//rtl/vid_tgen.v:93$3931: $auto$alumacc.cc:485:replace_alu$22109
  creating $alu cell for $flatten\cpu_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:1482$1830: $auto$alumacc.cc:485:replace_alu$22112
  creating $alu cell for $flatten\cpu_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:4130$2297: $auto$alumacc.cc:485:replace_alu$22115
  creating $alu cell for $flatten\cpu_I.\IBusCachedPlugin_cache.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:294$1775: $auto$alumacc.cc:485:replace_alu$22118
  creating $alu cell for $flatten\cpu_I.\IBusCachedPlugin_cache.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:307$1777: $auto$alumacc.cc:485:replace_alu$22121
  creating $alu cell for $flatten\memctrl_I.$neg$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3194: $auto$alumacc.cc:485:replace_alu$22124
  creating $alu cell for $flatten\memctrl_I.$neg$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:0$3203: $auto$alumacc.cc:485:replace_alu$22127
  creating $alu cell for $flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:510$3050: $auto$alumacc.cc:485:replace_alu$22130
  creating $alu cell for $flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:517$3053: $auto$alumacc.cc:485:replace_alu$22133
  creating $alu cell for $flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:695$3084: $auto$alumacc.cc:485:replace_alu$22136
  creating $alu cell for $flatten\memctrl_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:723$3121: $auto$alumacc.cc:485:replace_alu$22139
  creating $alu cell for $flatten\sys_mgr_I.\crg_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:78$4055: $auto$alumacc.cc:485:replace_alu$22142
  creating $alu cell for $flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:79$4417: $auto$alumacc.cc:485:replace_alu$22145
  creating $alu cell for $flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:83$4418: $auto$alumacc.cc:485:replace_alu$22148
  creating $alu cell for $flatten\uart_I.\uart_rx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_rx.v:92$4421: $auto$alumacc.cc:485:replace_alu$22151
  creating $alu cell for $flatten\uart_I.\uart_rx_I.\genblk1.gf_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/glitch_filter.v:74$3502: $auto$alumacc.cc:485:replace_alu$22154
  creating $alu cell for $flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:112$3977: $auto$alumacc.cc:485:replace_alu$22157
  creating $alu cell for $flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:71$3960: $auto$alumacc.cc:485:replace_alu$22160
  creating $alu cell for $flatten\uart_I.\uart_rx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:99$3975: $auto$alumacc.cc:485:replace_alu$22163
  creating $alu cell for $flatten\uart_I.\uart_tx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:46$4436: $auto$alumacc.cc:485:replace_alu$22166
  creating $alu cell for $flatten\uart_I.\uart_tx_I.$sub$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/uart_tx.v:55$4439: $auto$alumacc.cc:485:replace_alu$22169
  creating $alu cell for $flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:112$3977: $auto$alumacc.cc:485:replace_alu$22172
  creating $alu cell for $flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:71$3960: $auto$alumacc.cc:485:replace_alu$22175
  creating $alu cell for $flatten\uart_I.\uart_tx_fifo_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_ram.v:99$3975: $auto$alumacc.cc:485:replace_alu$22178
  created 56 $alu and 9 $macc cells.

63.27. Executing OPT pass (performing simple optimizations).

63.27.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6 debug messages>

63.27.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3 debug messages>
Removed a total of 1 cells.

63.27.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~228 debug messages>

63.27.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

63.27.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.27.6. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 8 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 9 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 10 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 11 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 12 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 13 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 14 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 15 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 16 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 17 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 18 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 19 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 20 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 21 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 22 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.
Setting constant 0-bit at position 23 on $auto$ff.cc:266:slice$21417 ($sdff) from module top.

63.27.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 20 unused cells and 296 unused wires.
<suppressed ~23 debug messages>

63.27.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.27.9. Rerunning OPT passes. (Maybe there is more to do..)

63.27.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~228 debug messages>

63.27.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

63.27.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.27.13. Executing OPT_DFF pass (perform DFF optimizations).

63.27.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.27.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.27.16. Finished OPT passes. (There is nothing left to do.)

63.28. Executing MEMORY pass.

63.28.1. Executing OPT_MEM pass (optimize memories).
Performed a total of 96 transformations.

63.28.2. Executing OPT_MEM_PRIORITY pass (removing unnecessary memory write priority relations).
Performed a total of 6 transformations.

63.28.3. Executing OPT_MEM_FEEDBACK pass (finding memory read-to-write feedback paths).

63.28.4. Executing MEMORY_BMUX2ROM pass (converting muxes to ROMs).

63.28.5. Executing MEMORY_DFF pass (merging $dff cells to $memrd).

63.28.6. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.28.7. Executing MEMORY_SHARE pass (consolidating $memrd/$memwr cells).
Consolidating write ports of memory top.bram_I.mem by address:
  Merging ports 0, 1 (address \cache_I.req_addr_pre [7:0]).
  Merging ports 0, 2 (address \cache_I.req_addr_pre [7:0]).
  Merging ports 0, 3 (address \cache_I.req_addr_pre [7:0]).
Consolidating read ports of memory top.cpu_I.RegFilePlugin_regFile by address:

63.28.8. Executing OPT_MEM_WIDEN pass (optimize memories where all ports are wide).
Performed a total of 0 transformations.

63.28.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 4 unused cells and 4 unused wires.
<suppressed ~5 debug messages>

63.28.10. Executing MEMORY_COLLECT pass (generating $mem cells).

63.29. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.30. Executing MEMORY_LIBMAP pass (mapping memories to cells).
using FF mapping for memory top.$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698
mapping memory top.bram_I.mem via $__ICE40_RAM4K_
mapping memory top.cpu_I.IBusCachedPlugin_cache.ways_0_datas via $__ICE40_RAM4K_
mapping memory top.cpu_I.IBusCachedPlugin_cache.ways_0_tags via $__ICE40_RAM4K_
mapping memory top.cpu_I.RegFilePlugin_regFile via $__ICE40_RAM4K_
using FF mapping for memory top.sys_mgr_I.crg_I.rst_cnt_nxt
mapping memory top.uart_I.uart_rx_fifo_I.ram_I.ram via $__ICE40_RAM4K_
mapping memory top.uart_I.uart_tx_fifo_I.ram_I.ram via $__ICE40_RAM4K_
<suppressed ~519 debug messages>

63.31. Executing TECHMAP pass (map to technology primitives).

63.31.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/brams_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/brams_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_RAM4K_'.
Successfully finished Verilog frontend.

63.31.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/spram_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/spram_map.v' to AST representation.
Generating RTLIL representation for module `\$__ICE40_SPRAM_'.
Successfully finished Verilog frontend.

63.31.3. Continuing TECHMAP pass.
Using template $paramod$13b3947419e62b7bbba1b93c77e4155efbe69a94\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_.
Using template $paramod$a1f6b5309207cf102bfb625dccbd224ad06df61d\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_.
Using template $paramod$6cc8fd47caff289061963e34e1c9c65b14b0572b\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_.
Using template $paramod$263d2dc0491cea06b00e73804e105f483fcfc9bb\$__ICE40_RAM4K_ for cells of type $__ICE40_RAM4K_.
No more expansions possible.
<suppressed ~108 debug messages>

63.32. Executing ICE40_BRAMINIT pass.

63.33. Executing OPT pass (performing simple optimizations).

63.33.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~387 debug messages>

63.33.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~21 debug messages>
Removed a total of 7 cells.

63.33.3. Executing OPT_DFF pass (perform DFF optimizations).
Adding EN signal on $flatten\memctrl_I.$procdff$20654 ($dff) from module top (D = $flatten\memctrl_I.$0\so_cnt[5:0] [1:0], Q = \memctrl_I.so_cnt [1:0]).
Removing always-active EN on $auto$mem.cc:1146:emulate_transparency$22247 ($dffe) from module top.
Setting constant 1-bit at position 0 on $auto$ff.cc:266:slice$21616 ($dffe) from module top.
Setting constant 1-bit at position 1 on $auto$ff.cc:266:slice$21616 ($dffe) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$21616 ($dffe) from module top.
Setting constant 1-bit at position 3 on $auto$ff.cc:266:slice$21616 ($dffe) from module top.

63.33.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 9 unused cells and 329 unused wires.
<suppressed ~10 debug messages>

63.33.5. Rerunning OPT passes. (Removed registers in this run.)

63.33.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3 debug messages>

63.33.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.33.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$mem.cc:1625:emulate_read_first$22235 ($dff) from module top (D = \cpu_I._zz_169_, Q = $auto$mem.cc:1622:emulate_read_first$22232, rval = 1'1).
Setting constant 1-bit at position 0 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 1 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 2 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 3 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 4 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 5 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 6 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 7 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 8 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 9 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 10 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 11 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 12 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 13 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 14 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 15 on $auto$ff.cc:266:slice$21533 ($dffe) from module top.
Setting constant 1-bit at position 0 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 1 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 2 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 3 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 4 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 5 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 6 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 7 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 8 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 9 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 10 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 11 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 12 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 13 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 14 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 15 on $auto$ff.cc:266:slice$21559 ($dffe) from module top.
Setting constant 1-bit at position 0 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 1 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 2 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 3 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 4 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 5 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 6 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 7 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 8 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 9 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 10 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 11 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 12 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 13 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 14 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 15 on $auto$ff.cc:266:slice$21581 ($dffe) from module top.
Setting constant 1-bit at position 0 on $auto$ff.cc:266:slice$21652 ($sdffce) from module top.
Setting constant 1-bit at position 1 on $auto$ff.cc:266:slice$21652 ($sdffce) from module top.
Setting constant 0-bit at position 2 on $auto$ff.cc:266:slice$21652 ($sdffce) from module top.
Setting constant 0-bit at position 1 on $auto$mem.cc:1623:emulate_read_first$22211 ($dff) from module top.

63.33.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 8 unused wires.
<suppressed ~4 debug messages>

63.33.10. Rerunning OPT passes. (Removed registers in this run.)

63.33.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.33.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.33.13. Executing OPT_DFF pass (perform DFF optimizations).
Setting constant 0-bit at position 1 on $auto$mem.cc:1146:emulate_transparency$22215 ($dffe) from module top.

63.33.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.33.15. Rerunning OPT passes. (Removed registers in this run.)

63.33.16. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.33.17. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.33.18. Executing OPT_DFF pass (perform DFF optimizations).

63.33.19. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.33.20. Finished fast OPT passes.

63.34. Executing MEMORY_MAP pass (converting memories to logic and flip-flops).
Mapping memory $flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698 in module \top:
  created 16 $dff cells and 0 static cells of width 5.
Extracted data FF from read port 0 of top.$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698: $$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdreg[0]
  read interface: 1 $dff and 15 $mux cells.
  write interface: 0 write mux blocks.
Mapping memory \sys_mgr_I.crg_I.rst_cnt_nxt in module \top:
  created 16 $dff cells and 0 static cells of width 4.
Extracted data FF from read port 0 of top.sys_mgr_I.crg_I.rst_cnt_nxt: $\sys_mgr_I.crg_I.rst_cnt_nxt$rdreg[0]
  read interface: 1 $dff and 15 $mux cells.
  write interface: 0 write mux blocks.

63.35. Executing OPT pass (performing simple optimizations).

63.35.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~5 debug messages>

63.35.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.35.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
      Replacing known input bits on port A of cell $flatten\cpu_I.$procmux$6754: \cpu_I.IBusCachedPlugin_iBusRsp_redoFetch -> 1'0
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~188 debug messages>

63.35.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    New input vector for $reduce_or cell $auto$memory_libmap.cc:1855:emit_port$22184: { $flatten\bram_I.$0$memwr$\mem$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/soc_bram.v:36$3352_EN[31:0]$3365 [31] $auto$wreduce.cc:461:run$21660 [23] }
    New input vector for $reduce_or cell $auto$memory_libmap.cc:1855:emit_port$22182: { $auto$wreduce.cc:461:run$21659 [15] $auto$wreduce.cc:461:run$21658 [7] }
    Consolidated identical input bits for $mux cell $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][3][2]$22538:
      Old ports: A=4'0101, B=4'0110, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][1]$a$22524
      New ports: A=2'01, B=2'10, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][1]$a$22524 [1:0]
      New connections: $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][1]$a$22524 [3:2] = 2'01
    Consolidated identical input bits for $mux cell $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][3][1]$22535:
      Old ports: A=4'0011, B=4'0100, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$b$22522
      New ports: A=2'01, B=2'10, Y={ $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$b$22522 [2] $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$b$22522 [0] }
      New connections: { $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$b$22522 [3] $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$b$22522 [1] } = { 1'0 $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$b$22522 [0] }
    Consolidated identical input bits for $mux cell $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][3][0]$22532:
      Old ports: A=4'0001, B=4'0010, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521
      New ports: A=2'01, B=2'10, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [1:0]
      New connections: $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [3:2] = 2'00
    Consolidated identical input bits for $mux cell $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][3][5]$22547:
      Old ports: A=4'1011, B=4'1100, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$b$22528
      New ports: A=2'01, B=2'10, Y={ $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$b$22528 [2] $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$b$22528 [0] }
      New connections: { $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$b$22528 [3] $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$b$22528 [1] } = { 1'1 $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$b$22528 [0] }
    Consolidated identical input bits for $mux cell $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][3][5]$22502:
      Old ports: A=5'11011, B=5'00000, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$b$22483
      New ports: A=1'1, B=1'0, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$b$22483 [0]
      New connections: $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$b$22483 [4:1] = { $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$b$22483 [0] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$b$22483 [0] 1'0 $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$b$22483 [0] }
    Consolidated identical input bits for $mux cell $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][3][4]$22499:
      Old ports: A=5'01001, B=5'01010, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$a$22482
      New ports: A=2'01, B=2'10, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$a$22482 [1:0]
      New connections: $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$a$22482 [4:2] = 3'010
    Consolidated identical input bits for $mux cell $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][3][3]$22496:
      Old ports: A=5'00111, B=5'11000, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][1]$b$22480
      New ports: A=2'01, B=2'10, Y={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][1]$b$22480 [3] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][1]$b$22480 [0] }
      New connections: { $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][1]$b$22480 [4] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][1]$b$22480 [2:1] } = { $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][1]$b$22480 [3] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][1]$b$22480 [0] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][1]$b$22480 [0] }
    Consolidated identical input bits for $mux cell $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][3][2]$22493:
      Old ports: A=5'00101, B=5'10110, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][1]$a$22479
      New ports: A=2'01, B=2'10, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][1]$a$22479 [1:0]
      New connections: $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][1]$a$22479 [4:2] = { $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][1]$a$22479 [1] 2'01 }
    Consolidated identical input bits for $mux cell $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][3][1]$22490:
      Old ports: A=5'10011, B=5'00100, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$b$22477
      New ports: A=2'01, B=2'10, Y={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$b$22477 [2] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$b$22477 [0] }
      New connections: { $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$b$22477 [4:3] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$b$22477 [1] } = { $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$b$22477 [0] 1'0 $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$b$22477 [0] }
    Consolidated identical input bits for $mux cell $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][3][0]$22487:
      Old ports: A=5'10001, B=5'00010, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476
      New ports: A=2'01, B=2'10, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [1:0]
      New connections: $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4:2] = { $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [0] 2'00 }
    Consolidated identical input bits for $mux cell $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][3][4]$22544:
      Old ports: A=4'1001, B=4'1010, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$a$22527
      New ports: A=2'01, B=2'10, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$a$22527 [1:0]
      New connections: $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$a$22527 [3:2] = 2'10
    Consolidated identical input bits for $mux cell $flatten\cache_I.$procmux$4729:
      Old ports: A={ \cache_I.ev_way_r \cache_I.req_addr [11:3] \cache_I.cnt_ofs }, B={ \cache_I.lu_hit_way \cache_I.req_addr [11:0] }, Y=\cache_I.data_ram_I.mem_addr
      New ports: A={ \cache_I.ev_way_r \cache_I.cnt_ofs }, B={ \cache_I.lu_hit_way \cache_I.req_addr [2:0] }, Y={ \cache_I.data_ram_I.mem_addr [13:12] \cache_I.data_ram_I.mem_addr [2:0] }
      New connections: \cache_I.data_ram_I.mem_addr [11:3] = \cache_I.req_addr [11:3]
    Consolidated identical input bits for $mux cell $flatten\cache_bus_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2memcache//rtl/mc_bus_vex.v:156$3394:
      Old ports: A=3'000, B=3'110, Y=$auto$wreduce.cc:461:run$21672 [2:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$21672 [1]
      New connections: { $auto$wreduce.cc:461:run$21672 [2] $auto$wreduce.cc:461:run$21672 [0] } = { $auto$wreduce.cc:461:run$21672 [1] 1'0 }
    Consolidated identical input bits for $pmux cell $flatten\cpu_I.$procmux$6323:
      Old ports: A=4'1111, B=8'00010011, Y=\cpu_I._zz_156_
      New ports: A=2'11, B=4'0001, Y=\cpu_I._zz_156_ [2:1]
      New connections: { \cpu_I._zz_156_ [3] \cpu_I._zz_156_ [0] } = { \cpu_I._zz_156_ [2] 1'1 }
    Consolidated identical input bits for $mux cell $flatten\cpu_I.$procmux$6336:
      Old ports: A=4'0000, B={ \cpu_I.CsrPlugin_mcause_exceptionCode [3] 3'011 }, Y=\cpu_I._zz_152_ [3:0]
      New ports: A=2'00, B={ \cpu_I.CsrPlugin_mcause_exceptionCode [3] 1'1 }, Y={ \cpu_I._zz_152_ [3] \cpu_I._zz_152_ [0] }
      New connections: \cpu_I._zz_152_ [2:1] = { 1'0 \cpu_I._zz_152_ [0] }
    Consolidated identical input bits for $mux cell $flatten\cpu_I.$procmux$6523:
      Old ports: A={ \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3814$2231_Y [19:0] }, B=4, Y=$flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0]
      New ports: A={ \cpu_I.decode_to_execute_INSTRUCTION [31] $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3814$2231_Y [19:0] }, B=21'000000000000000000100, Y=$flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20:0]
      New connections: $flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [31:21] = { $flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20] $flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20] }
    Consolidated identical input bits for $pmux cell $flatten\cpu_I.$procmux$6700:
      Old ports: A={ \cpu_I.memory_to_writeBack_MEMORY_READ_DATA [31:16] \cpu_I._zz_87_ [15:8] \cpu_I._zz_85_ [7:0] }, B={ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_85_ [7:0] \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_87_ [15:8] \cpu_I._zz_85_ [7:0] }, Y=\cpu_I.writeBack_DBusSimplePlugin_rspFormated
      New ports: A={ \cpu_I.memory_to_writeBack_MEMORY_READ_DATA [31:16] \cpu_I._zz_87_ [15:8] }, B={ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_84_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_86_ \cpu_I._zz_87_ [15:8] }, Y=\cpu_I.writeBack_DBusSimplePlugin_rspFormated [31:8]
      New connections: \cpu_I.writeBack_DBusSimplePlugin_rspFormated [7:0] = \cpu_I._zz_85_ [7:0]
    Consolidated identical input bits for $pmux cell $flatten\cpu_I.$procmux$6744:
      Old ports: A=\cpu_I.decode_to_execute_RS2, B={ \cpu_I.decode_to_execute_RS2 [7:0] \cpu_I.decode_to_execute_RS2 [7:0] \cpu_I.decode_to_execute_RS2 [7:0] \cpu_I.decode_to_execute_RS2 [7:0] \cpu_I.decode_to_execute_RS2 [15:0] \cpu_I.decode_to_execute_RS2 [15:0] }, Y=\cpu_I._zz_82_
      New ports: A=\cpu_I.decode_to_execute_RS2 [31:8], B={ \cpu_I.decode_to_execute_RS2 [7:0] \cpu_I.decode_to_execute_RS2 [7:0] \cpu_I.decode_to_execute_RS2 [7:0] \cpu_I.decode_to_execute_RS2 [15:0] \cpu_I.decode_to_execute_RS2 [15:8] }, Y=\cpu_I._zz_82_ [31:8]
      New connections: \cpu_I._zz_82_ [7:0] = \cpu_I.decode_to_execute_RS2 [7:0]
    Consolidated identical input bits for $mux cell $flatten\cpu_I.$procmux$6793:
      Old ports: A={ $flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2947$2077_Y [31:2] 2'00 }, B={ \cpu_I.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress [31:2] 2'00 }, Y=$flatten\cpu_I.$1\IBusCachedPlugin_fetchPc_pc[31:0]
      New ports: A=$flatten\cpu_I.$add$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2947$2077_Y [31:2], B=\cpu_I.IBusCachedPlugin_cache.decodeStage_mmuRsp_physicalAddress [31:2], Y=$flatten\cpu_I.$1\IBusCachedPlugin_fetchPc_pc[31:0] [31:2]
      New connections: $flatten\cpu_I.$1\IBusCachedPlugin_fetchPc_pc[31:0] [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\cpu_I.$procmux$6814:
      Old ports: A=0, B={ \cpu_I.CsrPlugin_mtvec_base 2'00 }, Y=$flatten\cpu_I.$1\CsrPlugin_jumpInterface_payload[31:0]
      New ports: A=30'000000000000000000000000000000, B=\cpu_I.CsrPlugin_mtvec_base, Y=$flatten\cpu_I.$1\CsrPlugin_jumpInterface_payload[31:0] [31:2]
      New connections: $flatten\cpu_I.$1\CsrPlugin_jumpInterface_payload[31:0] [1:0] = 2'00
    Consolidated identical input bits for $mux cell $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3156$2121:
      Old ports: A={ \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [7] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [30:25] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [11:8] 1'0 }, B={ \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [19:12] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [20] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [30:21] 1'0 }, Y={ $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3156$2121_Y [19:2] \cpu_I.IBusCachedPlugin_predictionJumpInterface_payload [1:0] }
      New ports: A={ \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [31] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [7] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [11:8] }, B={ \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [19:12] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [20] \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [24:21] }, Y={ $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3156$2121_Y [19:11] $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3156$2121_Y [4:2] \cpu_I.IBusCachedPlugin_predictionJumpInterface_payload [1] }
      New connections: { $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3156$2121_Y [10:5] \cpu_I.IBusCachedPlugin_predictionJumpInterface_payload [0] } = { \cpu_I.IBusCachedPlugin_cache.io_cpu_fetch_data_regNextWhen [30:25] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3814$2231:
      Old ports: A={ \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [7] \cpu_I.decode_to_execute_INSTRUCTION [30:25] \cpu_I.decode_to_execute_INSTRUCTION [11:8] 1'0 }, B={ \cpu_I.decode_to_execute_INSTRUCTION [19:12] \cpu_I.decode_to_execute_INSTRUCTION [20] \cpu_I.decode_to_execute_INSTRUCTION [30:21] 1'0 }, Y=$flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3814$2231_Y [19:0]
      New ports: A={ \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [7] \cpu_I.decode_to_execute_INSTRUCTION [11:8] }, B={ \cpu_I.decode_to_execute_INSTRUCTION [19:12] \cpu_I.decode_to_execute_INSTRUCTION [20] \cpu_I.decode_to_execute_INSTRUCTION [24:21] }, Y={ $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3814$2231_Y [19:11] $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3814$2231_Y [4:1] }
      New connections: { $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3814$2231_Y [10:5] $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3814$2231_Y [0] } = { \cpu_I.decode_to_execute_INSTRUCTION [30:25] 1'0 }
    New ctrl vector for $pmux cell $flatten\memctrl_I.$procmux$5237: $auto$opt_reduce.cc:134:opt_pmux$22557
    Consolidated identical input bits for $pmux cell $flatten\memctrl_I.$procmux$5499:
      Old ports: A=4'0001, B=8'00001111, Y=$flatten\memctrl_I.$2\phy_io_oe[3:0]
      New ports: A=2'01, B=4'0011, Y=$flatten\memctrl_I.$2\phy_io_oe[3:0] [1:0]
      New connections: $flatten\memctrl_I.$2\phy_io_oe[3:0] [3:2] = { $flatten\memctrl_I.$2\phy_io_oe[3:0] [1] $flatten\memctrl_I.$2\phy_io_oe[3:0] [1] }
    Consolidated identical input bits for $pmux cell $flatten\memctrl_I.$procmux$5629:
      Old ports: A=6'001011, B=36'010011011011111101111111000001000011, Y=$flatten\memctrl_I.$2$mem2reg_rd$\cmd_len_rom$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:570$2988_DATA[5:0]$3069
      New ports: A=4'0101, B=24'100111011110111100000001, Y=$flatten\memctrl_I.$2$mem2reg_rd$\cmd_len_rom$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:570$2988_DATA[5:0]$3069 [4:1]
      New connections: { $flatten\memctrl_I.$2$mem2reg_rd$\cmd_len_rom$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:570$2988_DATA[5:0]$3069 [5] $flatten\memctrl_I.$2$mem2reg_rd$\cmd_len_rom$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:570$2988_DATA[5:0]$3069 [0] } = { $flatten\memctrl_I.$2$mem2reg_rd$\cmd_len_rom$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:570$2988_DATA[5:0]$3069 [2] 1'1 }
    Consolidated identical input bits for $pmux cell $flatten\memctrl_I.$procmux$5652:
      Old ports: A=4'0010, B=12'011010001100, Y={ $flatten\memctrl_I.$2\so_ld_mode[1:0] $flatten\memctrl_I.$2\so_ld_dst[1:0] }
      New ports: A=3'001, B=9'011100110, Y={ $flatten\memctrl_I.$2\so_ld_mode[1:0] $flatten\memctrl_I.$2\so_ld_dst[1:0] [1] }
      New connections: $flatten\memctrl_I.$2\so_ld_dst[1:0] [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\uart_I.\uart_rx_I.\genblk1.gf_I.$procmux$5121:
      Old ports: A=2'00, B=2'11, Y=$flatten\uart_I.\uart_rx_I.\genblk1.gf_I.$2\cnt_move[1:0]
      New ports: A=1'0, B=1'1, Y=$flatten\uart_I.\uart_rx_I.\genblk1.gf_I.$2\cnt_move[1:0] [0]
      New connections: $flatten\uart_I.\uart_rx_I.\genblk1.gf_I.$2\cnt_move[1:0] [1] = $flatten\uart_I.\uart_rx_I.\genblk1.gf_I.$2\cnt_move[1:0] [0]
    Consolidated identical input bits for $mux cell $flatten\uart_I.\uart_tx_I.$procmux$5028:
      Old ports: A={ 1'1 \uart_I.uart_tx_I.shift [9:1] }, B={ 1'1 \uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\uart_I.\uart_tx_I.$0\shift[9:0]
      New ports: A=\uart_I.uart_tx_I.shift [9:1], B={ \uart_I.uart_tx_fifo_I.ram_I.rd_data 1'0 }, Y=$flatten\uart_I.\uart_tx_I.$0\shift[9:0] [8:0]
      New connections: $flatten\uart_I.\uart_tx_I.$0\shift[9:0] [9] = 1'1
    Consolidated identical input bits for $mux cell $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][3][6]$22550:
      Old ports: A=4'1101, B=4'1110, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][3]$a$22530
      New ports: A=2'01, B=2'10, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][3]$a$22530 [1:0]
      New connections: $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][3]$a$22530 [3:2] = 2'11
    Consolidated identical input bits for $mux cell $flatten\vid_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/vid_top.v:236$1634:
      Old ports: A=9'000000000, B=9'101000000, Y=$auto$wreduce.cc:461:run$21690 [8:0]
      New ports: A=1'0, B=1'1, Y=$auto$wreduce.cc:461:run$21690 [6]
      New connections: { $auto$wreduce.cc:461:run$21690 [8:7] $auto$wreduce.cc:461:run$21690 [5:0] } = { $auto$wreduce.cc:461:run$21690 [6] 7'0000000 }
    Consolidated identical input bits for $pmux cell $flatten\vid_I.\tgen_I.$procmux$5069:
      Old ports: A=10'0000000000, B=30'000001111101110111100000001000, Y=$flatten\vid_I.\tgen_I.$2\v_mux[9:0]
      New ports: A=4'0000, B=12'011111100100, Y={ $flatten\vid_I.\tgen_I.$2\v_mux[9:0] [6] $flatten\vid_I.\tgen_I.$2\v_mux[9:0] [3] $flatten\vid_I.\tgen_I.$2\v_mux[9:0] [1:0] }
      New connections: { $flatten\vid_I.\tgen_I.$2\v_mux[9:0] [9:7] $flatten\vid_I.\tgen_I.$2\v_mux[9:0] [5:4] $flatten\vid_I.\tgen_I.$2\v_mux[9:0] [2] } = { 1'0 $flatten\vid_I.\tgen_I.$2\v_mux[9:0] [6] $flatten\vid_I.\tgen_I.$2\v_mux[9:0] [6] 1'0 $flatten\vid_I.\tgen_I.$2\v_mux[9:0] [1] $flatten\vid_I.\tgen_I.$2\v_mux[9:0] [1] }
    Consolidated identical input bits for $pmux cell $flatten\vid_I.\tgen_I.$procmux$5084:
      Old ports: A=11'00001011110, B=33'000001011100100111111000000001110, Y=$flatten\vid_I.\tgen_I.$2\h_mux[10:0]
      New ports: A=3'001, B=9'010111000, Y={ $flatten\vid_I.\tgen_I.$2\h_mux[10:0] [9] $flatten\vid_I.\tgen_I.$2\h_mux[10:0] [5:4] }
      New connections: { $flatten\vid_I.\tgen_I.$2\h_mux[10:0] [10] $flatten\vid_I.\tgen_I.$2\h_mux[10:0] [8:6] $flatten\vid_I.\tgen_I.$2\h_mux[10:0] [3:0] } = { 3'000 $flatten\vid_I.\tgen_I.$2\h_mux[10:0] [4] 4'1110 }
    Consolidated identical input bits for $mux cell $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][3][3]$22541:
      Old ports: A=4'0111, B=4'1000, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][1]$b$22525
      New ports: A=2'01, B=2'10, Y={ $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][1]$b$22525 [3] $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][1]$b$22525 [0] }
      New connections: $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][1]$b$22525 [2:1] = { $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][1]$b$22525 [0] $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][1]$b$22525 [0] }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][3]$22529:
      Old ports: A=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][3]$a$22530, B=4'1111, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][1]$b$22519
      New ports: A=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][3]$a$22530 [1:0], B=2'11, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][1]$b$22519 [1:0]
      New connections: $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][1]$b$22519 [3:2] = 2'11
    Consolidated identical input bits for $mux cell $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$22526:
      Old ports: A=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$a$22527, B=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$b$22528, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][1]$a$22518
      New ports: A={ 1'0 $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$a$22527 [1:0] }, B={ $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$b$22528 [2] $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$b$22528 [0] $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$b$22528 [0] }, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][1]$a$22518 [2:0]
      New connections: $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][1]$a$22518 [3] = 1'1
    Consolidated identical input bits for $mux cell $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$22520:
      Old ports: A=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521, B=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$b$22522, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][0]$a$22515
      New ports: A={ 1'0 $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [1:0] }, B={ $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$b$22522 [2] $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$b$22522 [0] $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$b$22522 [0] }, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][0]$a$22515 [2:0]
      New connections: $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][0]$a$22515 [3] = 1'0
    Consolidated identical input bits for $mux cell $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$22481:
      Old ports: A=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$a$22482, B=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$b$22483, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][1]$a$22473
      New ports: A={ 2'01 $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$a$22482 [1:0] }, B={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$b$22483 [0] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$b$22483 [0] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$b$22483 [0] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][2]$b$22483 [0] }, Y={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][1]$a$22473 [4:3] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][1]$a$22473 [1:0] }
      New connections: $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][1]$a$22473 [2] = 1'0
    Consolidated identical input bits for $mux cell $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$22475:
      Old ports: A=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476, B=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$b$22477, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$a$22470
      New ports: A={ 1'0 $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [1:0] }, B={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$b$22477 [2] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$b$22477 [0] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$b$22477 [0] }, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$a$22470 [2:0]
      New connections: $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$a$22470 [4:3] = { $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$a$22470 [0] 1'0 }
    Consolidated identical input bits for $mux cell $flatten\cpu_I.$procmux$6523:
      Old ports: A={ \cpu_I.decode_to_execute_INSTRUCTION [31] $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3814$2231_Y [19:0] }, B=21'000000000000000000100, Y=$flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20:0]
      New ports: A={ \cpu_I.decode_to_execute_INSTRUCTION [31] $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3814$2231_Y [19:11] \cpu_I.decode_to_execute_INSTRUCTION [30:25] $flatten\cpu_I.$ternary$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:3814$2231_Y [4:1] }, B=20'00000000000000000010, Y=$flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20:1]
      New connections: $flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [0] = 1'0
    Consolidated identical input bits for $mux cell $flatten\cpu_I.$procmux$6529:
      Old ports: A=$flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0], B={ \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31:20] }, Y=\cpu_I.execute_BranchPlugin_branch_src2
      New ports: A=$flatten\cpu_I.$2\execute_BranchPlugin_branch_src2[31:0] [20:0], B={ \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31] \cpu_I.decode_to_execute_INSTRUCTION [31:20] }, Y=\cpu_I.execute_BranchPlugin_branch_src2 [20:0]
      New connections: \cpu_I.execute_BranchPlugin_branch_src2 [31:21] = { \cpu_I.execute_BranchPlugin_branch_src2 [20] \cpu_I.execute_BranchPlugin_branch_src2 [20] \cpu_I.execute_BranchPlugin_branch_src2 [20] \cpu_I.execute_BranchPlugin_branch_src2 [20] \cpu_I.execute_BranchPlugin_branch_src2 [20] \cpu_I.execute_BranchPlugin_branch_src2 [20] \cpu_I.execute_BranchPlugin_branch_src2 [20] \cpu_I.execute_BranchPlugin_branch_src2 [20] \cpu_I.execute_BranchPlugin_branch_src2 [20] \cpu_I.execute_BranchPlugin_branch_src2 [20] \cpu_I.execute_BranchPlugin_branch_src2 [20] }
    Consolidated identical input bits for $mux cell $flatten\memctrl_I.$procmux$5522:
      Old ports: A=4'0000, B=$flatten\memctrl_I.$2\phy_io_oe[3:0], Y=\memctrl_I.phy_io_oe
      New ports: A=2'00, B=$flatten\memctrl_I.$2\phy_io_oe[3:0] [1:0], Y=\memctrl_I.phy_io_oe [1:0]
      New connections: \memctrl_I.phy_io_oe [3:2] = { \memctrl_I.phy_io_oe [1] \memctrl_I.phy_io_oe [1] }
    Consolidated identical input bits for $pmux cell $flatten\memctrl_I.$procmux$5667:
      Old ports: A=$flatten\memctrl_I.$2$mem2reg_rd$\cmd_len_rom$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:570$2988_DATA[5:0]$3069, B=12'000001000011, Y=\memctrl_I.so_ld_cnt
      New ports: A=$flatten\memctrl_I.$2$mem2reg_rd$\cmd_len_rom$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:570$2988_DATA[5:0]$3069 [4:1], B=8'00000001, Y=\memctrl_I.so_ld_cnt [4:1]
      New connections: { \memctrl_I.so_ld_cnt [5] \memctrl_I.so_ld_cnt [0] } = { \memctrl_I.so_ld_cnt [2] 1'1 }
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][1]$22517:
      Old ports: A=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][1]$a$22518, B=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][1]$b$22519, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][0][0]$b$22513
      New ports: A=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][1]$a$22518 [2:0], B={ 1'1 $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][1]$b$22519 [1:0] }, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][0][0]$b$22513 [2:0]
      New connections: $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][0][0]$b$22513 [3] = 1'1
    Consolidated identical input bits for $mux cell $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][1]$22472:
      Old ports: A=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][1]$a$22473, B=5'00000, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][0][0]$b$22468
      New ports: A={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][1]$a$22473 [4:3] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][1]$a$22473 [1:0] }, B=4'0000, Y={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][0][0]$b$22468 [4:3] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][0][0]$b$22468 [1:0] }
      New connections: $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][0][0]$b$22468 [2] = 1'0
  Optimizing cells in module \top.
Performed a total of 46 changes.

63.35.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~33 debug messages>
Removed a total of 11 cells.

63.35.6. Executing OPT_DFF pass (perform DFF optimizations).

63.35.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 1 unused cells and 48 unused wires.
<suppressed ~2 debug messages>

63.35.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6 debug messages>

63.35.9. Rerunning OPT passes. (Maybe there is more to do..)

63.35.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~191 debug messages>

63.35.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$22475:
      Old ports: A={ 1'0 $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [1] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4] }, B={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [1] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4] }, Y={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$a$22470 [2:1] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$a$22470 [4] }
      New ports: A={ 1'0 $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [1] }, B={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [1] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4] }, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$a$22470 [2:1]
      New connections: $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$a$22470 [4] = $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4]
    Consolidated identical input bits for $mux cell $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][1]$22478:
      Old ports: A={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [1] 2'01 $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [1] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4] }, B={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [1] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [1] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4] }, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$b$22471
      New ports: A={ 2'01 $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [1] }, B={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [1] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4] }, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$b$22471 [3:1]
      New connections: { $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$b$22471 [4] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$b$22471 [0] } = { $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [1] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4] }
    Consolidated identical input bits for $mux cell $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][1]$22523:
      Old ports: A={ 2'01 $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [1:0] }, B={ $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [1:0] $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [0] $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [0] }, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][0]$b$22516
      New ports: A={ 2'01 $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [1] }, B={ $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [1:0] $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [0] }, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][0]$b$22516 [3:1]
      New connections: $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][0]$b$22516 [0] = $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [0]
    Consolidated identical input bits for $mux cell $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][2]$22526:
      Old ports: A={ 1'0 $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [1:0] }, B={ $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [1:0] $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [0] }, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][0]$a$22515 [2:0]
      New ports: A={ 1'0 $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [1] }, B=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [1:0], Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][0]$a$22515 [2:1]
      New connections: $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][0]$a$22515 [0] = $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [0]
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$22469:
      Old ports: A={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$a$22470 [4] 1'0 $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$a$22470 [2:1] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$a$22470 [4] }, B=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$b$22471, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][0][0]$a$22467
      New ports: A={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4] 1'0 $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$a$22470 [2:1] }, B={ $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [1] $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][1][0]$b$22471 [3:1] }, Y=$memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][0][0]$a$22467 [4:1]
      New connections: $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][0][0]$a$22467 [0] = $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][2][0]$a$22476 [4]
    Consolidated identical input bits for $mux cell $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][0]$22514:
      Old ports: A={ 1'0 $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][0]$a$22515 [2:0] }, B=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][0]$b$22516, Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][0][0]$a$22512
      New ports: A={ 1'0 $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][0]$a$22515 [2:1] }, B=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][1][0]$b$22516 [3:1], Y=$memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][0][0]$a$22512 [3:1]
      New connections: $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][0][0]$a$22512 [0] = $memory\sys_mgr_I.crg_I.rst_cnt_nxt$rdmux[0][2][0]$a$22521 [0]
  Optimizing cells in module \top.
Performed a total of 6 changes.

63.35.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.35.13. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$22455 ($dffe) from module top (D = 1'x, Q = \memctrl_I.so_cnt [0], rval = 1'1).
Adding SRST signal on $$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdreg[0] ($sdffce) from module top (D = $memory$flatten\vid_I.$auto$proc_rom.cc:155:do_switch$4698$rdmux[0][0][0]$a$22467 [2], Q = \vid_I.pp_yscale_state [2], rval = 1'0).
Setting constant 1-bit at position 9 on $auto$ff.cc:266:slice$21392 ($adffe) from module top.
Setting constant 1-bit at position 0 on $auto$ff.cc:266:slice$22561 ($sdffce) from module top.

63.35.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 3 unused wires.
<suppressed ~1 debug messages>

63.35.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~27 debug messages>

63.35.16. Rerunning OPT passes. (Maybe there is more to do..)

63.35.17. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~192 debug messages>

63.35.18. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
    Consolidated identical input bits for $mux cell $flatten\memctrl_I.$procmux$5528:
      Old ports: A=4'0000, B={ 1'1 $flatten\memctrl_I.$2\phy_clk_o[3:0] [2:0] }, Y=\memctrl_I.phy_clk_o
      New ports: A=3'000, B={ 1'1 $flatten\memctrl_I.$2\phy_clk_o[3:0] [1:0] }, Y=\memctrl_I.phy_clk_o [2:0]
      New connections: \memctrl_I.phy_clk_o [3] = \memctrl_I.phy_clk_o [2]
  Optimizing cells in module \top.
Performed a total of 1 changes.

63.35.19. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~8 debug messages>
Removed a total of 2 cells.

63.35.20. Executing OPT_DFF pass (perform DFF optimizations).

63.35.21. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 22 unused wires.
<suppressed ~1 debug messages>

63.35.22. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.35.23. Rerunning OPT passes. (Maybe there is more to do..)

63.35.24. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
Removed 0 multiplexer ports.
<suppressed ~192 debug messages>

63.35.25. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

63.35.26. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.35.27. Executing OPT_DFF pass (perform DFF optimizations).

63.35.28. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.35.29. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.35.30. Finished OPT passes. (There is nothing left to do.)

63.36. Executing ICE40_WRAPCARRY pass (wrap carries).

63.37. Executing TECHMAP pass (map to technology primitives).

63.37.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

63.37.2. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/arith_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/arith_map.v' to AST representation.
Generating RTLIL representation for module `\_80_ice40_alu'.
Successfully finished Verilog frontend.

63.37.3. Continuing TECHMAP pass.
Using extmapper simplemap for cells of type $reduce_or.
Using extmapper maccmap for cells of type $macc.
  add { 1'0 \cpu_I.decode_to_execute_RS1 [15:0] } * \cpu_I.execute_MulPlugin_bHigh [16] (17x1 bits, signed)
  add $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.blk.partial[0] [31:16] (16 bits, unsigned)
  packed 1 (1) bits / 1 words into adder tree
  add { 1'0 \cpu_I.decode_to_execute_RS1 [31:16] } * 1'0 (17x1 bits, signed)
  add $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.blk.partial[0] [31:16] (16 bits, unsigned)
Using extmapper simplemap for cells of type $mux.
  add { 1'0 \cpu_I.execute_to_memory_MUL_LL } (33 bits, signed)
  add { \cpu_I.execute_to_memory_MUL_HL 16'0000000000000000 } (50 bits, signed)
  add { \cpu_I.execute_to_memory_MUL_LH 16'0000000000000000 } (50 bits, signed)
Using extmapper simplemap for cells of type $reduce_and.
Using extmapper simplemap for cells of type $ne.
Using extmapper simplemap for cells of type $dffe.
Using extmapper simplemap for cells of type $eq.
Using extmapper simplemap for cells of type $sdffe.
  add { 1'0 \cpu_I.decode_to_execute_RS1 [31:16] } * \cpu_I.execute_MulPlugin_bHigh [16] (17x1 bits, signed)
Using extmapper simplemap for cells of type $logic_not.
Using extmapper simplemap for cells of type $sdff.
  add { \cpu_I.execute_MulPlugin_bHigh [16] \cpu_I.decode_to_execute_RS2 [31:16] } * \cpu_I.execute_MulPlugin_aHigh [16] (17x1 bits, signed)
Using extmapper simplemap for cells of type $dff.
  add { \cpu_I.execute_MulPlugin_bHigh [16] \cpu_I.decode_to_execute_RS2 [31:16] } * 1'0 (17x1 bits, signed)
  add $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2451$1978.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.blk.partial[0] [32:16] (17 bits, signed)
Using extmapper simplemap for cells of type $not.
Using extmapper simplemap for cells of type $reduce_bool.
Using extmapper simplemap for cells of type $and.
Using extmapper simplemap for cells of type $logic_or.
Using extmapper simplemap for cells of type $logic_and.
Using template $paramod$103b4016182df467cceab67bcf3e18e6361ec0fd\_80_ice40_alu for cells of type $alu.
Using template $paramod$ef8fb1849064cca7dc908988762d3374786d9fdb\_80_ice40_alu for cells of type $alu.
Using extmapper simplemap for cells of type $or.
Using extmapper simplemap for cells of type $adffe.
Using template $paramod$8fabc56b80a569262acfc42757a02ca0b8e91278\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $adff.
Using template $paramod$cc1e387d9d5ac1d3f6e6bed180038d9c0ac48d0c\_90_pmux for cells of type $pmux.
Using template $paramod$645fe0cc96ae5edb83bff90cc2c78f4a20ca3e3c\_90_pmux for cells of type $pmux.
Using template $paramod$54d740639e1393b22262823179ff783ea9f17a35\_90_pmux for cells of type $pmux.
Using template $paramod$c5c783b17ab1d780abfad8cfe6563a0a7b47a3b0\_90_pmux for cells of type $pmux.
Using template $paramod$521ce43182eecb9f60c72393a788160d2c356bf5\_90_pmux for cells of type $pmux.
Using extmapper simplemap for cells of type $xor.
Using template $paramod$1eb759649286d7485bd82f4dfc30385bade4b4b3\_80_ice40_alu for cells of type $alu.
Using template $paramod$6a42b6fefed750f8a1c58eab59479d960557103c\_80_ice40_alu for cells of type $alu.
Using template $paramod$403d07c18de10cda2ac652a859c56aea81aaf9b5\_80_ice40_alu for cells of type $alu.
Using template $paramod$3ef7d3dd227da7627a99c5e5a6a4deb817573e39\_80_ice40_alu for cells of type $alu.
Using template $paramod$32efbfac1c4dc57230cf86180788fdfd12e3b511\_80_ice40_alu for cells of type $alu.
Using template $paramod$9e063c849228667263119758c3ef2ce4bde04054\_80_ice40_alu for cells of type $alu.
Using extmapper simplemap for cells of type $sdffce.
Using template $paramod$fbc7873bff55778c0b3173955b7e4bce1d9d6834\_80_ice40_alu for cells of type $alu.
  add $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.blk.last_partial [15:0] (16 bits, signed)
  add $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.blk.last_partial [15:0] (16 bits, unsigned)
  add $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2499$1996.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.sliceA[0].mul.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.blk.partial[0] [31:16] (16 bits, unsigned)
Using template $paramod$constmap:6e3026a439ed4a6e7983ca0e910890cc59b2f7b2$paramod$f244f79b7bd028e965812e6cbb9720dcefdc7dda\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshl.
Using template $paramod$44a13d10af618e7fbe7b9aad2f6151ffcee1e2fa\_80_ice40_alu for cells of type $alu.
  add { 1'0 \cpu_I.decode_to_execute_RS2 [15:0] } * \cpu_I.execute_MulPlugin_aHigh [16] (17x1 bits, signed)
  add $flatten\cpu_I.$mul$/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:2477$1990.genblk1.genblk1.genblk1.genblk1.genblk1.genblk1.blk.partial[0] [32:16] (17 bits, signed)
  packed 1 (1) bits / 1 words into adder tree
Using template $paramod$ba2b8c117ce4915aa78c6334bae512cf5c3ff68e\_80_ice40_alu for cells of type $alu.
Using template $paramod$constmap:87f69c0bea22f84de4bcd0314b57cb19e61b5eb7$paramod$455891ae50d34e43581a517459d55825f76fa58e\_90_shift_ops_shr_shl_sshl_sshr for cells of type $sshr.
Using template $paramod$57f63e8a3282e053be0430389b09fa050ac7dca0\_90_pmux for cells of type $pmux.
Using template $paramod$d629d85c8826a74239b9178d1930215a43b0ceb0\_90_pmux for cells of type $pmux.
Using template $paramod$6df0329addda9228fcc2546de2aaf14ad26c98e1\_80_ice40_alu for cells of type $alu.
Using template $paramod$97565c3687be688407d1272a293bd9d0ae6852dc\_90_pmux for cells of type $pmux.
Using template $paramod$c654a831025ee805eb993d5880de10a3d616cd3b\_90_pmux for cells of type $pmux.
Using template $paramod$78e969f2586efcf3a5b0b0440bcca0db83d5cca2\_80_ice40_alu for cells of type $alu.
Using template $paramod$175e67c02b86e96b1288b9dc100122520d7240d8\_90_alu for cells of type $alu.
Using template $paramod$7e708ae28ab761f11d0fb59d3ffc72f6a4baf5d9\_90_alu for cells of type $alu.
Using template $paramod$2af30114e9bd4ccb04dad757b3f0a8f6bf0615b0\_80_ice40_alu for cells of type $alu.
  add \cpu_I._zz_103_ (32 bits, signed)
  add { 1'0 \cpu_I.decode_to_execute_SRC_USE_SUB_LESS } (2 bits, signed)
  add \cpu_I._zz_245_ (32 bits, signed)
  packed 1 (1) bits / 1 words into adder tree
Using template $paramod$85df5dc01c7df96a7d8e5f1fdf76ce9ac452af63\_90_pmux for cells of type $pmux.
Using template $paramod$a13703aa027da371a1931fc542d213d7de559b19\_90_pmux for cells of type $pmux.
Using template $paramod$bf2533632d512eac76dd186c0da49367e29b8e98\_90_pmux for cells of type $pmux.
Using template $paramod$b098bc6f249c0ac91c4d6e19d54b23c285914115\_90_pmux for cells of type $pmux.
Using template $paramod$constmap:15e79b306e15a379262200aca23b0d875ae73042$paramod$cedf4aa7cd4baad38a7d2755402136fd292204b2\_90_shift_shiftx for cells of type $shift.
Analyzing pattern of constant bits for this cell:
  Constant input on bit 0 of port A: 1'1
Creating constmapped module `$paramod$constmap:a61ca6c0517c83d96a4aebb151c5b77d0d7b5f1b$paramod$cedf4aa7cd4baad38a7d2755402136fd292204b2\_90_shift_shiftx'.

63.37.81. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$constmap:a61ca6c0517c83d96a4aebb151c5b77d0d7b5f1b$paramod$cedf4aa7cd4baad38a7d2755402136fd292204b2\_90_shift_shiftx..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 2/2 on $mux $procmux$31201.
    dead port 2/2 on $mux $procmux$31195.
Removed 2 multiplexer ports.
<suppressed ~2414 debug messages>

63.37.82. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$constmap:a61ca6c0517c83d96a4aebb151c5b77d0d7b5f1b$paramod$cedf4aa7cd4baad38a7d2755402136fd292204b2\_90_shift_shiftx.
<suppressed ~2 debug messages>
Removed 0 unused cells and 8 unused wires.
Using template $paramod$constmap:a61ca6c0517c83d96a4aebb151c5b77d0d7b5f1b$paramod$cedf4aa7cd4baad38a7d2755402136fd292204b2\_90_shift_shiftx for cells of type $shift.
Using template $paramod$403a3c2fa431a154c52a6a5429d7a6260b5d144f\_80_ice40_alu for cells of type $alu.
Using template $paramod$4598135cf15630e609dba0dc434804e375ac5643\_80_ice40_alu for cells of type $alu.
Using template $paramod$constmap:4a72d14c58177853799461d6d8b69c1e77949e0a$paramod$282e2f6c0b1116d84b8f8102ddacd7ff760b6794\_90_shift_shiftx for cells of type $shiftx.
Analyzing pattern of constant bits for this cell:
  Constant input on bit 0 of port A: 1'1
  Constant input on bit 1 of port A: 1'1
  Constant input on bit 2 of port A: 1'0
  Constant input on bit 3 of port A: 1'1
  Constant input on bit 4 of port A: 1'0
  Constant input on bit 5 of port A: 1'0
  Constant input on bit 6 of port A: 1'0
  Constant input on bit 7 of port A: 1'0
  Constant input on bit 8 of port A: 1'1
  Constant input on bit 9 of port A: 1'1
  Constant input on bit 10 of port A: 1'0
  Constant input on bit 11 of port A: 1'1
  Constant input on bit 12 of port A: 1'0
  Constant input on bit 13 of port A: 1'1
  Constant input on bit 14 of port A: 1'1
  Constant input on bit 15 of port A: 1'1
  Constant input on bit 16 of port A: 1'0
  Constant input on bit 17 of port A: 1'0
  Constant input on bit 18 of port A: 1'0
  Constant input on bit 19 of port A: 1'0
  Constant input on bit 20 of port A: 1'0
  Constant input on bit 21 of port A: 1'0
  Constant input on bit 22 of port A: 1'0
  Constant input on bit 23 of port A: 1'0
  Constant input on bit 24 of port A: 1'0
  Constant input on bit 25 of port A: 1'0
  Constant input on bit 26 of port A: 1'0
  Constant input on bit 27 of port A: 1'0
  Constant input on bit 28 of port A: 1'0
  Constant input on bit 29 of port A: 1'0
  Constant input on bit 30 of port A: 1'0
  Constant input on bit 31 of port A: 1'0
  Constant input on bit 0 of port B: 1'0
  Constant input on bit 1 of port B: 1'0
  Constant input on bit 2 of port B: 1'0
  Constant input on bit 5 of port B: 1'0
Creating constmapped module `$paramod$constmap:3b0683df01c5cef058918510351278881b9fb3fa$paramod$282e2f6c0b1116d84b8f8102ddacd7ff760b6794\_90_shift_shiftx'.

63.37.92. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module $paramod$constmap:3b0683df01c5cef058918510351278881b9fb3fa$paramod$282e2f6c0b1116d84b8f8102ddacd7ff760b6794\_90_shift_shiftx..
  Creating internal representation of mux trees.
  Evaluating internal representation of mux trees.
  Analyzing evaluation results.
    dead port 1/2 on $mux $procmux$31292.
    dead port 1/2 on $mux $procmux$31289.
    dead port 2/2 on $mux $procmux$31289.
    dead port 1/2 on $mux $procmux$31286.
    dead port 1/2 on $mux $procmux$31283.
    dead port 2/2 on $mux $procmux$31283.
    dead port 1/2 on $mux $procmux$31280.
    dead port 1/2 on $mux $procmux$31277.
    dead port 2/2 on $mux $procmux$31277.
    dead port 2/2 on $mux $procmux$31271.
    dead port 2/2 on $mux $procmux$31265.
Removed 11 multiplexer ports.
<suppressed ~266 debug messages>

63.37.93. Executing OPT_EXPR pass (perform const folding).
Optimizing module $paramod$constmap:3b0683df01c5cef058918510351278881b9fb3fa$paramod$282e2f6c0b1116d84b8f8102ddacd7ff760b6794\_90_shift_shiftx.
<suppressed ~3 debug messages>
Removed 0 unused cells and 14 unused wires.
Using template $paramod$constmap:3b0683df01c5cef058918510351278881b9fb3fa$paramod$282e2f6c0b1116d84b8f8102ddacd7ff760b6794\_90_shift_shiftx for cells of type $shiftx.
Using template $paramod$8742280fdebca84e1c87f2a86ed84f62d558f4cc\_80_ice40_alu for cells of type $alu.
Using template $paramod$d4fbf181fbf74ad2c33c84c81168c20bdbe88f93\_80_ice40_alu for cells of type $alu.
Using template $paramod$c2e415ef15bc3ccd2723772353a6b450d3d76206\_90_pmux for cells of type $pmux.
Using template $paramod$484d51534650924b7ed4c69e46eed3a56904771f\_80_ice40_alu for cells of type $alu.
Using template $paramod$c15aee48e26a714a5f3d013cd387ce60c26c192c\_80_ice40_alu for cells of type $alu.
Using template $paramod$dc04b7d98e503a7bab16fce2df70e6e2c5ca34d6\_80_ice40_alu for cells of type $alu.
Using template $paramod$53700bbee849b2010ad0b60a61ccd204a10e24ca\_80_ice40_alu for cells of type $alu.
Using template $paramod$99587ee084ca1d98447afdf42785390b4a3bd9c2\_80_ice40_alu for cells of type $alu.
Using extmapper simplemap for cells of type $pos.
Using template $paramod\_90_lcu_brent_kung\WIDTH=32'00000000000000000000000000000010 for cells of type $lcu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000110100 for cells of type $fa.
Using template $paramod$cc23faa4302ed2a717f4fd0b175ca8ec4dc7bbd3\_80_ice40_alu for cells of type $alu.
Using template $paramod$3bb72ad0665cdca279bbc49ed6a39f403f16497f\_80_ice40_alu for cells of type $alu.
Using template $paramod$12350b8c8422a70d10b7db4eaae1202a7148b784\_80_ice40_alu for cells of type $alu.
Using template $paramod\_90_fa\WIDTH=32'00000000000000000000000000010000 for cells of type $fa.
No more expansions possible.
<suppressed ~1565 debug messages>

63.38. Executing OPT pass (performing simple optimizations).

63.38.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~3426 debug messages>

63.38.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~3045 debug messages>
Removed a total of 1015 cells.

63.38.3. Executing OPT_DFF pass (perform DFF optimizations).
Handling D = Q on $auto$ff.cc:266:slice$31667 ($_SDFFCE_PP0P_) from module top (conecting SRST instead).
Handling D = Q on $auto$ff.cc:266:slice$31668 ($_SDFFCE_PP0P_) from module top (conecting SRST instead).
Handling D = Q on $auto$ff.cc:266:slice$31669 ($_SDFFCE_PP0P_) from module top (conecting SRST instead).
Handling D = Q on $auto$ff.cc:266:slice$31670 ($_SDFFCE_PP0P_) from module top (conecting SRST instead).
Handling D = Q on $auto$ff.cc:266:slice$31671 ($_SDFFCE_PP0P_) from module top (conecting SRST instead).
Handling D = Q on $auto$ff.cc:266:slice$31672 ($_SDFFCE_PP0P_) from module top (conecting SRST instead).
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$31672 ($_DFFE_PP_) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$31671 ($_DFFE_PP_) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$31670 ($_DFFE_PP_) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$31669 ($_DFFE_PP_) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$31668 ($_DFFE_PP_) from module top.
Setting constant 0-bit at position 0 on $auto$ff.cc:266:slice$31667 ($_DFFE_PP_) from module top.

63.38.4. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 888 unused cells and 3444 unused wires.
<suppressed ~893 debug messages>

63.38.5. Rerunning OPT passes. (Removed registers in this run.)

63.38.6. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~10 debug messages>

63.38.7. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.38.8. Executing OPT_DFF pass (perform DFF optimizations).
Adding SRST signal on $auto$ff.cc:266:slice$31688 ($_DFF_P_) from module top (D = $auto$alumacc.cc:485:replace_alu$22037.Y [5], Q = \vid_I.pp_addr_cur_1 [5], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$31687 ($_DFF_P_) from module top (D = $auto$alumacc.cc:485:replace_alu$22037.Y [4], Q = \vid_I.pp_addr_cur_1 [4], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$31686 ($_DFF_P_) from module top (D = $auto$alumacc.cc:485:replace_alu$22037.Y [3], Q = \vid_I.pp_addr_cur_1 [3], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$31685 ($_DFF_P_) from module top (D = $auto$alumacc.cc:485:replace_alu$22037.Y [2], Q = \vid_I.pp_addr_cur_1 [2], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$31684 ($_DFF_P_) from module top (D = $auto$alumacc.cc:485:replace_alu$22037.Y [1], Q = \vid_I.pp_addr_cur_1 [1], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$31683 ($_DFF_P_) from module top (D = $auto$alumacc.cc:485:replace_alu$22037.Y [0], Q = \vid_I.pp_addr_cur_1 [0], rval = 1'0).
Adding SRST signal on $auto$ff.cc:266:slice$30544 ($_DFFE_PP_) from module top (D = $flatten\memctrl_I.$procmux$5681.Y_B [1], Q = \memctrl_I.so_mode [1], rval = 1'1).
Adding SRST signal on $auto$ff.cc:266:slice$30543 ($_DFFE_PP_) from module top (D = $flatten\memctrl_I.$procmux$5681.Y_B [0], Q = \memctrl_I.so_mode [0], rval = 1'1).
Adding SRST signal on $auto$ff.cc:266:slice$30541 ($_DFFE_PP_) from module top (D = \memctrl_I.state [1], Q = \memctrl_I.so_dst [0], rval = 1'0).

63.38.9. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 9 unused cells and 1 unused wires.
<suppressed ~10 debug messages>

63.38.10. Rerunning OPT passes. (Removed registers in this run.)

63.38.11. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.38.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.38.13. Executing OPT_DFF pass (perform DFF optimizations).

63.38.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.38.15. Finished fast OPT passes.

63.39. Executing ICE40_OPT pass (performing simple optimizations).

63.39.1. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[0].carry: CO=\memctrl_I.so_cnt [1]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[10].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [10]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [11]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[12].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [12]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[13].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [13]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[14].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [14]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[15].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [15]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[16].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [16]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[17].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [17]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[18].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [18]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[19].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [19]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[1].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [1]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[20].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [20]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[21].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [21]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[22].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [22]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[23].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [23]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[24].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [24]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[25].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [25]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[26].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [26]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[27].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [27]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[28].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [28]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[29].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [29]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[2].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [2]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[30].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [30]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[3].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [3]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[4].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [4]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[5].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [5]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[6].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [6]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[7].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [7]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[8].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [8]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$21980.slice[9].carry: CO=$auto$alumacc.cc:485:replace_alu$21980.C [9]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22046.slice[0].carry: CO=\cache_I.cnt_ofs [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22106.slice[0].carry: CO=\vid_I.tgen_I.v_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22109.slice[0].carry: CO=\vid_I.tgen_I.h_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22112.slice[0].carry: CO=\cpu_I.CsrPlugin_jumpInterface_valid
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22112.slice[1].carry: CO=$auto$alumacc.cc:485:replace_alu$22112.C [1]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22118.slice[0].carry: CO=\cpu_I.IBusCachedPlugin_cache.lineLoader_wordIndex [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22121.slice[0].carry: CO=\cpu_I.IBusCachedPlugin_cache.lineLoader_flushCounter [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22124.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$22124.BB [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22124.slice[2].carry: CO=$auto$alumacc.cc:485:replace_alu$22124.C [2]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22127.slice[0].carry: CO=$auto$alumacc.cc:485:replace_alu$22127.BB [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22127.slice[2].carry: CO=$auto$alumacc.cc:485:replace_alu$22127.C [2]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22130.slice[0].carry: CO=\memctrl_I.xfer_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22133.slice[0].carry: CO=\memctrl_I.pause_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22136.slice[0].carry: CO=\memctrl_I.so_cnt [2]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22145.slice[0].carry: CO=\uart_I.uart_div [1]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22145.slice[11].carry: CO=$auto$alumacc.cc:485:replace_alu$22145.C [11]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22148.slice[0].carry: CO=\uart_I.uart_rx_I.div_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22151.slice[0].carry: CO=\uart_I.uart_rx_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22157.slice[0].carry: CO=\uart_I.uart_rx_fifo_I.ram_rd_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22163.slice[0].carry: CO=\uart_I.uart_rx_fifo_I.ram_wr_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22166.slice[0].carry: CO=\uart_I.uart_tx_I.div_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22169.slice[0].carry: CO=\uart_I.uart_tx_I.bit_cnt [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22172.slice[0].carry: CO=\uart_I.uart_tx_fifo_I.ram_rd_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$alumacc.cc:485:replace_alu$22178.slice[0].carry: CO=\uart_I.uart_tx_fifo_I.ram_wr_addr [0]
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[0].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[16].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[0].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[0].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$27029.slice[0].carry: CO=1'0

63.39.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~72 debug messages>

63.39.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~93 debug messages>
Removed a total of 31 cells.

63.39.4. Executing OPT_DFF pass (perform DFF optimizations).

63.39.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 5 unused cells and 11 unused wires.
<suppressed ~6 debug messages>

63.39.6. Rerunning OPT passes. (Removed registers in this run.)

63.39.7. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[1].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[1].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[1].carry: CO=1'0

63.39.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~2 debug messages>

63.39.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.10. Executing OPT_DFF pass (perform DFF optimizations).

63.39.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.12. Rerunning OPT passes. (Removed registers in this run.)

63.39.13. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[2].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[2].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[2].carry: CO=1'0

63.39.14. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.15. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.16. Executing OPT_DFF pass (perform DFF optimizations).

63.39.17. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.18. Rerunning OPT passes. (Removed registers in this run.)

63.39.19. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[3].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[3].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[3].carry: CO=1'0

63.39.20. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.21. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.22. Executing OPT_DFF pass (perform DFF optimizations).

63.39.23. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.24. Rerunning OPT passes. (Removed registers in this run.)

63.39.25. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[4].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[4].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[4].carry: CO=1'0

63.39.26. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.27. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.28. Executing OPT_DFF pass (perform DFF optimizations).

63.39.29. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.30. Rerunning OPT passes. (Removed registers in this run.)

63.39.31. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[5].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[5].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[5].carry: CO=1'0

63.39.32. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.33. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.34. Executing OPT_DFF pass (perform DFF optimizations).

63.39.35. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.36. Rerunning OPT passes. (Removed registers in this run.)

63.39.37. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[6].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[6].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[6].carry: CO=1'0

63.39.38. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.39. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.40. Executing OPT_DFF pass (perform DFF optimizations).

63.39.41. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.42. Rerunning OPT passes. (Removed registers in this run.)

63.39.43. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[7].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[7].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[7].carry: CO=1'0

63.39.44. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.45. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.46. Executing OPT_DFF pass (perform DFF optimizations).

63.39.47. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.48. Rerunning OPT passes. (Removed registers in this run.)

63.39.49. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[8].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[8].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[8].carry: CO=1'0

63.39.50. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.51. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.52. Executing OPT_DFF pass (perform DFF optimizations).

63.39.53. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.54. Rerunning OPT passes. (Removed registers in this run.)

63.39.55. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[9].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[9].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[9].carry: CO=1'0

63.39.56. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.57. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.58. Executing OPT_DFF pass (perform DFF optimizations).

63.39.59. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.60. Rerunning OPT passes. (Removed registers in this run.)

63.39.61. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[10].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[10].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[10].carry: CO=1'0

63.39.62. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.63. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.64. Executing OPT_DFF pass (perform DFF optimizations).

63.39.65. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.66. Rerunning OPT passes. (Removed registers in this run.)

63.39.67. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[11].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[11].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[11].carry: CO=1'0

63.39.68. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.69. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.70. Executing OPT_DFF pass (perform DFF optimizations).

63.39.71. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.72. Rerunning OPT passes. (Removed registers in this run.)

63.39.73. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[12].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[12].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[12].carry: CO=1'0

63.39.74. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.75. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.76. Executing OPT_DFF pass (perform DFF optimizations).

63.39.77. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.78. Rerunning OPT passes. (Removed registers in this run.)

63.39.79. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[13].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[13].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[13].carry: CO=1'0

63.39.80. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.81. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.82. Executing OPT_DFF pass (perform DFF optimizations).

63.39.83. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.84. Rerunning OPT passes. (Removed registers in this run.)

63.39.85. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[14].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[14].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[14].carry: CO=1'0

63.39.86. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.87. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.88. Executing OPT_DFF pass (perform DFF optimizations).

63.39.89. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.90. Rerunning OPT passes. (Removed registers in this run.)

63.39.91. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22676.slice[15].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[15].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[15].carry: CO=1'0

63.39.92. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.93. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.94. Executing OPT_DFF pass (perform DFF optimizations).

63.39.95. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

63.39.96. Rerunning OPT passes. (Removed registers in this run.)

63.39.97. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22685.slice[16].carry: CO=1'0
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[16].carry: CO=1'0

63.39.98. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.99. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.100. Executing OPT_DFF pass (perform DFF optimizations).

63.39.101. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

63.39.102. Rerunning OPT passes. (Removed registers in this run.)

63.39.103. Running ICE40 specific optimizations.
Optimized $__ICE40_CARRY_WRAPPER cell back to logic (without SB_CARRY) top.$auto$maccmap.cc:240:synth$22883.slice[17].carry: CO=1'0

63.39.104. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.105. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~6 debug messages>
Removed a total of 2 cells.

63.39.106. Executing OPT_DFF pass (perform DFF optimizations).

63.39.107. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 1 unused wires.
<suppressed ~1 debug messages>

63.39.108. Rerunning OPT passes. (Removed registers in this run.)

63.39.109. Running ICE40 specific optimizations.

63.39.110. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.39.111. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.39.112. Executing OPT_DFF pass (perform DFF optimizations).

63.39.113. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.39.114. Finished OPT passes. (There is nothing left to do.)

63.40. Executing DFFLEGALIZE pass (convert FFs to types supported by the target).

63.41. Executing TECHMAP pass (map to technology primitives).

63.41.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.

63.41.2. Continuing TECHMAP pass.
Using template \$_DFFE_PP_ for cells of type $_DFFE_PP_.
Using template \$_DFF_P_ for cells of type $_DFF_P_.
Using template \$_SDFFCE_PP0P_ for cells of type $_SDFFCE_PP0P_.
Using template \$_DFF_PP0_ for cells of type $_DFF_PP0_.
Using template \$_DFFE_PP0P_ for cells of type $_DFFE_PP0P_.
Using template \$_DFF_PP1_ for cells of type $_DFF_PP1_.
Using template \$_SDFF_PP1_ for cells of type $_SDFF_PP1_.
Using template \$_SDFF_PP0_ for cells of type $_SDFF_PP0_.
Using template \$_SDFFCE_PP1P_ for cells of type $_SDFFCE_PP1P_.
Using template \$_DFFE_PP1P_ for cells of type $_DFFE_PP1P_.
No more expansions possible.
<suppressed ~1957 debug messages>

63.42. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~6 debug messages>

63.43. Executing SIMPLEMAP pass (map simple cells to gate primitives).
Mapping top.$auto$alumacc.cc:485:replace_alu$22046.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22106.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22109.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22118.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22121.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22124.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22124.slice[2].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22127.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22127.slice[2].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22130.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22133.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22136.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22145.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22145.slice[11].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22148.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22151.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22157.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22163.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22166.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22169.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22172.slice[0].carry ($lut).
Mapping top.$auto$alumacc.cc:485:replace_alu$22178.slice[0].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[0].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[10].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[11].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[12].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[13].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[14].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[15].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[16].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[1].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[2].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[3].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[4].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[5].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[6].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[7].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[8].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22676.slice[9].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[0].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[10].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[11].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[12].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[13].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[14].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[15].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[16].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[1].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[2].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[3].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[4].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[5].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[6].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[7].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[8].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22685.slice[9].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[0].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[10].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[11].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[12].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[13].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[14].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[15].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[16].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[1].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[2].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[3].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[4].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[5].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[6].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[7].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[8].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$22883.slice[9].carry ($lut).
Mapping top.$auto$maccmap.cc:240:synth$27029.slice[0].carry ($lut).

63.44. Executing ICE40_OPT pass (performing simple optimizations).

63.44.1. Running ICE40 specific optimizations.

63.44.2. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~1322 debug messages>

63.44.3. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~2082 debug messages>
Removed a total of 694 cells.

63.44.4. Executing OPT_DFF pass (perform DFF optimizations).

63.44.5. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 51 unused cells and 10340 unused wires.
<suppressed ~52 debug messages>

63.44.6. Rerunning OPT passes. (Removed registers in this run.)

63.44.7. Running ICE40 specific optimizations.

63.44.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.44.9. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.44.10. Executing OPT_DFF pass (perform DFF optimizations).

63.44.11. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.44.12. Finished OPT passes. (There is nothing left to do.)

63.45. Executing TECHMAP pass (map to technology primitives).

63.45.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/latches_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/latches_map.v' to AST representation.
Generating RTLIL representation for module `\$_DLATCH_N_'.
Generating RTLIL representation for module `\$_DLATCH_P_'.
Successfully finished Verilog frontend.

63.45.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~4 debug messages>

63.46. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/abc9_model.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ICE40_CARRY_WRAPPER'.
Successfully finished Verilog frontend.

63.47. Executing ABC9 pass.

63.47.1. Executing ABC9_OPS pass (helper functions for ABC9).

63.47.2. Executing ABC9_OPS pass (helper functions for ABC9).

63.47.3. Executing SCC pass (detecting logic loops).
Found 0 SCCs in module top.
Found 0 SCCs.

63.47.4. Executing ABC9_OPS pass (helper functions for ABC9).

63.47.5. Executing PROC pass (convert processes to netlists).

63.47.5.1. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

63.47.5.2. Executing PROC_RMDEAD pass (remove dead branches from decision trees).
Removed a total of 0 dead cases.

63.47.5.3. Executing PROC_PRUNE pass (remove redundant assignments in processes).
Removed 0 redundant assignments.
Promoted 0 assignments to connections.

63.47.5.4. Executing PROC_INIT pass (extract init attributes).

63.47.5.5. Executing PROC_ARST pass (detect async resets in processes).

63.47.5.6. Executing PROC_ROM pass (convert switches to ROMs).
Converted 0 switches.

63.47.5.7. Executing PROC_MUX pass (convert decision trees to multiplexers).

63.47.5.8. Executing PROC_DLATCH pass (convert process syncs to latches).

63.47.5.9. Executing PROC_DFF pass (convert process syncs to FFs).

63.47.5.10. Executing PROC_MEMWR pass (convert process memory writes to cells).

63.47.5.11. Executing PROC_CLEAN pass (remove empty switches from decision trees).
Cleaned up 0 empty switches.

63.47.5.12. Executing OPT_EXPR pass (perform const folding).

63.47.6. Executing TECHMAP pass (map to technology primitives).

63.47.6.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

63.47.6.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~140 debug messages>

63.47.7. Executing OPT pass (performing simple optimizations).

63.47.7.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module SB_DFFER.
Optimizing module SB_DFFR.
Optimizing module SB_DFFS.
Optimizing module SB_DFFES.

63.47.7.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\SB_DFFER'.
Finding identical cells in module `\SB_DFFR'.
Finding identical cells in module `\SB_DFFS'.
Finding identical cells in module `\SB_DFFES'.
Removed a total of 0 cells.

63.47.7.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \SB_DFFER..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \SB_DFFR..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \SB_DFFS..
  Creating internal representation of mux trees.
  No muxes found in this module.
Running muxtree optimizer on module \SB_DFFES..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

63.47.7.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \SB_DFFER.
  Optimizing cells in module \SB_DFFR.
  Optimizing cells in module \SB_DFFS.
  Optimizing cells in module \SB_DFFES.
Performed a total of 0 changes.

63.47.7.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\SB_DFFER'.
Finding identical cells in module `\SB_DFFR'.
Finding identical cells in module `\SB_DFFS'.
Finding identical cells in module `\SB_DFFES'.
Removed a total of 0 cells.

63.47.7.6. Executing OPT_DFF pass (perform DFF optimizations).

63.47.7.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \SB_DFFER..
Finding unused cells or wires in module \SB_DFFR..
Finding unused cells or wires in module \SB_DFFS..
Finding unused cells or wires in module \SB_DFFES..

63.47.7.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module SB_DFFER.
Optimizing module SB_DFFES.
Optimizing module SB_DFFR.
Optimizing module SB_DFFS.

63.47.7.9. Finished OPT passes. (There is nothing left to do.)

63.47.8. Executing TECHMAP pass (map to technology primitives).

63.47.8.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/abc9_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/abc9_map.v' to AST representation.
Successfully finished Verilog frontend.

63.47.8.2. Continuing TECHMAP pass.
Using template SB_DFFR for cells of type SB_DFFR.
Using template SB_DFFS for cells of type SB_DFFS.
Using template SB_DFFER for cells of type SB_DFFER.
Using template SB_DFFES for cells of type SB_DFFES.
No more expansions possible.
<suppressed ~349 debug messages>

63.47.9. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/abc9_model.v
Parsing Verilog input from `/usr/bin/../share/yosys/abc9_model.v' to AST representation.
Generating RTLIL representation for module `$__ABC9_DELAY'.
Generating RTLIL representation for module `$__ABC9_SCC_BREAKER'.
Generating RTLIL representation for module `$__DFF_N__$abc9_flop'.
Generating RTLIL representation for module `$__DFF_P__$abc9_flop'.
Successfully finished Verilog frontend.

63.47.10. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~1665 debug messages>

63.47.11. Executing ABC9_OPS pass (helper functions for ABC9).

63.47.12. Executing ABC9_OPS pass (helper functions for ABC9).
<suppressed ~2 debug messages>

63.47.13. Executing TECHMAP pass (map to technology primitives).

63.47.13.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/techmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/techmap.v' to AST representation.
Generating RTLIL representation for module `\_90_simplemap_bool_ops'.
Generating RTLIL representation for module `\_90_simplemap_reduce_ops'.
Generating RTLIL representation for module `\_90_simplemap_logic_ops'.
Generating RTLIL representation for module `\_90_simplemap_compare_ops'.
Generating RTLIL representation for module `\_90_simplemap_various'.
Generating RTLIL representation for module `\_90_simplemap_registers'.
Generating RTLIL representation for module `\_90_shift_ops_shr_shl_sshl_sshr'.
Generating RTLIL representation for module `\_90_shift_shiftx'.
Generating RTLIL representation for module `\_90_fa'.
Generating RTLIL representation for module `\_90_lcu_brent_kung'.
Generating RTLIL representation for module `\_90_alu'.
Generating RTLIL representation for module `\_90_macc'.
Generating RTLIL representation for module `\_90_alumacc'.
Generating RTLIL representation for module `\$__div_mod_u'.
Generating RTLIL representation for module `\$__div_mod_trunc'.
Generating RTLIL representation for module `\_90_div'.
Generating RTLIL representation for module `\_90_mod'.
Generating RTLIL representation for module `\$__div_mod_floor'.
Generating RTLIL representation for module `\_90_divfloor'.
Generating RTLIL representation for module `\_90_modfloor'.
Generating RTLIL representation for module `\_90_pow'.
Generating RTLIL representation for module `\_90_pmux'.
Generating RTLIL representation for module `\_90_demux'.
Generating RTLIL representation for module `\_90_lut'.
Successfully finished Verilog frontend.

63.47.13.2. Continuing TECHMAP pass.
Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1.
Using template $paramod\SB_LUT4\LUT_INIT=16'0110100110010110 for cells of type SB_LUT4.
Using template SB_CARRY for cells of type SB_CARRY.
Using extmapper simplemap for cells of type $logic_or.
Using extmapper simplemap for cells of type $logic_and.
Using extmapper simplemap for cells of type $mux.
No more expansions possible.
<suppressed ~171 debug messages>

63.47.14. Executing OPT pass (performing simple optimizations).

63.47.14.1. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.
<suppressed ~4 debug messages>

63.47.14.2. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
<suppressed ~29 debug messages>
Removed a total of 12 cells.

63.47.14.3. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

63.47.14.4. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

63.47.14.5. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.47.14.6. Executing OPT_DFF pass (perform DFF optimizations).

63.47.14.7. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..
Removed 0 unused cells and 24 unused wires.
<suppressed ~1 debug messages>

63.47.14.8. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.47.14.9. Rerunning OPT passes. (Maybe there is more to do..)

63.47.14.10. Executing OPT_MUXTREE pass (detect dead branches in mux trees).
Running muxtree optimizer on module \top..
  Creating internal representation of mux trees.
  No muxes found in this module.
Removed 0 multiplexer ports.

63.47.14.11. Executing OPT_REDUCE pass (consolidate $*mux and $reduce_* inputs).
  Optimizing cells in module \top.
Performed a total of 0 changes.

63.47.14.12. Executing OPT_MERGE pass (detect identical cells).
Finding identical cells in module `\top'.
Removed a total of 0 cells.

63.47.14.13. Executing OPT_DFF pass (perform DFF optimizations).

63.47.14.14. Executing OPT_CLEAN pass (remove unused cells and wires).
Finding unused cells or wires in module \top..

63.47.14.15. Executing OPT_EXPR pass (perform const folding).
Optimizing module top.

63.47.14.16. Finished OPT passes. (There is nothing left to do.)

63.47.15. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 7 cells with 43 new cells, skipped 11 cells.
  replaced 2 cell types:
       2 $_OR_
       5 $_MUX_
  not replaced 3 cell types:
       8 $specify2
       1 $_NOT_
       2 $_AND_

63.47.16. Executing AIGMAP pass (map logic to AIG).
Module top: replaced 4256 cells with 25701 new cells, skipped 7017 cells.
  replaced 5 cell types:
    1358 $_OR_
     237 $_XOR_
       1 $_ANDNOT_
       3 $_ORNOT_
    2657 $_MUX_
  not replaced 47 cell types:
       8 $print
     195 $scopeinfo
     682 $_NOT_
    1359 $_AND_
       1 SB_LEDDA_IP
       1 SB_RGBA_DRV
       4 SB_SPRAM256KA
       2 SB_GB
     651 SB_DFF
     899 SB_DFFE
     178 SB_DFFER
      78 SB_DFFESR
      23 SB_IO
       6 $paramod$ba68a0420314c29d51ab7ddbd2ec9361aa29f018\SB_RAM40_4K
     596 $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1
       1 $paramod$2949a269df5c3db52940b052c0e157bca6914067\SB_RAM40_4K
       1 SB_PLL40_2F_PAD
       1 $paramod$3de16b38bccaf247863fc873bf23c76c0819f04d\SB_RAM40_4K
       8 $paramod$0995edba3b5d39c0753e657c6041e4ce50627dc5\SB_RAM40_4KNW
      24 $paramod\SB_LUT4\LUT_INIT=16'1001000000001001
       8 $paramod\SB_LUT4\LUT_INIT=16'1000000000000000
       6 $paramod$65b9e5893759870fd62e6b87dc6ba151fdc97e95\SB_RAM40_4K
     127 SB_DFFR_$abc9_byp
       2 $paramod\SB_LUT4\LUT_INIT=s32'00000000000000000000010000000000
     178 SB_DFFER_$abc9_byp
      29 SB_DFFS_$abc9_byp
       9 SB_DFFES_$abc9_byp
      93 SB_DFFSR
     127 SB_DFFR
       8 SB_DFFSS
      29 SB_DFFS
       6 SB_DFFESS
       9 SB_DFFES
       4 SB_MAC16
       1 $paramod$7d38eb718a152176365f3bb0cbbaf0f0d310aac5\SB_RAM40_4K
      23 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000011111100
      23 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000010111001
      46 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000111110111
     185 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000001000010010
      80 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000010001111
     368 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000100110001
     253 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000110101000
       4 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000110010100
      56 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000100001100
     368 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000001000000101
     253 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000110000000
       4 $paramod$__ABC9_DELAY\DELAY=32'00000000000000000000000100100001

63.47.16.1. Executing ABC9_OPS pass (helper functions for ABC9).

63.47.16.2. Executing ABC9_OPS pass (helper functions for ABC9).

63.47.16.3. Executing XAIGER backend.
<suppressed ~2521 debug messages>
Extracted 11403 AND gates and 35293 wires from module `top' to a netlist network with 2586 inputs and 3918 outputs.

63.47.16.4. Executing ABC9_EXE pass (technology mapping using ABC9).

63.47.16.5. Executing ABC9.
Running ABC command: "abc" -s -f <abc-temp-dir>/abc.script 2>&1
ABC: ABC command line: "source <abc-temp-dir>/abc.script".
ABC: 
ABC: + read_lut <abc-temp-dir>/input.lut 
ABC: + read_box <abc-temp-dir>/input.box 
ABC: + &read <abc-temp-dir>/input.xaig 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   2586/   3918  and =   10872  lev =   31 (1.52)  mem = 0.35 MB  box = 2602  bb = 2006
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 77 carries.
ABC: + &scorr 
ABC: Warning: The network is combinational.
ABC: + &sweep 
ABC: + &dc2 
ABC: + &dch -f 
ABC: + &ps 
ABC: <abc-temp-dir>/input : i/o =   2586/   3918  and =   14455  lev =   23 (1.14)  mem = 0.40 MB  ch = 2024  box = 2596  bb = 2005
ABC: Warning: AIG with boxes has internal fanout in 0 complex flops and 77 carries.
ABC: + &if -W 750 -v 
ABC: K = 4. Memory (bytes): Truth =    0. Cut =   48. Obj =  128. Set =  528. CutMin = no
ABC: Node =   14455.  Ch =  1902.  Total mem =    4.04 MB. Peak cut mem =    0.17 MB.
ABC: P:  Del = 19951.00.  Ar =    3956.0.  Edge =    13853.  Cut =    83347.  T =     0.02 sec
ABC: P:  Del = 19951.00.  Ar =    3650.0.  Edge =    12984.  Cut =    76430.  T =     0.02 sec
ABC: P:  Del = 19951.00.  Ar =    3312.0.  Edge =    10981.  Cut =    82624.  T =     0.02 sec
ABC: F:  Del = 19951.00.  Ar =    3185.0.  Edge =    10770.  Cut =    84470.  T =     0.02 sec
ABC: A:  Del = 19951.00.  Ar =    3046.0.  Edge =     9664.  Cut =    84597.  T =     0.04 sec
ABC: A:  Del = 19951.00.  Ar =    3044.0.  Edge =     9627.  Cut =    85191.  T =     0.04 sec
ABC: Total time =     0.17 sec
ABC: + &write -n <abc-temp-dir>/output.aig 
ABC: + &mfs 
ABC: abc: src/aig/gia/giaMfs.c:388: Gia_ManInsertMfs: Assertion `iLitNew >= 0' failed.
Warning: ABC: execution of command ""abc" -s -f /tmp/yosys-abc-iC2UQK/abc.script 2>&1" failed: return code 134.

63.47.16.6. Executing AIGER frontend.
<suppressed ~13026 debug messages>
Removed 13836 unused cells and 29052 unused wires.

63.47.16.7. Executing ABC9_OPS pass (helper functions for ABC9).
ABC RESULTS:              $lut cells:     3102
ABC RESULTS:   $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 cells:      591
ABC RESULTS:   \SB_DFFR_$abc9_byp cells:      126
ABC RESULTS:   \SB_DFFER_$abc9_byp cells:      178
ABC RESULTS:   \SB_DFFS_$abc9_byp cells:       29
ABC RESULTS:   \SB_DFFES_$abc9_byp cells:        9
ABC RESULTS:           input signals:      622
ABC RESULTS:          output signals:     2178
Removing temp directory.

63.47.17. Executing TECHMAP pass (map to technology primitives).

63.47.17.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/abc9_unmap.v
Parsing Verilog input from `/usr/bin/../share/yosys/abc9_unmap.v' to AST representation.
Generating RTLIL representation for module `\$__DFF_x__$abc9_flop'.
Generating RTLIL representation for module `\$__ABC9_SCC_BREAKER'.
Successfully finished Verilog frontend.

63.47.17.2. Continuing TECHMAP pass.
Using template $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1 for cells of type $paramod$__ICE40_CARRY_WRAPPER\LUT=16'0110100110010110\I3_IS_CI=1'1.
Using template SB_DFFER_$abc9_byp for cells of type SB_DFFER_$abc9_byp.
Using template SB_DFFR_$abc9_byp for cells of type SB_DFFR_$abc9_byp.
Using template SB_DFFS_$abc9_byp for cells of type SB_DFFS_$abc9_byp.
Using template SB_DFFES_$abc9_byp for cells of type SB_DFFES_$abc9_byp.
Using template $paramod$65b9e5893759870fd62e6b87dc6ba151fdc97e95\SB_RAM40_4K for cells of type $paramod$65b9e5893759870fd62e6b87dc6ba151fdc97e95\SB_RAM40_4K.
Using template $paramod$ba68a0420314c29d51ab7ddbd2ec9361aa29f018\SB_RAM40_4K for cells of type $paramod$ba68a0420314c29d51ab7ddbd2ec9361aa29f018\SB_RAM40_4K.
Using template $paramod$2949a269df5c3db52940b052c0e157bca6914067\SB_RAM40_4K for cells of type $paramod$2949a269df5c3db52940b052c0e157bca6914067\SB_RAM40_4K.
Using template $paramod$0995edba3b5d39c0753e657c6041e4ce50627dc5\SB_RAM40_4KNW for cells of type $paramod$0995edba3b5d39c0753e657c6041e4ce50627dc5\SB_RAM40_4KNW.
Using template $paramod\SB_LUT4\LUT_INIT=16'1001000000001001 for cells of type $paramod\SB_LUT4\LUT_INIT=16'1001000000001001.
Using template $paramod\SB_LUT4\LUT_INIT=16'1000000000000000 for cells of type $paramod\SB_LUT4\LUT_INIT=16'1000000000000000.
Using template $paramod$3de16b38bccaf247863fc873bf23c76c0819f04d\SB_RAM40_4K for cells of type $paramod$3de16b38bccaf247863fc873bf23c76c0819f04d\SB_RAM40_4K.
Using template $paramod$7d38eb718a152176365f3bb0cbbaf0f0d310aac5\SB_RAM40_4K for cells of type $paramod$7d38eb718a152176365f3bb0cbbaf0f0d310aac5\SB_RAM40_4K.
Using template $paramod\SB_LUT4\LUT_INIT=s32'00000000000000000000010000000000 for cells of type $paramod\SB_LUT4\LUT_INIT=s32'00000000000000000000010000000000.
No more expansions possible.
<suppressed ~1009 debug messages>

63.48. Executing ICE40_WRAPCARRY pass (wrap carries).

63.49. Executing TECHMAP pass (map to technology primitives).

63.49.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/ff_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/ff_map.v' to AST representation.
Generating RTLIL representation for module `\$_DFF_N_'.
Generating RTLIL representation for module `\$_DFF_P_'.
Generating RTLIL representation for module `\$_DFFE_NP_'.
Generating RTLIL representation for module `\$_DFFE_PP_'.
Generating RTLIL representation for module `\$_DFF_NP0_'.
Generating RTLIL representation for module `\$_DFF_NP1_'.
Generating RTLIL representation for module `\$_DFF_PP0_'.
Generating RTLIL representation for module `\$_DFF_PP1_'.
Generating RTLIL representation for module `\$_DFFE_NP0P_'.
Generating RTLIL representation for module `\$_DFFE_NP1P_'.
Generating RTLIL representation for module `\$_DFFE_PP0P_'.
Generating RTLIL representation for module `\$_DFFE_PP1P_'.
Generating RTLIL representation for module `\$_SDFF_NP0_'.
Generating RTLIL representation for module `\$_SDFF_NP1_'.
Generating RTLIL representation for module `\$_SDFF_PP0_'.
Generating RTLIL representation for module `\$_SDFF_PP1_'.
Generating RTLIL representation for module `\$_SDFFCE_NP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_NP1P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP0P_'.
Generating RTLIL representation for module `\$_SDFFCE_PP1P_'.
Successfully finished Verilog frontend.

63.49.2. Continuing TECHMAP pass.
No more expansions possible.
<suppressed ~22 debug messages>
Removed 954 unused cells and 44249 unused wires.

63.50. Executing OPT_LUT pass (optimize LUTs).
Discovering LUTs.
Number of LUTs:     3661
  1-LUT               58
  2-LUT              534
  3-LUT             2070
  4-LUT              999
  with \SB_CARRY    (#0)  518
  with \SB_CARRY    (#1)  520

Eliminating LUTs.
Number of LUTs:     3661
  1-LUT               58
  2-LUT              534
  3-LUT             2070
  4-LUT              999
  with \SB_CARRY    (#0)  518
  with \SB_CARRY    (#1)  520

Combining LUTs.
Number of LUTs:     3573
  1-LUT               58
  2-LUT              500
  3-LUT             1940
  4-LUT             1075
  with \SB_CARRY    (#0)  518
  with \SB_CARRY    (#1)  520

Eliminated 0 LUTs.
Combined 88 LUTs.
<suppressed ~19774 debug messages>

63.51. Executing TECHMAP pass (map to technology primitives).

63.51.1. Executing Verilog-2005 frontend: /usr/bin/../share/yosys/ice40/cells_map.v
Parsing Verilog input from `/usr/bin/../share/yosys/ice40/cells_map.v' to AST representation.
Generating RTLIL representation for module `\$lut'.
Successfully finished Verilog frontend.

63.51.2. Continuing TECHMAP pass.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0100 for cells of type $lut.
Using template $paramod$873c285bdccf0ac2b60d2304ea5cd14bf211d2a6\$lut for cells of type $lut.
Using template $paramod$a010528dfa56506a075642ed88f758b6719a77f1\$lut for cells of type $lut.
Using template $paramod$8e44661def013b6bf9fe6f8b049ef2c838d749f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1110 for cells of type $lut.
Using template $paramod$9e354de8d358bf081aa0c089488ea3bc5b7c2fd9\$lut for cells of type $lut.
Using template $paramod$4789582d00084c3344b7a6dacf516efd46244876\$lut for cells of type $lut.
Using template $paramod$8d7a8d6e3356de09670738ba85f2c6b874f6b06d\$lut for cells of type $lut.
Using template $paramod$df196ed0a1da5c4a58c5e08a1dac304fd3fccaab\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01000000 for cells of type $lut.
Using template $paramod$1241d759e3df4cac11dc7c99c36b0d1b07f7a673\$lut for cells of type $lut.
Using template $paramod$c71ed138d834112b80a85f4478e2e21f72e5c48b\$lut for cells of type $lut.
Using template $paramod$b4410865e8124402796f9dfbf73ef8d279fdbd08\$lut for cells of type $lut.
Using template $paramod$59f2a3e232df3029c8bc36978b9bbe72a71dfb5a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1011 for cells of type $lut.
Using template $paramod$fca001e3e0b52158a872e76e56c01ec10dfbb1de\$lut for cells of type $lut.
Using template $paramod$7d35f3eb4056e6484203c99fe42cfcf1dfaba704\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110000 for cells of type $lut.
Using template $paramod$b4f85a6321a00b090afc4e21d68e7b99eb94d149\$lut for cells of type $lut.
Using template $paramod$571404c0889eaf57f492cb5e37f8acb5df5852f9\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000001 for cells of type $lut.
Using template $paramod$8da02996bc6ce025fcc2ce1dafd66f4b38a423f1\$lut for cells of type $lut.
Using template $paramod$f3e1547c4b47e64c590e75cf09078b2507c8cc75\$lut for cells of type $lut.
Using template $paramod$865395c0228487a64a8e4011cecafc2c64b79f2b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0010 for cells of type $lut.
Using template $paramod$cdd0df38422365e6219ff27ee00f3f08c803e942\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1001 for cells of type $lut.
Using template $paramod$272652f6c6fbe9a75eff76e45cc7e2788835518b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000000 for cells of type $lut.
Using template $paramod$52953750219effadf43093a566baf492fdd6b6c8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001100 for cells of type $lut.
Using template $paramod$4b2297966ddb718657b80566604f97685ffc0120\$lut for cells of type $lut.
Using template $paramod$fb5ee0bdef1c4e74aaf1fd8efae98b46a2f5e564\$lut for cells of type $lut.
Using template $paramod$097592bb16245531f0716c5ddb18d7090f9c7d9d\$lut for cells of type $lut.
Using template $paramod$f8f63b209b7230e81958663ff24fef1613156af7\$lut for cells of type $lut.
Using template $paramod$6e46ec5a196ba1a24b8e69ab094cadc07c13ac1f\$lut for cells of type $lut.
Using template $paramod$ead66ba22839f96e739c8f1b5a09bc1717b3be02\$lut for cells of type $lut.
Using template $paramod$3b56205e0e57b3ea26d80fc7983017f83663129e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001111 for cells of type $lut.
Using template $paramod$fd904e9e35cfd343a9df248824bd3f1408724879\$lut for cells of type $lut.
Using template $paramod$7d58cd79f2fe2d2c2cb33a80d00be3f8c42b5e57\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'1101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100000 for cells of type $lut.
Using template $paramod$5dc745bb48e2cf535179547ba13f0fe5364d6d54\$lut for cells of type $lut.
Using template $paramod$3a4f629a30905d3a448d2b9104042184fc100182\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111010 for cells of type $lut.
Using template $paramod$973818279bc95792902f3c09371fd2407d04a2a5\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101100 for cells of type $lut.
Using template $paramod$f9813472aa48e533b3838c6f2316dc2e78c66111\$lut for cells of type $lut.
Using template $paramod$179512a187da069f3b79ef6612a41e494e7d54b6\$lut for cells of type $lut.
Using template $paramod$7d7d10d01ad0b0f84c295373b1fe3864889e6539\$lut for cells of type $lut.
Using template $paramod$47a8214374025465e226fa66bee690ff33268a25\$lut for cells of type $lut.
Using template $paramod$cb3f11b3dc41fb411db0ebc8b103ddb7d046633c\$lut for cells of type $lut.
Using template $paramod$ba7b4568c306470a7f204c239212739869e234a1\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100000 for cells of type $lut.
Using template $paramod$1aac0860da5a035d87455cf51c9a0f07f9d345b6\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111000 for cells of type $lut.
Using template $paramod$b9d8b7e91a2c68da033af948ea0bd8bdebbaf6b2\$lut for cells of type $lut.
Using template $paramod$02fbe8c67d33eabc42a06d471f5fbd85b121dbcc\$lut for cells of type $lut.
Using template $paramod$79b0a1936afde10c31186b63f39698d9b41269bf\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0110 for cells of type $lut.
Using template $paramod$bcd0ec8486cd042d1327ec39d9c0f6f57473bc07\$lut for cells of type $lut.
Using template $paramod$9e45b1a8f5d89c07bcbb75a2bb1c598231b04feb\$lut for cells of type $lut.
Using template $paramod$2ea69c779d6c1b79ac5a87b0d1523c67d5628dba\$lut for cells of type $lut.
Using template $paramod$b27efe94af524608e2c158786bdf6c13e4c8b578\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00100111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100100 for cells of type $lut.
Using template $paramod$4da2968a38813be585b46e20e9ee8670b201e6eb\$lut for cells of type $lut.
Using template $paramod$d980e96aaa8fd1a44dd0a77b7b61a6fcf6e1f9d5\$lut for cells of type $lut.
Using template $paramod$fcff9a7b1687e357a40264efcefe8443c8b2971a\$lut for cells of type $lut.
Using template $paramod$4586fa76bc179636508b7a3d387ddbd6225a9b95\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011011 for cells of type $lut.
Using template $paramod$e6a488add0b5a2d742e2ae29f62ce7616e04271d\$lut for cells of type $lut.
Using template $paramod$a1d323730045824cfc84bb9f4ee8031f1c4dcc9e\$lut for cells of type $lut.
Using template $paramod$a245cf5846ca9615c0f9e135de4c8f203f82e8ac\$lut for cells of type $lut.
Using template $paramod$2955ab75367a3dc9d6f50d3655eebcd4f615031f\$lut for cells of type $lut.
Using template $paramod$5c7d886f3b88971ac55fed4bca034a87bf180f7d\$lut for cells of type $lut.
Using template $paramod$234fd643079033ba0cbc98ff572df9b7b7a0dc86\$lut for cells of type $lut.
Using template $paramod$b27270e54531f78fcd95aa06eed49d923f0efb9f\$lut for cells of type $lut.
Using template $paramod$101238f3d8d49ab12a9b49a2f01cd503b26e9c61\$lut for cells of type $lut.
Using template $paramod$243c00f5eb9faa1d5ce3478fdc389a56070781f8\$lut for cells of type $lut.
Using template $paramod$fbed19fb84ee7c8a884778d28a96daea96245184\$lut for cells of type $lut.
Using template $paramod$ff74d3b36221c7c7b417c242545ab45c7d96a8ff\$lut for cells of type $lut.
Using template $paramod$037be5c00d8a02858cdb1ab049b58a0133287ff1\$lut for cells of type $lut.
Using template $paramod$8494168726d27c2200605afcf1fb7470bf987857\$lut for cells of type $lut.
Using template $paramod$cad45b6c9da81941161a13849773fe2ed4bc1c6f\$lut for cells of type $lut.
Using template $paramod$8614da24b3846fe751594d00fba789cfcb7b874c\$lut for cells of type $lut.
Using template $paramod$b26fbfdb68e98cf016d61a8611b449e9f4a30f3c\$lut for cells of type $lut.
Using template $paramod$62e34d236b5cf9e50e7481784c0097067a15fba4\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110101 for cells of type $lut.
Using template $paramod$8d08395e9a4e4cded27c9198dd6b7fb30a5dc6be\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001101 for cells of type $lut.
Using template $paramod$b2e8d279775d333b39e310bd45fd5952acdde290\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000010\LUT=4'0111 for cells of type $lut.
Using template $paramod$a584b7b837e345f02b84b59cd30fcecc11fb5f26\$lut for cells of type $lut.
Using template $paramod$31bf24a0bd5adeee9622243032714595f96813a2\$lut for cells of type $lut.
Using template $paramod$65d5928f10d93820ad360cabb53aaf31b165496d\$lut for cells of type $lut.
Using template $paramod$53ce561f80f32d4298a3beadc88b6c5c78293221\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101100 for cells of type $lut.
Using template $paramod$6b0849254d6c87461fb93e37cc18f089f61eb912\$lut for cells of type $lut.
Using template $paramod$c6b00b6e5a45587dd2a405086c5dc32a5a05c4c3\$lut for cells of type $lut.
Using template $paramod$e4cede61517c69f4283b34833b70389aba0ba4b3\$lut for cells of type $lut.
Using template $paramod$013e6b6a4353b046ff7459503710c79f47324c2a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000001 for cells of type $lut.
Using template $paramod$4282def8dbd6df3d1248ad282c629bee684502c2\$lut for cells of type $lut.
Using template $paramod$626c926c090c24ceb89df275614206a0a54168a8\$lut for cells of type $lut.
Using template $paramod$5e9374f44a27c3f8a1c38af244ec43ceb4fb8d4f\$lut for cells of type $lut.
Using template $paramod$f82f61ce77e6e9727709cafaabfd337936f75346\$lut for cells of type $lut.
Using template $paramod$25445fb9dd8fc77490980c6bd2e9dbc53c6e84a5\$lut for cells of type $lut.
Using template $paramod$182db0642215a33a838908353a4a183e32659a91\$lut for cells of type $lut.
Using template $paramod$e77dfcebfafd1b28481271247adc84662b57a60b\$lut for cells of type $lut.
Using template $paramod$12d55b60f0f4993cdeef74f2f65f385722841c5f\$lut for cells of type $lut.
Using template $paramod$b2192df6f90569fea4015d0a6658bdc192199f95\$lut for cells of type $lut.
Using template $paramod$29f8e8d81860939642ad82bb36af3cbb544c3dea\$lut for cells of type $lut.
Using template $paramod$5321e04f7ce32c091123c3570ab562efb1c81402\$lut for cells of type $lut.
Using template $paramod$1d0525724ac068b5dfb483a798d6d5f207b20d29\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01011100 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110001 for cells of type $lut.
Using template $paramod$f5f41ee5d60dede31a2b59f58ec46b167939d713\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010111 for cells of type $lut.
Using template $paramod$3331a91b4e24483a258fc0d47474cffbd93ab577\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000110 for cells of type $lut.
Using template $paramod$ce3956c966acb67743cb55a9100788a51ece0f5f\$lut for cells of type $lut.
Using template $paramod$e9c77024ca501b890c641f9c0b10e27242db8730\$lut for cells of type $lut.
Using template $paramod$c558182ca6649a2d62585dbabdcbd4e932559c7e\$lut for cells of type $lut.
Using template $paramod$359fe4e746656bf9c72aecaff84fc7bdea9f55a5\$lut for cells of type $lut.
Using template $paramod$ba7c22fadfbf9ee7abcb895a21403114111dd201\$lut for cells of type $lut.
Using template $paramod$19e5b38cca183d8b6b3a15d20dc995c09cd71893\$lut for cells of type $lut.
Using template $paramod$9ea238b3c4036add2bd96e5aaac8768e1ad77c5a\$lut for cells of type $lut.
Using template $paramod$7fcc2f13195f27c397064377984d87a90c06749d\$lut for cells of type $lut.
Using template $paramod$59848369e5f408d15e0c8c710ff689c98ce02999\$lut for cells of type $lut.
Using template $paramod$1843b3c15f2447d117e2d5de9b00f791ef5f9fa3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110101 for cells of type $lut.
Using template $paramod$480d3b9fc7c6a57575657fd8f0dc2a86c4cc650e\$lut for cells of type $lut.
Using template $paramod$658b9ed803f0d3d335616d3858b53e0a2522f1e8\$lut for cells of type $lut.
Using template $paramod$afceeb21a88aad210a7a4582fbc4377c30be6ab4\$lut for cells of type $lut.
Using template $paramod$39825c5ed3d135e502be79829033166f1762d78b\$lut for cells of type $lut.
Using template $paramod$a4640096cbef09c4ef8613155a589c40164ac034\$lut for cells of type $lut.
Using template $paramod$f9df0bb8fc3cbb332d575e165ec04d3cfd4c90ca\$lut for cells of type $lut.
Using template $paramod$ad3a97108c9f4d10f8acfa309b668b9455d3d733\$lut for cells of type $lut.
Using template $paramod$338ce46cf7ff44b9974887dd2adee6c4e0530bed\$lut for cells of type $lut.
Using template $paramod$c5b694ec89d7629b942ccf6a9be1d39e24f8edec\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010000 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101010 for cells of type $lut.
Using template $paramod$c0db8f8b81aa2496df7fc609f2c3005b47ee2ccd\$lut for cells of type $lut.
Using template $paramod$c5479cb3b02237832e868d4808b3a7f1be08f618\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110010 for cells of type $lut.
Using template $paramod$279a8d961e6b2ded8450bee8ed637cb9efa31f02\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01001111 for cells of type $lut.
Using template $paramod$3a0a392069bc969f34c65c546a8c56fbbb67e282\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100011 for cells of type $lut.
Using template $paramod$d76df6204e5e08a70e04785415e78377888545e3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101010 for cells of type $lut.
Using template $paramod$a3cdc1eb771a2c6a16f64da161e11100ac409d2b\$lut for cells of type $lut.
Using template $paramod$bba54c1ef87367812b4c15f4aed5ac70773df775\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101111 for cells of type $lut.
Using template $paramod$a59b6c8d81194b59764286a4118e90f9abac65dc\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11010001 for cells of type $lut.
Using template $paramod$a03ef989f8f4e1878ce2f5c4e0e3d2dfb54307ef\$lut for cells of type $lut.
Using template $paramod$6b5883288025142ea7fae07f3b28110cd4680dda\$lut for cells of type $lut.
Using template $paramod$2bbec90035bea8ace991b30dd6d61930d1c61b49\$lut for cells of type $lut.
Using template $paramod$46ca4a7f696642c56ce23381d0e2a69ca11e7103\$lut for cells of type $lut.
Using template $paramod$640f0b255c4baeb1d5ed3ee07d5b4acf52609838\$lut for cells of type $lut.
Using template $paramod$498daa9936ffa1c0b12d774cacc95a35d14b818e\$lut for cells of type $lut.
Using template $paramod$723be7177967d6866729df0ff463a602326a012e\$lut for cells of type $lut.
Using template $paramod$df6b12cebabc3b2db650658c5e894d03a346e968\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110001 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000001\LUT=2'01 for cells of type $lut.
Using template $paramod$556f1f8248d46fa51b5b76abd5030284b37d6d0e\$lut for cells of type $lut.
Using template $paramod$46df0bdce53054d48e1bf3b89777e624402baad3\$lut for cells of type $lut.
Using template $paramod$18df3812bc12364e5ebcb6c3ed05c0294e4c26fc\$lut for cells of type $lut.
Using template $paramod$728af64da11d42500d51a71dd7007ac25b15b46a\$lut for cells of type $lut.
Using template $paramod$4e79aa6839e287ee36e65fa83c13a532a028e9cd\$lut for cells of type $lut.
Using template $paramod$27dd7ea71d2126c74d85758e5a06b7f432d9242f\$lut for cells of type $lut.
Using template $paramod$c1a19a87ccbbb03d43a72335db63f692ddf82cc1\$lut for cells of type $lut.
Using template $paramod$be48d952fcad8a16b8d84daa4c48a3065f343e5e\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11011100 for cells of type $lut.
Using template $paramod$c2ec04e79a837992e22a44516a441e33767962c2\$lut for cells of type $lut.
Using template $paramod$364c9ffbffac467d60dfec81bba4e18476c15602\$lut for cells of type $lut.
Using template $paramod$bb4fff1cc3b827238aa40993cafede1c5beecbe3\$lut for cells of type $lut.
Using template $paramod$608f40069c27841a5b3bdf03643a34bdc8974072\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11100010 for cells of type $lut.
Using template $paramod$30305e55a780880b9c824fe3509a4d981acb0f2b\$lut for cells of type $lut.
Using template $paramod$2f35f125a78690286f0cd2faecbaee9c64828b65\$lut for cells of type $lut.
Using template $paramod$ea01c267d60de3df2a073e256dd58614b0b52c59\$lut for cells of type $lut.
Using template $paramod$a699ad34be768465e9f62cdbd92e381326cc035a\$lut for cells of type $lut.
Using template $paramod$0f19b1c588a47c675d00132b243b5e3308ffab5d\$lut for cells of type $lut.
Using template $paramod$6e4a86e6f1a5dc8f826898a131e83cdba4a4fc9e\$lut for cells of type $lut.
Using template $paramod$6e238df02989b317f10820a22773676e71120644\$lut for cells of type $lut.
Using template $paramod$619b7c9a4d44585e10b42f7fb79b16304cca97c5\$lut for cells of type $lut.
Using template $paramod$e51a8a571bee774247b38f52d6e85fd62ae52cea\$lut for cells of type $lut.
Using template $paramod$70030fad4752898f91dbdc976f7643d169393c6b\$lut for cells of type $lut.
Using template $paramod$e5cad3f70ef8abd514139dd032da350013fc446a\$lut for cells of type $lut.
Using template $paramod$a0aea495a7ec615204e185eb69340453c5633d1c\$lut for cells of type $lut.
Using template $paramod$068092ddede495d8462ffe530e6d91711913edbc\$lut for cells of type $lut.
Using template $paramod$d21d214a5aa271f2d9da3f90f22432c0ecee130f\$lut for cells of type $lut.
Using template $paramod$02750f8d568bd99efbda01449a05e084a3143ca8\$lut for cells of type $lut.
Using template $paramod$9fcf2314b06bf8475a41a06506d87acad1afbbaf\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00010101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00011101 for cells of type $lut.
Using template $paramod$e2d96f36ef28053ecd27167cd95b944485ac3146\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001101 for cells of type $lut.
Using template $paramod$1bb2fc47b457abe7e28b98cfa3441b6432237f90\$lut for cells of type $lut.
Using template $paramod$270f983928553715955cf08a11086b798a43d244\$lut for cells of type $lut.
Using template $paramod$c3eebc324c24bdb439fa93c1973646b7d6c15a01\$lut for cells of type $lut.
Using template $paramod$fcdc75950e9c9127acf485657090feabcdb3115f\$lut for cells of type $lut.
Using template $paramod$b600d182ae966d09f33a746441e104587fe7a58f\$lut for cells of type $lut.
Using template $paramod$f6718da5409ec8636fab31113c774a3123f56b0b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11101000 for cells of type $lut.
Using template $paramod$e2abc3b706ab86fd7c0d14a17f66f1e597465517\$lut for cells of type $lut.
Using template $paramod$42c7f7e0577b90a637faf761b61988640dc1e9f6\$lut for cells of type $lut.
Using template $paramod$a642d9cfd5ba13532c60b90e27156eef10bdd135\$lut for cells of type $lut.
Using template $paramod$325e90edf97670f9dea57833ae1f51a5e8bcddea\$lut for cells of type $lut.
Using template $paramod$9238b4f918408168668f80b2f347ff8fe515d0e4\$lut for cells of type $lut.
Using template $paramod$6d6beead1425af15cf78b27fd9b11b41b5d4bce8\$lut for cells of type $lut.
Using template $paramod$35369ee2661bc6f22afa7fd33e082ebba93672ba\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100110 for cells of type $lut.
Using template $paramod$74190755306950a81a07803293f7549508f6f157\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101110 for cells of type $lut.
Using template $paramod$3f330f3f236f8a0c8630b339a705c122dda8a3af\$lut for cells of type $lut.
Using template $paramod$a555129d1bdb0d7959981d04023ff8433a552b93\$lut for cells of type $lut.
Using template $paramod$6051cc942ebe6def12ad03e74fc57fd19331d317\$lut for cells of type $lut.
Using template $paramod$a5516fc31d1e552de2435200bb732b4d4ad63a9c\$lut for cells of type $lut.
Using template $paramod$95f7039f046b84b6f96cadfc318eec9c1ebbb1a9\$lut for cells of type $lut.
Using template $paramod$30c7bb594369ca20ff4ff844ba6ed3179f45572d\$lut for cells of type $lut.
Using template $paramod$c6a0421f5b5114b68e9782f0585d571421cf8f01\$lut for cells of type $lut.
Using template $paramod$7dc80f6db7113f8d3efb3affd3151d83c6b5c052\$lut for cells of type $lut.
Using template $paramod$92aa09275b3191bf9ceb0407a1940a21ad9187ab\$lut for cells of type $lut.
Using template $paramod$33ccc8f22b89035b8d52d2a174a85382f436cc07\$lut for cells of type $lut.
Using template $paramod$e49f6e3576ef1a6d2f58c54414dbb786af8cc869\$lut for cells of type $lut.
Using template $paramod$3ed438b31cd3dcd93a3c8d3415e659937e220c54\$lut for cells of type $lut.
Using template $paramod$9d65a3530a0c54a9611b149a2a5bd69c99184f7d\$lut for cells of type $lut.
Using template $paramod$992bdc10cff2c6edd722994f0e1044bc863f79f7\$lut for cells of type $lut.
Using template $paramod$a6ef2a845efd4ff0d96bc4fd2f06cc3516fa63ff\$lut for cells of type $lut.
Using template $paramod$da51ef318da4444412f84f5c19623c98c27988e0\$lut for cells of type $lut.
Using template $paramod$09deb89cf77b6e37f6ed7fef8d797dc05c0b2eee\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01101111 for cells of type $lut.
Using template $paramod$5a621b016c894274d07edef48c49b401a15fd796\$lut for cells of type $lut.
Using template $paramod$9d707d218adbd63b6f9a0c79d7ee037306fb6296\$lut for cells of type $lut.
Using template $paramod$ba7f31f246a278c41fa0648a6e0512f63185dec0\$lut for cells of type $lut.
Using template $paramod$a5dd9ee10fc2202a29791f7d68d4afcce241aee5\$lut for cells of type $lut.
Using template $paramod$92c3899764cd8074859d6a5a5b733cffe8a391b3\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01110100 for cells of type $lut.
Using template $paramod$d3a3ddc7575971ca62210d5a8f545d7e1ae72a48\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00101000 for cells of type $lut.
Using template $paramod$22a17f102d8eb29f9e3f67afc5da9acc7c1e8867\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00001011 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10010110 for cells of type $lut.
Using template $paramod$5766b753e513aa2393ffc25ef94ebc79dc098484\$lut for cells of type $lut.
Using template $paramod$232aa2e56e6d9def4d9d4ceb69f9fbf5154e7af6\$lut for cells of type $lut.
Using template $paramod$0fa6c93fee22246f217b8b1fb39f21b5cc1cdd4e\$lut for cells of type $lut.
Using template $paramod$2aa716f9a4c5591c2aa6059f9b8a14d113f28078\$lut for cells of type $lut.
Using template $paramod$90bf02bfbc9ec8907e9d716c05e921b93d4705fd\$lut for cells of type $lut.
Using template $paramod$eeb94fcd8e5392649fe04244642520b1ad9644c4\$lut for cells of type $lut.
Using template $paramod$ab2e45f7a350a5d7d54d88d8019d5256ae32568f\$lut for cells of type $lut.
Using template $paramod$d151c38cd9b2f723ca2e7bae80e30ea6d32d7878\$lut for cells of type $lut.
Using template $paramod$20d76b8deb3530e72461aafa0917e952ed06d0b7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110001 for cells of type $lut.
Using template $paramod$027b71830bd0fbfb04ad11206c5a0de76ed9d3f5\$lut for cells of type $lut.
Using template $paramod$573269cdf5f92479a3d66b4e920186d363a31a37\$lut for cells of type $lut.
Using template $paramod$e8b805c60b05d29dea83383ec9e8df8657d8e0fa\$lut for cells of type $lut.
Using template $paramod$a7c07944e10969b2e1fd563a5b72f89493cb3705\$lut for cells of type $lut.
Using template $paramod$fb2de0338fd9cb56279bec3d2d5d229fcea1942b\$lut for cells of type $lut.
Using template $paramod$703a13a751e631ef123f38f7d2125aeabec0f94c\$lut for cells of type $lut.
Using template $paramod$ec48a966498c043d93f34c3316787ddea9cedda3\$lut for cells of type $lut.
Using template $paramod$6b7c9c56fc2a32a479d463d5f3b0d3f4673b67f1\$lut for cells of type $lut.
Using template $paramod$c796465325e8612408ffd6216ec3001cb65cf6eb\$lut for cells of type $lut.
Using template $paramod$bab0ea0d717fb03593996e2a9f716c39db2520fb\$lut for cells of type $lut.
Using template $paramod$053427f7f5ea07d59a8194fc808f0dbdb8dee48b\$lut for cells of type $lut.
Using template $paramod$e8b1383c6901b56df73ac402d78a5e0a42461be0\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111000 for cells of type $lut.
Using template $paramod$4f8066b1ac1b63eb4f02643acff28e860271e033\$lut for cells of type $lut.
Using template $paramod$3ea5e1aff67d5158d4abe40f7c4e0ca909124912\$lut for cells of type $lut.
Using template $paramod$348e2e3c2386524c4c07656cb22e89d0405fecdc\$lut for cells of type $lut.
Using template $paramod$ff7561cfb7d3ae7112e6974b98c96c3d891737ce\$lut for cells of type $lut.
Using template $paramod$c84fab5e7b37c95087ffba9e140088af3811754c\$lut for cells of type $lut.
Using template $paramod$9ce83c401f07863ef6c07aa36141bf86d010bac8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10111111 for cells of type $lut.
Using template $paramod$1644affdabe7f65febd25ca1c4d1e050be54e54f\$lut for cells of type $lut.
Using template $paramod$a1d56211abfa1aaa7a2cc9b3a3197892923d914b\$lut for cells of type $lut.
Using template $paramod$ee7954db7791f7dba0d0a60c296cfdde356f0714\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110100 for cells of type $lut.
Using template $paramod$fb5496753f4cd235e71c284b2ffee9d41a960ca2\$lut for cells of type $lut.
Using template $paramod$d4fae2c0d9ad2966369cd4e39b81c71bcd1327c9\$lut for cells of type $lut.
Using template $paramod$4cab3b31c601551ff65536bf4f533afa0b2094ee\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010001 for cells of type $lut.
Using template $paramod$c24ed72ebb67e9ead6029e42e909ef7fc0abbb11\$lut for cells of type $lut.
Using template $paramod$0bf8365142e452e4b96ef0dc44149e6371e8cfe3\$lut for cells of type $lut.
Using template $paramod$d8804b47fe6c89d4302d34b95a82bd35efdd4ea0\$lut for cells of type $lut.
Using template $paramod$c28a8b7ce0535d090c4cfb52e9c74affd52b110c\$lut for cells of type $lut.
Using template $paramod$b1680225cc6a5792caa95f54b8b3218fae21705d\$lut for cells of type $lut.
Using template $paramod$b19c924e82e74e12bbbdaf9e71fc6291c87db11e\$lut for cells of type $lut.
Using template $paramod$562f871270d8c7c5695cf742d525d0699e0efdce\$lut for cells of type $lut.
Using template $paramod$d521d1c5bdb026589a8e9968bf0fdc6f35c43580\$lut for cells of type $lut.
Using template $paramod$5fe96f355639de70b97b40ec080e72e3eaec0c04\$lut for cells of type $lut.
Using template $paramod$a670b08a47dd8a34f954c50cd06e9996d77e8467\$lut for cells of type $lut.
Using template $paramod$66caeb00a39d236782a97659e3bd99621b74681b\$lut for cells of type $lut.
Using template $paramod$bd52683f5d7d773e55760c18e3bff8f6a3bc6c6d\$lut for cells of type $lut.
Using template $paramod$2179d3bc72bf0dec4b560f3c7f432f7901bacb58\$lut for cells of type $lut.
Using template $paramod$f28aede8a07a53ff316cc6f8627c7d8a2337a88a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00110010 for cells of type $lut.
Using template $paramod$480273aedff341609bb0d70e79d3d629c4101764\$lut for cells of type $lut.
Using template $paramod$8512f4fb47fa9596f76cdbe5b407a5b54df368e7\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10000100 for cells of type $lut.
Using template $paramod$5183b4454493323aca6310872659274580528fcf\$lut for cells of type $lut.
Using template $paramod$ef23bc364ceee2a8dc5800c611734cfdf1fda657\$lut for cells of type $lut.
Using template $paramod$2d73cf21e7a3b53006ebbae47ecc48e73975ec46\$lut for cells of type $lut.
Using template $paramod$9a6965d4f53d69e345bd8d48283856520a30225e\$lut for cells of type $lut.
Using template $paramod$32ccf65669c41e1e3bce1f16051f6d60ad96a2a0\$lut for cells of type $lut.
Using template $paramod$19451f719aa4a75f15cb977ed4212a1c1a1550e9\$lut for cells of type $lut.
Using template $paramod$d6ca727e39f31d51d29072e0f33aa09c65e37336\$lut for cells of type $lut.
Using template $paramod$20235ca863361fbc253329cfc7eeea38c77404dc\$lut for cells of type $lut.
Using template $paramod$9749a72623ffeb0da03674bad641afecefb354e8\$lut for cells of type $lut.
Using template $paramod$d3ef1e4c51780d0a5425e32110ea022c31c1404f\$lut for cells of type $lut.
Using template $paramod$66658cbed86a8310f9b7ba1190d35eff90ee749b\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'00000111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001110 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10100010 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10001010 for cells of type $lut.
Using template $paramod$ab5c02e04aac2a755a7077d4a47f25280e3bc179\$lut for cells of type $lut.
Using template $paramod$bbb10333e84a7e80f65e1494ebbfbf3f28568fcd\$lut for cells of type $lut.
Using template $paramod$4cf5305612d86489c1a6171729557670bf08582e\$lut for cells of type $lut.
Using template $paramod$fe70bb3280659663b8fa2b45f42fda9ccf4ccfaa\$lut for cells of type $lut.
Using template $paramod$38b3d8f5fe89b555d34f1c064cf7c542780e0b8c\$lut for cells of type $lut.
Using template $paramod$19f568890ed784cb1efc3ce1b67eed20a6c54d9a\$lut for cells of type $lut.
Using template $paramod$f5c5b56521a6811444a94cf8aec11258bf0a108d\$lut for cells of type $lut.
Using template $paramod$6695e6c06e585275b2860979e9fd110a3e22d5f7\$lut for cells of type $lut.
Using template $paramod$54ef21ccddfa27629768f219f304bb4163ac6894\$lut for cells of type $lut.
Using template $paramod$8b24407096beec47292ddeb1567a058197a320b9\$lut for cells of type $lut.
Using template $paramod$b40ed8783cd24943f4c31bddb9063d9895eb569a\$lut for cells of type $lut.
Using template $paramod$0e021b5ab9c9dffe82b887dcb2beb3fac2b87759\$lut for cells of type $lut.
Using template $paramod$b45e5cb971154e30a797eecb0461619c3eeae12d\$lut for cells of type $lut.
Using template $paramod$2af7fd5c408581c2b6e80048f54948ce05a232f8\$lut for cells of type $lut.
Using template $paramod$debd9b669717840687fe3e52f7822c4b59921848\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01100000 for cells of type $lut.
Using template $paramod$8d41622da0aa87c171e3ad24745637a8e540bedc\$lut for cells of type $lut.
Using template $paramod$ec6c71d259df49ae0842190ffaff1179e43a8db4\$lut for cells of type $lut.
Using template $paramod$f54c0ffd7b041ca43eac7710ab19c0666d826c22\$lut for cells of type $lut.
Using template $paramod$22dec7e8c4f4b1c3e62879fa2207e0c39047bbd3\$lut for cells of type $lut.
Using template $paramod$694c95659b447cef99dd4cdbd49b87dfd5f6c806\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01111111 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'01010111 for cells of type $lut.
Using template $paramod$e098d38d00670bf1f66f3fff32b3e8f0f799bc39\$lut for cells of type $lut.
Using template $paramod$b812877c6826ca7c644c48fb02bb69a3ab237674\$lut for cells of type $lut.
Using template $paramod$95437c548840ae5673e70f982edd362a76476eb8\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11110111 for cells of type $lut.
Using template $paramod$7c3833e617307006af30409ed68b65a011a1121e\$lut for cells of type $lut.
Using template $paramod$bdef8a4236b2618ef82ff6d08787d9d3dfc92d2b\$lut for cells of type $lut.
Using template $paramod$95454eff2b0bb0c7425b41d029b34bbd8fbe521a\$lut for cells of type $lut.
Using template $paramod$5f892cbccc8e0b846db30004f6a576906c92120c\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'11111101 for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10110011 for cells of type $lut.
Using template $paramod$9d1915f40715c7f715525567f7dfd63744c26c4a\$lut for cells of type $lut.
Using template $paramod\$lut\WIDTH=32'00000000000000000000000000000011\LUT=8'10101110 for cells of type $lut.
Using template $paramod$d9e869de4ea8677851dc452d380224cee441f821\$lut for cells of type $lut.
Using template $paramod$b4f15f202f50520dbc381cd0880ac94f830f05a8\$lut for cells of type $lut.
No more expansions possible.
<suppressed ~8498 debug messages>
Removed 0 unused cells and 7819 unused wires.

63.52. Executing AUTONAME pass.
Renamed 90530 objects in module top (99 iterations).
<suppressed ~8886 debug messages>

63.53. Executing HIERARCHY pass (managing design hierarchy).

63.53.1. Analyzing design hierarchy..
Top module:  \top

63.53.2. Analyzing design hierarchy..
Top module:  \top
Removed 0 unused modules.
Module top directly or indirectly displays text -> setting "keep" attribute.

63.54. Printing statistics.

=== top ===

   Number of wires:               4977
   Number of wire bits:          26795
   Number of public wires:        4977
   Number of public wire bits:   26795
   Number of ports:                 15
   Number of port bits:             30
   Number of memories:               0
   Number of memory bits:            0
   Number of processes:              0
   Number of cells:               6533
     $print                          8
     $scopeinfo                    195
     SB_CARRY                      552
     SB_DFF                        651
     SB_DFFE                       899
     SB_DFFER                      178
     SB_DFFES                        9
     SB_DFFESR                      78
     SB_DFFESS                       6
     SB_DFFR                       127
     SB_DFFS                        29
     SB_DFFSR                       93
     SB_DFFSS                        8
     SB_GB                           2
     SB_IO                          23
     SB_LEDDA_IP                     1
     SB_LUT4                      3641
     SB_MAC16                        4
     SB_PLL40_2F_PAD                 1
     SB_RAM40_4K                    15
     SB_RAM40_4KNW                   8
     SB_RGBA_DRV                     1
     SB_SPRAM256KA                   4

63.55. Executing CHECK pass (checking for obvious problems).
Checking module top...
Found and reported 0 problems.

63.56. Executing JSON backend.

Warnings: 17 unique messages, 463 total
End of script. Logfile hash: 04a466be93, CPU: user 47.32s system 0.28s, MEM: 153.20 MB peak
Yosys 0.43 (git sha1 ead4718e5, g++ 14.2.1 -march=x86-64 -mtune=generic -O2 -fno-plt -fexceptions -fstack-clash-protection -fcf-protection -fno-omit-frame-pointer -mno-omit-leaf-frame-pointer -ffile-prefix-map=/build/yosys/src=/usr/src/debug/yosys -fPIC -Os)
Time spent: 25% 77x opt_expr (13 sec), 21% 55x opt_clean (11 sec), ...