commit 01b6ac0c7af5b54cbb565fd20eca5777be02c7ef
Author: Jakub Duchniewicz <j.duchniewicz@gmail.com>
Date:   Wed Jan 8 13:52:29 2025 +0100

    Update to build with Systemverilog.
    
    Signed-off-by: Jakub Duchniewicz <j.duchniewicz@gmail.com>

diff --git a/rtl/prims.v b/rtl/prims.v
index 9bc5fbc..df03506 100644
--- a/rtl/prims.v
+++ b/rtl/prims.v
@@ -28,7 +28,7 @@ module lut4_n #(
 	genvar i;
 	generate
 		for (i=0; i<WIDTH; i=i+1)
-		begin : bit
+		begin : gen_bit
 			(* RBEL_X=RBEL_X *)
 			(* RBEL_Y=RBEL_Y+(RBEL_Z+i)>>3 *)
 			(* RBEL_Z=(RBEL_Z+i)&7 *)
@@ -72,7 +72,7 @@ module lut4_carry_n #(
 	genvar i;
 	generate
 		for (i=0; i<WIDTH; i=i+1)
-		begin : bit
+		begin : gen_bit
 			(* RBEL_X=RBEL_X *)
 			(* RBEL_Y=RBEL_Y+(RBEL_Z+i)>>3 *)
 			(* RBEL_Z=(RBEL_Z+i)&7 *)
@@ -114,7 +114,7 @@ module dff_n #(
 	genvar i;
 	generate
 		for (i=0; i<WIDTH; i=i+1)
-		begin : bit
+		begin : gen_bit
 			(* RBEL_X=RBEL_X *)
 			(* RBEL_Y=RBEL_Y+(RBEL_Z+i)>>3 *)
 			(* RBEL_Z=(RBEL_Z+i)&7 *)
@@ -147,7 +147,7 @@ module dffe_n #(
 	genvar i;
 	generate
 		for (i=0; i<WIDTH; i=i+1)
-		begin : bit
+		begin : gen_bit
 			(* RBEL_X=RBEL_X *)
 			(* RBEL_Y=RBEL_Y+((RBEL_Z+i)>>3) *)
 			(* RBEL_Z=(RBEL_Z+i)&7 *)
@@ -183,7 +183,7 @@ module dffer_n #(
 	genvar i;
 	generate
 		for (i=0; i<WIDTH; i=i+1)
-		begin : bit
+		begin : gen_bit
 			if (RSTVAL[i] == 1'b1)
 				(* RBEL_X=RBEL_X *)
 				(* RBEL_Y=RBEL_Y+((RBEL_Z+i)>>3) *)
@@ -234,7 +234,7 @@ module dffesr_n #(
 	genvar i;
 	generate
 		for (i=0; i<WIDTH; i=i+1)
-		begin : bit
+		begin : gen_bit
 			if (RSTVAL[i] == 1'b1)
 				(* RBEL_X=RBEL_X *)
 				(* RBEL_Y=RBEL_Y+((RBEL_Z+i)>>3) *)