/*
 * timer_wb.v
 *
 * vim: ts=4 sw=4
 *
 * Copyright (C) 2025 Krzysztof Skrzynecki, Jakub Duchniewicz <j.duchniewicz@gmail.com>
 * SPDX-License-Identifier: TODO:
 */

`default_nettype none

module timer_wb #(
    parameter DW = 32   // Data width for the Wishbone interface (32 bits)
)(
    input  wire             clk,
    input  wire             rst,
    // Wishbone Interface
    output reg  [DW-1:0]    wb_rdata,
    input  wire             wb_cyc,
    output reg              wb_ack
);

    reg[31:0] cnt;

    always @(posedge clk or posedge rst) begin
        if (rst)
            cnt <= 32'h0;
        else
            cnt <= cnt + 32'h1;
    end

    // Wishbone read logic
    always @(posedge clk) begin
        if (wb_cyc) begin
            wb_ack <= wb_cyc & ~wb_ack;
        end
    end

    assign wb_rdata = cnt;
endmodule