Info: constrained 'spi_sck' to bel 'X24/Y0/io0'
Info: constrained 'spi_io[0]' to bel 'X23/Y0/io0'
Info: constrained 'spi_io[1]' to bel 'X23/Y0/io1'
Info: constrained 'spi_io[2]' to bel 'X18/Y0/io0'
Info: constrained 'spi_io[3]' to bel 'X19/Y0/io0'
Info: constrained 'spi_cs_n[0]' to bel 'X24/Y0/io1'
Info: constrained 'spi_cs_n[1]' to bel 'X13/Y31/io0'
Info: constrained 'hdmi_clk' to bel 'X8/Y31/io1'
Info: constrained 'hdmi_de' to bel 'X16/Y31/io0'
Info: constrained 'hdmi_hsync' to bel 'X16/Y31/io1'
Info: constrained 'hdmi_vsync' to bel 'X17/Y31/io0'
Info: constrained 'hdmi_b[3]' to bel 'X9/Y31/io0'
Info: constrained 'hdmi_b[2]' to bel 'X8/Y31/io0'
Info: constrained 'hdmi_b[1]' to bel 'X9/Y31/io1'
Info: constrained 'hdmi_b[0]' to bel 'X13/Y31/io1'
Info: constrained 'hdmi_g[3]' to bel 'X6/Y0/io0'
Info: constrained 'hdmi_g[2]' to bel 'X5/Y0/io0'
Info: constrained 'hdmi_g[1]' to bel 'X7/Y0/io1'
Info: constrained 'hdmi_g[0]' to bel 'X6/Y0/io1'
Info: constrained 'hdmi_r[3]' to bel 'X9/Y0/io0'
Info: constrained 'hdmi_r[2]' to bel 'X9/Y0/io1'
Info: constrained 'hdmi_r[1]' to bel 'X8/Y0/io0'
Info: constrained 'hdmi_r[0]' to bel 'X7/Y0/io0'
Info: constrained 'uart_rx' to bel 'X13/Y0/io1'
Info: constrained 'uart_tx' to bel 'X15/Y0/io0'
Info: constrained 'clk_in' to bel 'X12/Y31/io1'
Info: constrained 'btn' to bel 'X16/Y0/io0'
Info: constrained 'rgb[0]' to bel 'X4/Y31/io0'
Info: constrained 'rgb[1]' to bel 'X5/Y31/io0'
Info: constrained 'rgb[2]' to bel 'X6/Y31/io0'
Info: constraining clock net 'clk_1x' to 23.29 MHz
Info: constraining clock net 'clk_4x' to 100.70 MHz

Info: Packing constants..
Info: Packing IOs..
Info: spi_cs_n[1] feeds SB_IO phy_I.genblk3.iob_spi_cs_I[1], removing $nextpnr_iobuf spi_cs_n[1].
Info: spi_cs_n[0] feeds SB_IO phy_I.genblk3.iob_spi_cs_I[0], removing $nextpnr_iobuf spi_cs_n[0].
Info: rgb[2] use by SB_RGBA_DRV/SB_RGB_DRV rgb_I.rgb_drv_I, not creating SB_IO
Info: rgb[1] use by SB_RGBA_DRV/SB_RGB_DRV rgb_I.rgb_drv_I, not creating SB_IO
Info: rgb[0] use by SB_RGBA_DRV/SB_RGB_DRV rgb_I.rgb_drv_I, not creating SB_IO
Info: hdmi_vsync feeds SB_IO vid_I.phy_I.iob_hdmi_ctrl_I[1], removing $nextpnr_obuf hdmi_vsync.
Info: hdmi_r[3] feeds SB_IO vid_I.phy_I.iob_hdmi_data_I[11], removing $nextpnr_obuf hdmi_r[3].
Info: hdmi_r[2] feeds SB_IO vid_I.phy_I.iob_hdmi_data_I[10], removing $nextpnr_obuf hdmi_r[2].
Info: hdmi_r[1] feeds SB_IO vid_I.phy_I.iob_hdmi_data_I[9], removing $nextpnr_obuf hdmi_r[1].
Info: hdmi_r[0] feeds SB_IO vid_I.phy_I.iob_hdmi_data_I[8], removing $nextpnr_obuf hdmi_r[0].
Info: hdmi_hsync feeds SB_IO vid_I.phy_I.iob_hdmi_ctrl_I[2], removing $nextpnr_obuf hdmi_hsync.
Info: hdmi_g[3] feeds SB_IO vid_I.phy_I.iob_hdmi_data_I[7], removing $nextpnr_obuf hdmi_g[3].
Info: hdmi_g[2] feeds SB_IO vid_I.phy_I.iob_hdmi_data_I[6], removing $nextpnr_obuf hdmi_g[2].
Info: hdmi_g[1] feeds SB_IO vid_I.phy_I.iob_hdmi_data_I[5], removing $nextpnr_obuf hdmi_g[1].
Info: hdmi_g[0] feeds SB_IO vid_I.phy_I.iob_hdmi_data_I[4], removing $nextpnr_obuf hdmi_g[0].
Info: hdmi_de feeds SB_IO vid_I.phy_I.iob_hdmi_ctrl_I[0], removing $nextpnr_obuf hdmi_de.
Info: hdmi_clk feeds SB_IO vid_I.phy_I.iob_hdmi_clk_I, removing $nextpnr_obuf hdmi_clk.
Info: hdmi_b[3] feeds SB_IO vid_I.phy_I.iob_hdmi_data_I[3], removing $nextpnr_obuf hdmi_b[3].
Info: hdmi_b[2] feeds SB_IO vid_I.phy_I.iob_hdmi_data_I[2], removing $nextpnr_obuf hdmi_b[2].
Info: hdmi_b[1] feeds SB_IO vid_I.phy_I.iob_hdmi_data_I[1], removing $nextpnr_obuf hdmi_b[1].
Info: hdmi_b[0] feeds SB_IO vid_I.phy_I.iob_hdmi_data_I[0], removing $nextpnr_obuf hdmi_b[0].
Info: spi_sck feeds SB_IO phy_I.genblk2.iob_clk_I, removing $nextpnr_iobuf spi_sck.
Info: spi_io[3] feeds SB_IO phy_I.iob_spi_io_I[3], removing $nextpnr_iobuf spi_io[3].
Info: spi_io[2] feeds SB_IO phy_I.iob_spi_io_I[2], removing $nextpnr_iobuf spi_io[2].
Info: spi_io[1] feeds SB_IO phy_I.iob_spi_io_I[1], removing $nextpnr_iobuf spi_io[1].
Info: spi_io[0] feeds SB_IO phy_I.iob_spi_io_I[0], removing $nextpnr_iobuf spi_io[0].
Info: Packing LUT-FFs..
Info:     2643 LCs used as LUT4 only
Info:      998 LCs used as LUT4 and DFF
Info: Packing non-LUT FFs..
Info:     1080 LCs used as DFF only
Info: Packing carries..
Info:        7 LCs used as CARRY only
Info: Packing indirect carry+LUT pairs...
Info:        7 LUTs merged into carry LCs
Info: Packing RAMs..
Info: Placing PLLs..
Info:   constrained PLL 'sys_mgr_I.pll_I' to X12/Y31/pll_3
Info: Packing special functions..
Info:   constrained SB_RGBA_DRV 'rgb_I.rgb_drv_I' to X0/Y30/rgba_drv_0
Info:   constrained SB_LEDDA_IP 'rgb_I.led_I' to X0/Y31/ledda_ip_2
Info: Packing PLLs..
Info:   PLL 'sys_mgr_I.pll_I' has LOCK output, need to pass all outputs via LUT
Info:   constrained 'sys_mgr_I.crg_I.pll_lock_SB_LUT4_I3_LC' to X1/Y30/lc0
Info: Promoting globals..
Info: promoting cpu_I.decode_to_execute_IS_DIV_SB_LUT4_I2_O_SB_LUT4_I2_O_SB_LUT4_O_9_I2_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_O[2] [reset] (fanout 33)
Info: promoting memctrl_I.wb_cyc_SB_LUT4_I3_O_SB_LUT4_I3_O [reset] (fanout 22)
Info: promoting cpu_I.decode_to_execute_MEMORY_ENABLE_SB_LUT4_I0_I3_SB_LUT4_I3_1_O_SB_LUT4_I3_O_SB_LUT4_I3_O_SB_DFFR_D_Q_SB_LUT4_I1_O [cen] (fanout 161)
Info: promoting cpu_I.IBusCachedPlugin_fetchPc_pcRegPropagate [cen] (fanout 119)
Info: promoting cache_bus_I.wb_ack_i_SB_LUT4_I2_O_SB_LUT4_I3_O [cen] (fanout 65)
Info: Constraining chains...
Info:       26 LCs used to legalise carry chains.
Info: Checksum: 0x141aed55

Info: Device utilisation:
Info: 	         ICESTORM_LC:    4752/   5280    90%
Info: 	        ICESTORM_RAM:      23/     30    76%
Info: 	               SB_IO:      27/     96    28%
Info: 	               SB_GB:       8/      8   100%
Info: 	        ICESTORM_PLL:       1/      1   100%
Info: 	         SB_WARMBOOT:       0/      1     0%
Info: 	        ICESTORM_DSP:       4/      8    50%
Info: 	      ICESTORM_HFOSC:       0/      1     0%
Info: 	      ICESTORM_LFOSC:       0/      1     0%
Info: 	              SB_I2C:       0/      2     0%
Info: 	              SB_SPI:       0/      2     0%
Info: 	              IO_I3C:       0/      2     0%
Info: 	         SB_LEDDA_IP:       1/      1   100%
Info: 	         SB_RGBA_DRV:       1/      1   100%
Info: 	      ICESTORM_SPRAM:       4/      4   100%

Info: Placed 166 cells based on constraints.
Info: Creating initial analytic placement for 4078 cells, random placement wirelen = 118835.
Info:     at initial placer iter 0, wirelen = 2768
Info:     at initial placer iter 1, wirelen = 2917
Info:     at initial placer iter 2, wirelen = 2933
Info:     at initial placer iter 3, wirelen = 2933
Info: Running main analytical placer, max placement attempts per cell = 2905255.
Info:     at iteration #1, type ALL: wirelen solved = 2937, spread = 51169, legal = 56479; time = 0.21s
Info:     at iteration #2, type ALL: wirelen solved = 3782, spread = 48902, legal = 56745; time = 0.26s
Info:     at iteration #3, type ALL: wirelen solved = 4667, spread = 48007, legal = 55169; time = 0.22s
Info:     at iteration #4, type ALL: wirelen solved = 5928, spread = 42741, legal = 51608; time = 0.23s
Info:     at iteration #5, type ALL: wirelen solved = 7207, spread = 39852, legal = 48615; time = 0.23s
Info:     at iteration #6, type ALL: wirelen solved = 8163, spread = 37351, legal = 46373; time = 0.21s
Info:     at iteration #7, type ALL: wirelen solved = 9195, spread = 35612, legal = 43356; time = 0.21s
Info:     at iteration #8, type ALL: wirelen solved = 10319, spread = 34750, legal = 42982; time = 0.19s
Info:     at iteration #9, type ALL: wirelen solved = 10985, spread = 33851, legal = 42255; time = 0.21s
Info:     at iteration #10, type ALL: wirelen solved = 11241, spread = 34186, legal = 41715; time = 0.20s
Info:     at iteration #11, type ALL: wirelen solved = 11825, spread = 33600, legal = 42837; time = 0.21s
Info:     at iteration #12, type ALL: wirelen solved = 12343, spread = 32961, legal = 41620; time = 0.21s
Info:     at iteration #13, type ALL: wirelen solved = 13155, spread = 32890, legal = 42149; time = 0.20s
Info:     at iteration #14, type ALL: wirelen solved = 13372, spread = 32749, legal = 42676; time = 0.21s
Info:     at iteration #15, type ALL: wirelen solved = 14038, spread = 32590, legal = 40111; time = 0.20s
Info:     at iteration #16, type ALL: wirelen solved = 14438, spread = 32378, legal = 40301; time = 0.20s
Info:     at iteration #17, type ALL: wirelen solved = 14960, spread = 32321, legal = 39675; time = 0.20s
Info:     at iteration #18, type ALL: wirelen solved = 15513, spread = 32251, legal = 41169; time = 0.19s
Info:     at iteration #19, type ALL: wirelen solved = 15712, spread = 32323, legal = 40199; time = 0.20s
Info:     at iteration #20, type ALL: wirelen solved = 15813, spread = 32080, legal = 40527; time = 0.21s
Info:     at iteration #21, type ALL: wirelen solved = 16254, spread = 32382, legal = 40563; time = 0.20s
Info:     at iteration #22, type ALL: wirelen solved = 16468, spread = 31699, legal = 39619; time = 0.18s
Info:     at iteration #23, type ALL: wirelen solved = 16708, spread = 31755, legal = 39610; time = 0.19s
Info:     at iteration #24, type ALL: wirelen solved = 17085, spread = 31750, legal = 38655; time = 0.19s
Info:     at iteration #25, type ALL: wirelen solved = 17247, spread = 31450, legal = 38929; time = 0.19s
Info:     at iteration #26, type ALL: wirelen solved = 17475, spread = 31665, legal = 38888; time = 0.19s
Info:     at iteration #27, type ALL: wirelen solved = 17679, spread = 31585, legal = 40492; time = 0.21s
Info:     at iteration #28, type ALL: wirelen solved = 17827, spread = 32344, legal = 38184; time = 0.19s
Info:     at iteration #29, type ALL: wirelen solved = 17795, spread = 31350, legal = 39624; time = 0.19s
Info:     at iteration #30, type ALL: wirelen solved = 18180, spread = 32659, legal = 40015; time = 0.19s
Info:     at iteration #31, type ALL: wirelen solved = 18469, spread = 32321, legal = 38990; time = 0.19s
Info:     at iteration #32, type ALL: wirelen solved = 18552, spread = 31817, legal = 39920; time = 0.19s
Info:     at iteration #33, type ALL: wirelen solved = 18745, spread = 31677, legal = 37898; time = 0.18s
Info:     at iteration #34, type ALL: wirelen solved = 18949, spread = 32257, legal = 39037; time = 0.20s
Info:     at iteration #35, type ALL: wirelen solved = 19065, spread = 32283, legal = 38482; time = 0.26s
Info:     at iteration #36, type ALL: wirelen solved = 19414, spread = 32046, legal = 39782; time = 0.18s
Info:     at iteration #37, type ALL: wirelen solved = 19486, spread = 32570, legal = 37679; time = 0.18s
Info:     at iteration #38, type ALL: wirelen solved = 19502, spread = 32693, legal = 38542; time = 0.19s
Info:     at iteration #39, type ALL: wirelen solved = 19732, spread = 32683, legal = 40053; time = 0.26s
Info:     at iteration #40, type ALL: wirelen solved = 20142, spread = 32355, legal = 38432; time = 0.18s
Info:     at iteration #41, type ALL: wirelen solved = 20191, spread = 32400, legal = 38449; time = 0.18s
Info:     at iteration #42, type ALL: wirelen solved = 20359, spread = 32721, legal = 39413; time = 0.19s
Info: HeAP Placer Time: 10.85s
Info:   of which solving equations: 4.15s
Info:   of which spreading cells: 0.83s
Info:   of which strict legalisation: 3.68s

Info: Running simulated annealing placer for refinement.
Info:   at iteration #1: temp = 0.000000, timing cost = 2032, wirelen = 37679
Info:   at iteration #5: temp = 0.000000, timing cost = 1553, wirelen = 29523
Info:   at iteration #10: temp = 0.000000, timing cost = 1733, wirelen = 28312
Info:   at iteration #15: temp = 0.000000, timing cost = 1844, wirelen = 27610
Info:   at iteration #20: temp = 0.000000, timing cost = 1799, wirelen = 27213
Info:   at iteration #25: temp = 0.000000, timing cost = 1754, wirelen = 27074
Info:   at iteration #27: temp = 0.000000, timing cost = 1755, wirelen = 27040 
Info: SA placement time 9.96s

Info: Max frequency for clock 'clk_1x': 24.50 MHz (PASS at 23.29 MHz)
Info: Max frequency for clock 'clk_4x': 80.75 MHz (FAIL at 100.70 MHz)

Info: Max delay <async>        -> posedge clk_1x: 2.99 ns
Info: Max delay posedge clk_1x -> <async>       : 5.34 ns
Info: Max delay posedge clk_1x -> posedge clk_4x: 5.20 ns
Info: Max delay posedge clk_4x -> posedge clk_1x: 18.73 ns

Info: Slack histogram:
Info:  legend: * represents 20 endpoint(s)
Info:          + represents [1,20) endpoint(s)
Info: [ -2454,   -340) |+
Info: [  -340,   1774) |+
Info: [  1774,   3888) |***+
Info: [  3888,   6002) |*******+
Info: [  6002,   8116) |*********+
Info: [  8116,  10230) |*******+
Info: [ 10230,  12344) |****+
Info: [ 12344,  14458) |********+
Info: [ 14458,  16572) |**************+
Info: [ 16572,  18686) |***********+
Info: [ 18686,  20800) |******+
Info: [ 20800,  22914) |************+
Info: [ 22914,  25028) |************************+
Info: [ 25028,  27142) |********************+
Info: [ 27142,  29256) |******************+
Info: [ 29256,  31370) |********************+
Info: [ 31370,  33484) |**************+
Info: [ 33484,  35598) |******************************+
Info: [ 35598,  37712) |***************************************+
Info: [ 37712,  39826) |************************************************************ 
Info: Checksum: 0xf8df3b74

Info: Routing..
Info: Setting up routing queue.
Info: Routing 15364 arcs.
Info:            |   (re-)routed arcs  |   delta    | remaining|       time spent     |
Info:    IterCnt |  w/ripup   wo/ripup |  w/r  wo/r |      arcs| batch(sec) total(sec)|
Info:       1000 |       52        947 |   52   947 |     14432|       1.18       1.18|
Info:       2000 |      149       1850 |   97   903 |     13560|       0.43       1.61|
Info:       3000 |      311       2688 |  162   838 |     12807|       0.37       1.99|
Info:       4000 |      466       3505 |  155   817 |     12032|       0.28       2.27|
Info:       5000 |      858       4113 |  392   608 |     11613|       0.42       2.69|
Info:       6000 |     1152       4819 |  294   706 |     11083|       0.46       3.15|
Info:       7000 |     1434       5510 |  282   691 |     10544|       0.40       3.55|
Info:       8000 |     1792       6151 |  358   641 |     10083|       0.47       4.02|
Info:       9000 |     2201       6742 |  409   591 |      9813|       0.54       4.56|
Info:      10000 |     2495       7406 |  294   664 |      9297|       0.37       4.93|
Info:      11000 |     2825       8050 |  330   644 |      8865|       0.38       5.32|
Info:      12000 |     3173       8694 |  348   644 |      8320|       0.36       5.68|
Info:      13000 |     3472       9349 |  299   655 |      7758|       0.31       5.98|
Info:      14000 |     3826       9982 |  354   633 |      7317|       0.43       6.42|
Info:      15000 |     4184      10597 |  358   615 |      6898|       0.38       6.80|
Info:      16000 |     4635      11127 |  451   530 |      6704|       0.57       7.37|
Info:      17000 |     5048      11689 |  413   562 |      6402|       0.51       7.88|
Info:      18000 |     5491      12232 |  443   543 |      6109|       0.54       8.42|
Info:      19000 |     5875      12776 |  384   544 |      5716|       0.54       8.96|
Info:      20000 |     6380      13268 |  505   492 |      5515|       0.57       9.53|
Info:      21000 |     6835      13806 |  455   538 |      5232|       0.54      10.08|
Info:      22000 |     7280      14361 |  445   555 |      4961|       0.55      10.63|
Info:      23000 |     7670      14964 |  390   603 |      4657|       0.51      11.14|
Info:      24000 |     8134      15500 |  464   536 |      4408|       0.60      11.73|
Info:      25000 |     8590      16040 |  456   540 |      4148|       0.51      12.25|
Info:      26000 |     9091      16538 |  501   498 |      3978|       0.63      12.88|
Info:      27000 |     9585      17034 |  494   496 |      3749|       0.56      13.44|
Info:      28000 |    10079      17519 |  494   485 |      3543|       0.60      14.04|
Info:      29000 |    10619      17972 |  540   453 |      3429|       0.65      14.69|
Info:      30000 |    11131      18450 |  512   478 |      3218|       0.59      15.29|
Info:      31000 |    11713      18868 |  582   418 |      3093|       0.65      15.94|
Info:      32000 |    12221      19360 |  508   492 |      2957|       0.61      16.55|
Info:      33000 |    12747      19829 |  526   469 |      2848|       0.66      17.21|
Info:      34000 |    13291      20278 |  544   449 |      2709|       0.69      17.90|
Info:      35000 |    13861      20701 |  570   423 |      2628|       0.73      18.63|
Info:      36000 |    14477      21085 |  616   384 |      2563|       0.73      19.36|
Info:      37000 |    15047      21515 |  570   430 |      2476|       0.67      20.03|
Info:      38000 |    15661      21900 |  614   385 |      2421|       0.66      20.68|
Info:      39000 |    16222      22339 |  561   439 |      2339|       0.63      21.32|
Info:      40000 |    16805      22755 |  583   416 |      2237|       0.77      22.09|
Info:      41000 |    17381      23179 |  576   424 |      2129|       0.70      22.79|
Info:      42000 |    17926      23633 |  545   454 |      2073|       0.85      23.64|
Info:      43000 |    18461      24098 |  535   465 |      1951|       0.69      24.33|
Info:      44000 |    19006      24545 |  545   447 |      1866|       0.62      24.95|
Info:      45000 |    19617      24934 |  611   389 |      1767|       0.70      25.65|
Info:      46000 |    20021      25492 |  404   558 |      1345|       0.59      26.24|
Info:      47000 |    20533      25980 |  512   488 |      1024|       0.47      26.71|
Info:      48000 |    21059      26454 |  526   474 |       902|       0.50      27.21|
Info:      49000 |    21406      27107 |  347   653 |       448|       1.06      28.27|
Info:      50000 |    21803      27710 |  397   603 |        92|       1.07      29.35|
Info:      50781 |    22266      28029 |  463   319 |         0|       0.88      30.22|
Info: Routing complete.
Info: Router1 time 30.22s
Info: Checksum: 0x6dd3b8f9

Info: Critical path report for clock 'clk_1x' (posedge -> posedge):
Info:       type curr  total name
Info:   clk-to-q  1.39  1.39 Source cpu_I.decode_to_execute_RS2_SB_DFFE_Q_21_DFFLC.O
Info:    routing  5.44  6.83 Net cpu_I.decode_to_execute_RS2[10] (5,10) -> (13,23)
Info:                          Sink cpu_I._zz_31__SB_LUT4_O_9_I3_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_LC.I1
Info:                          Defined in:
Info:                               /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:838.45-838.56
Info:      logic  1.23  8.06 Source cpu_I._zz_31__SB_LUT4_O_9_I3_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3_SB_LUT4_O_LC.O
Info:    routing  1.76  9.82 Net cpu_I._zz_31__SB_LUT4_O_9_I3_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_I3[2] (13,23) -> (12,24)
Info:                          Sink cpu_I._zz_31__SB_LUT4_O_9_I3_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_LC.I3
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:      logic  0.87  10.69 Source cpu_I._zz_31__SB_LUT4_O_9_I3_SB_LUT4_O_I2_SB_LUT4_O_I3_SB_LUT4_O_LC.O
Info:    routing  1.76  12.46 Net cpu_I._zz_31__SB_LUT4_O_9_I3_SB_LUT4_O_I2_SB_LUT4_O_I3[1] (12,24) -> (11,24)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_1_I2_SB_LUT4_O_LC.I3
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:      logic  0.87  13.33 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_1_I2_SB_LUT4_O_LC.O
Info:    routing  1.76  15.09 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_1_I2[2] (11,24) -> (10,24)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_1_LC.I2
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:      logic  0.61  15.70 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_1_LC.COUT
Info:    routing  0.00  15.70 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_2_I2[3] (10,24) -> (10,24)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_2_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  15.98 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_2_LC.COUT
Info:    routing  0.00  15.98 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_3_I2[3] (10,24) -> (10,24)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_3_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  16.26 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_3_LC.COUT
Info:    routing  0.00  16.26 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_4_I2[3] (10,24) -> (10,24)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_4_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  16.53 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_4_LC.COUT
Info:    routing  0.00  16.53 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_5_I2[3] (10,24) -> (10,24)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_5_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  16.81 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_5_LC.COUT
Info:    routing  0.56  17.37 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_6_I2[3] (10,24) -> (10,25)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_6_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  17.65 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_6_LC.COUT
Info:    routing  0.00  17.65 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_7_I2[3] (10,25) -> (10,25)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_7_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  17.92 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_7_LC.COUT
Info:    routing  0.00  17.92 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_8_I2[3] (10,25) -> (10,25)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_8_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  18.20 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_8_LC.COUT
Info:    routing  0.00  18.20 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_9_I2[3] (10,25) -> (10,25)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_9_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  18.48 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_9_LC.COUT
Info:    routing  0.00  18.48 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_10_I2[3] (10,25) -> (10,25)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_10_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  18.76 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_10_LC.COUT
Info:    routing  0.00  18.76 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_11_I2[3] (10,25) -> (10,25)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_11_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  19.04 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_11_LC.COUT
Info:    routing  0.00  19.04 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_12_I2[3] (10,25) -> (10,25)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_12_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  19.31 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_12_LC.COUT
Info:    routing  0.00  19.31 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_13_I2[3] (10,25) -> (10,25)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_13_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  19.59 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_13_LC.COUT
Info:    routing  0.56  20.15 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_14_I2[3] (10,25) -> (10,26)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_14_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  20.43 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_14_LC.COUT
Info:    routing  0.00  20.43 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_27_I3_SB_LUT4_O_I2[3] (10,26) -> (10,26)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_27_I3_SB_LUT4_O_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  20.70 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_27_I3_SB_LUT4_O_LC.COUT
Info:    routing  0.00  20.70 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_15_I2[3] (10,26) -> (10,26)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_15_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  20.98 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_15_LC.COUT
Info:    routing  0.00  20.98 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_26_I3_SB_LUT4_O_I2[3] (10,26) -> (10,26)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_26_I3_SB_LUT4_O_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  21.26 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_26_I3_SB_LUT4_O_LC.COUT
Info:    routing  0.00  21.26 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_25_I3_SB_LUT4_O_I2[3] (10,26) -> (10,26)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_25_I3_SB_LUT4_O_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  21.54 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_25_I3_SB_LUT4_O_LC.COUT
Info:    routing  0.00  21.54 Net cpu_I._zz_31__SB_LUT4_O_31_I2_SB_LUT4_O_1_I3_SB_LUT4_O_I2[3] (10,26) -> (10,26)
Info:                          Sink cpu_I._zz_31__SB_LUT4_O_31_I2_SB_LUT4_O_1_I3_SB_LUT4_O_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  21.82 Source cpu_I._zz_31__SB_LUT4_O_31_I2_SB_LUT4_O_1_I3_SB_LUT4_O_LC.COUT
Info:    routing  0.00  21.82 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_24_I3_SB_LUT4_O_I3_SB_CARRY_CO_CI (10,26) -> (10,26)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_24_I3_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:      logic  0.28  22.09 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_24_I3_SB_LUT4_O_I3_SB_CARRY_CO_I1_SB_LUT4_I2_LC.COUT
Info:    routing  0.00  22.09 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_24_I3_SB_LUT4_O_I2[3] (10,26) -> (10,26)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_24_I3_SB_LUT4_O_LC.CIN
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.28  22.37 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_24_I3_SB_LUT4_O_LC.COUT
Info:    routing  1.22  23.59 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_24_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO (10,26) -> (10,27)
Info:                          Sink cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_24_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_LC.I3
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/arith_map.v:62.5-70.4
Info:                               /usr/bin/../share/yosys/ice40/abc9_model.v:4.9-4.11
Info:      logic  0.87  24.46 Source cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_24_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_LC.O
Info:    routing  1.76  26.23 Net cpu_I.execute_SrcPlugin_addSub_SB_LUT4_O_24_I3_SB_LUT4_O_I3_SB_CARRY_CI_CO_SB_LUT4_I3_O[3] (10,27) -> (9,28)
Info:                          Sink cpu_I.decode_to_execute_SRC_LESS_UNSIGNED_SB_LUT4_I1_O_SB_LUT4_O_LC.I3
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:      logic  0.87  27.10 Source cpu_I.decode_to_execute_SRC_LESS_UNSIGNED_SB_LUT4_I1_O_SB_LUT4_O_LC.O
Info:    routing  2.95  30.05 Net cpu_I.decode_to_execute_SRC_LESS_UNSIGNED_SB_LUT4_I1_O[3] (9,28) -> (9,24)
Info:                          Sink cpu_I._zz_280__SB_DFFER_D_Q_SB_LUT4_I2_O_SB_LUT4_O_1_LC.I3
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:      logic  0.87  30.92 Source cpu_I._zz_280__SB_DFFER_D_Q_SB_LUT4_I2_O_SB_LUT4_O_1_LC.O
Info:    routing  1.76  32.69 Net cpu_I._zz_280__SB_DFFER_D_Q_SB_LUT4_I2_O[3] (9,24) -> (8,23)
Info:                          Sink cpu_I._zz_31__SB_LUT4_O_28_LC.I3
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:      logic  0.87  33.56 Source cpu_I._zz_31__SB_LUT4_O_28_LC.O
Info:    routing  3.70  37.26 Net cpu_I._zz_31_[0] (8,23) -> (7,12)
Info:                          Sink cpu_I.decode_RS2_SB_LUT4_O_LC.I3
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:      logic  0.87  38.14 Source cpu_I.decode_RS2_SB_LUT4_O_LC.O
Info:    routing  4.14  42.28 Net cpu_I.decode_RS2[0] (7,12) -> (0,5)
Info:                          Sink cpu_I.execute_to_memory_MUL_LL_SB_MAC16_O_DSP.B_0
Info:                          Defined in:
Info:                               /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/VexRiscv.v:774.23-774.33
Info:      setup  0.10  42.38 Source cpu_I.execute_to_memory_MUL_LL_SB_MAC16_O_DSP.B_0
Info: 15.01 ns logic, 27.37 ns routing

Info: Critical path report for clock 'clk_4x' (posedge -> posedge):
Info:       type curr  total name
Info:   clk-to-q  1.39  1.39 Source sys_mgr_I.crg_I.clk_div_SB_LUT4_I1_LC.O
Info:    routing  2.29  3.68 Net sys_mgr_I.crg_I.clk_div[1] (10,2) -> (12,0)
Info:                          Sink sys_mgr_I.crg_I.gbuf_1x_I.USER_SIGNAL_TO_GLOBAL_BUFFER
Info:                          Defined in:
Info:                               /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:78.15-78.35
Info:                               /usr/bin/../share/yosys/techmap.v:270.23-270.24
Info:      logic  1.59  5.27 Source sys_mgr_I.crg_I.gbuf_1x_I.GLOBAL_BUFFER_OUTPUT
Info:    routing  1.76  7.03 Net clk_1x (12,0) -> (20,4)
Info:                          Sink sys_mgr_I.sync_96m_I.ff_samp0_I.genblk1.genblk1.genblk1.genblk1.genblk1.dff_I_DFFLC.I0
Info:                          Defined in:
Info:                               /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/prims.v:179.14-179.17
Info:      setup  1.23  8.26 Source sys_mgr_I.sync_96m_I.ff_samp0_I.genblk1.genblk1.genblk1.genblk1.genblk1.dff_I_DFFLC.I0
Info: 4.21 ns logic, 4.05 ns routing

Info: Critical path report for cross-domain path '<async>' -> 'posedge clk_1x':
Info:       type curr  total name
Info:     source  0.00  0.00 Source uart_rx$sb_io.D_IN_0
Info:    routing  1.76  1.76 Net uart_rx$SB_IO_IN (13,0) -> (12,1)
Info:                          Sink uart_I.uart_rx_I.genblk1.gf_I.sync_SB_DFF_Q_1_DFFLC.I0
Info:                          Defined in:
Info:                               /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/top.v:28.14-28.21
Info:      setup  1.23  2.99 Source uart_I.uart_rx_I.genblk1.gf_I.sync_SB_DFF_Q_1_DFFLC.I0
Info: 1.23 ns logic, 1.76 ns routing

Info: Critical path report for cross-domain path 'posedge clk_1x' -> '<async>':
Info:       type curr  total name
Info:   clk-to-q  1.39  1.39 Source uart_I.uart_tx_I.go_SB_LUT4_I3_8_LC.O
Info:    routing  5.98  7.37 Net uart_tx$SB_IO_OUT (2,9) -> (15,0)
Info:                          Sink uart_tx$sb_io.D_OUT_0
Info:                          Defined in:
Info:                               /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/projects/riscv_doom/rtl/top.v:29.14-29.21
Info: 1.39 ns logic, 5.98 ns routing

Info: Critical path report for cross-domain path 'posedge clk_1x' -> 'posedge clk_4x':
Info:       type curr  total name
Info:   clk-to-q  1.39  1.39 Source phy_I.bit[1].osd_o_I.genblk1[0].dff_cap_I.genblk1.dff_I_DFFLC.O
Info:    routing  2.41  3.80 Net phy_I.bit[1].osd_o_I.cap_out[0] (24,3) -> (24,1)
Info:                          Sink phy_I.bit[1].osd_o_I.genblk2[0].dff_shift_I.d_SB_LUT4_O_LC.I2
Info:                          Defined in:
Info:                               /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_dff.v:21.14-21.15
Info:      setup  1.15  4.95 Source phy_I.bit[1].osd_o_I.genblk2[0].dff_shift_I.d_SB_LUT4_O_LC.I2
Info: 2.55 ns logic, 2.41 ns routing

Info: Critical path report for cross-domain path 'posedge clk_4x' -> 'posedge clk_1x':
Info:       type curr  total name
Info:   clk-to-q  1.39  1.39 Source sys_mgr_I.crg_I.rst_i_SB_DFFS_Q_D_SB_LUT4_O_LC.O
Info:    routing  2.29  3.68 Net sys_mgr_I.crg_I.rst_i (10,2) -> (13,0)
Info:                          Sink sys_mgr_I.crg_I.gbuf_rst_I.USER_SIGNAL_TO_GLOBAL_BUFFER
Info:                          Defined in:
Info:                               /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2ice40//rtl/ice40_serdes_crg.v:33.13-33.18
Info:      logic  1.59  5.27 Source sys_mgr_I.crg_I.gbuf_rst_I.GLOBAL_BUFFER_OUTPUT
Info:    routing  1.76  7.03 Net rst (13,0) -> (22,15)
Info:                          Sink cache_bus_I.state_SB_DFF_Q_2_D_SB_LUT4_O_I1_SB_LUT4_O_LC.I2
Info:                          Defined in:
Info:                               /home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/prims.v:180.14-180.17
Info:      logic  1.21  8.23 Source cache_bus_I.state_SB_DFF_Q_2_D_SB_LUT4_O_I1_SB_LUT4_O_LC.O
Info:    routing  1.76  10.00 Net cache_bus_I.state_SB_DFF_Q_2_D_SB_LUT4_O_I1[1] (22,15) -> (21,15)
Info:                          Sink cache_bus_I.state_SB_DFF_Q_2_D_SB_LUT4_O_LC.I1
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:      logic  1.23  11.23 Source cache_bus_I.state_SB_DFF_Q_2_D_SB_LUT4_O_LC.O
Info:    routing  1.76  12.99 Net cache_bus_I.state_SB_DFF_Q_2_D[0] (21,15) -> (21,15)
Info:                          Sink cache_bus_I.state_SB_DFF_Q_2_DFFLC.I0
Info:                          Defined in:
Info:                               /usr/bin/../share/yosys/ice40/cells_map.v:6.21-6.22
Info:      setup  1.23  14.22 Source cache_bus_I.state_SB_DFF_Q_2_DFFLC.I0
Info: 6.65 ns logic, 7.57 ns routing

Info: Max frequency for clock 'clk_1x': 23.59 MHz (PASS at 23.29 MHz)
Info: Max frequency for clock 'clk_4x': 121.01 MHz (PASS at 100.70 MHz)

Info: Max delay <async>        -> posedge clk_1x: 2.99 ns
Info: Max delay posedge clk_1x -> <async>       : 7.37 ns
Info: Max delay posedge clk_1x -> posedge clk_4x: 4.95 ns
Info: Max delay posedge clk_4x -> posedge clk_1x: 14.22 ns

Info: Slack histogram:
Info:  legend: * represents 18 endpoint(s)
Info:          + represents [1,18) endpoint(s)
Info: [   560,   2518) |+
Info: [  2518,   4476) |*+
Info: [  4476,   6434) |**********+
Info: [  6434,   8392) |**********+
Info: [  8392,  10350) |****+
Info: [ 10350,  12308) |****+
Info: [ 12308,  14266) |*****************+
Info: [ 14266,  16224) |***********+
Info: [ 16224,  18182) |**************+
Info: [ 18182,  20140) |*******+
Info: [ 20140,  22098) |**********+
Info: [ 22098,  24056) |************************+
Info: [ 24056,  26014) |*******************+
Info: [ 26014,  27972) |*******************+
Info: [ 27972,  29930) |**************+
Info: [ 29930,  31888) |*********************+
Info: [ 31888,  33846) |*****************+
Info: [ 33846,  35804) |********************************+
Info: [ 35804,  37762) |************************************************************ 
Info: [ 37762,  39720) |********************************************************+

Info: Program finished normally.