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"bits": [ "1", "0", "1", "1", "1", "1" ], "attributes": { "hdlname": "memctrl_I cmd_len_rom[8]", "src": "/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:528.12-528.23" } }, "memctrl_I.cmd_len_rom[9]": { "hide_name": 0, "bits": [ "1", "1", "1", "1", "1", "1" ], "attributes": { "hdlname": "memctrl_I cmd_len_rom[9]", "src": "/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2qpimem//rtl/qpi_memctrl.v:528.12-528.23" } }, "memctrl_I.dly_si_dst.clk": { "hide_name": 0, "bits": [ 42 ], "attributes": { "hdlname": "memctrl_I dly_si_dst clk", "src": "/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:52.14-52.17" } }, "memctrl_I.dly_si_dst.d": { "hide_name": 0, "bits": [ 5399, 5397 ], "attributes": { "hdlname": "memctrl_I dly_si_dst d", "src": "/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:50.26-50.27" } }, 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}, "memctrl_I.dly_si_dst.q": { "hide_name": 0, "bits": [ 641, 230 ], "attributes": { "hdlname": "memctrl_I dly_si_dst q", "src": "/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:51.26-51.27" } }, "memctrl_I.dly_si_mode.clk": { "hide_name": 0, "bits": [ 42 ], "attributes": { "hdlname": "memctrl_I dly_si_mode clk", "src": "/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:23.14-23.17" } }, "memctrl_I.dly_si_mode.d": { "hide_name": 0, "bits": [ 5404 ], "attributes": { "hdlname": "memctrl_I dly_si_mode d", "src": "/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:21.14-21.15" } }, "memctrl_I.dly_si_mode.dl": { "hide_name": 0, "bits": [ 5408, 5406, 5407, 5409 ], "attributes": { "hdlname": "memctrl_I dly_si_mode dl", "src": "/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/delay.v:26.18-26.20" } }, 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"bits": [ "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x", "x" ], "attributes": { "hdlname": "memctrl_I genblk1.rsp_fifo_I data[0]", "src": "/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:40.20-40.24" } }, "memctrl_I.genblk1.rsp_fifo_I.data[1]": { "hide_name": 0, "bits": [ 7215, 7216, 7217, 5440, 7218, 7219, 5439, 5437, 5436, 5435, 7220, 7221, 5434, 7222, 7223, 7224, 5433, 5432, 5431, 5430, 5429, 5428, 5447, 5446, 5445, 5444, 5443, 5442, 5441, 5438, 5427, 5426 ], "attributes": { "hdlname": "memctrl_I genblk1.rsp_fifo_I data[1]", "src": "/home/jduchniewicz/Projects/SideHustle/FPGASignalsKS/ice40-playground/cores/no2misc//rtl/fifo_sync_shift.v:40.20-40.24", "unused_bits": "0 1 2 4 5 10 11 13 14 15" } }, "memctrl_I.genblk1.rsp_fifo_I.data[2]": { "hide_name": 0, "bits": [ 218, 217, 216, 225, 273, 272, 271, 280, 222, 221, 220, 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