`timescale 1ns / 1ps

module buttons(
	input CLK,
	input BTN1,
	input BTN2,
	input BTN3,
	input BTN_N,
	output reg [15:0] duty_val
	);	
	
	wire [3:0]butts={BTN_N,BTN3,BTN2,BTN1};
	reg [3:0]butts_buf;
	
	//b1111111111111100 - ciemne
	always @(posedge CLK) begin
		case(butts)
			4'b0001: duty_val <= 16'b0000000000000000;
			4'b0010: duty_val <= 16'b0000000000000000;
			4'b0100: duty_val <= 16'b0000000000000000;
			4'b1000: duty_val <= 16'b1000000000000000;
            default: duty_val <= 16'b0000000000000000;
        endcase
		butts_buf<=butts;
	end

endmodule