start.S 2.3 KB

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  1. /*
  2. * start.S
  3. *
  4. * Startup code taken from picosoc/picorv32 and adapted for use here
  5. *
  6. * Copyright (C) 2017 Clifford Wolf <clifford@clifford.at>
  7. * Copyright (C) 2019 Sylvain Munaut <tnt@246tNt.com>
  8. *
  9. * Permission to use, copy, modify, and/or distribute this software for any
  10. * purpose with or without fee is hereby granted, provided that the above
  11. * copyright notice and this permission notice appear in all copies.
  12. *
  13. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  14. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  15. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  16. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  17. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  18. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  19. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  20. */
  21. .section .text.start
  22. .global _start
  23. _start:
  24. // zero-initialize register file
  25. addi x1, zero, 0
  26. // x2 (sp) is initialized by reset
  27. addi x3, zero, 0
  28. addi x4, zero, 0
  29. addi x5, zero, 0
  30. addi x6, zero, 0
  31. addi x7, zero, 0
  32. addi x8, zero, 0
  33. addi x9, zero, 0
  34. addi x10, zero, 0
  35. addi x11, zero, 0
  36. addi x12, zero, 0
  37. addi x13, zero, 0
  38. addi x14, zero, 0
  39. addi x15, zero, 0
  40. addi x16, zero, 0
  41. addi x17, zero, 0
  42. addi x18, zero, 0
  43. addi x19, zero, 0
  44. addi x20, zero, 0
  45. addi x21, zero, 0
  46. addi x22, zero, 0
  47. addi x23, zero, 0
  48. addi x24, zero, 0
  49. addi x25, zero, 0
  50. addi x26, zero, 0
  51. addi x27, zero, 0
  52. addi x28, zero, 0
  53. addi x29, zero, 0
  54. addi x30, zero, 0
  55. addi x31, zero, 0
  56. #ifdef BOOT_DEBUG
  57. // Set UART divisor
  58. li a0, 0x81000000
  59. li a1, 22
  60. sw a1, 4(a0)
  61. // Output '1'
  62. li a1, 49
  63. sw a1, 0(a0)
  64. #endif
  65. // copy data section
  66. la a0, _sidata
  67. la a1, _sdata
  68. la a2, _edata
  69. bge a1, a2, end_init_data
  70. loop_init_data:
  71. lw a3, 0(a0)
  72. sw a3, 0(a1)
  73. addi a0, a0, 4
  74. addi a1, a1, 4
  75. blt a1, a2, loop_init_data
  76. end_init_data:
  77. #ifdef BOOT_DEBUG
  78. // Output '2'
  79. li a0, 0x81000000
  80. li a1, 50
  81. sw a1, 0(a0)
  82. #endif
  83. // zero-init bss section
  84. la a0, _sbss
  85. la a1, _ebss
  86. bge a0, a1, end_init_bss
  87. loop_init_bss:
  88. sw zero, 0(a0)
  89. addi a0, a0, 4
  90. blt a0, a1, loop_init_bss
  91. end_init_bss:
  92. #ifdef BOOT_DEBUG
  93. // Output '3'
  94. li a0, 0x81000000
  95. li a1, 51
  96. sw a1, 0(a0)
  97. #endif
  98. // call main
  99. call main
  100. loop:
  101. j loop