sysmgr.v 2.8 KB

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  1. /*
  2. * sysmgr.v
  3. *
  4. * Copyright (C) 2019 Sylvain Munaut <tnt@246tNt.com>
  5. * All rights reserved.
  6. *
  7. * BSD 3-clause, see LICENSE.bsd
  8. *
  9. * Redistribution and use in source and binary forms, with or without
  10. * modification, are permitted provided that the following conditions are met:
  11. * * Redistributions of source code must retain the above copyright
  12. * notice, this list of conditions and the following disclaimer.
  13. * * Redistributions in binary form must reproduce the above copyright
  14. * notice, this list of conditions and the following disclaimer in the
  15. * documentation and/or other materials provided with the distribution.
  16. * * Neither the name of the <organization> nor the
  17. * names of its contributors may be used to endorse or promote products
  18. * derived from this software without specific prior written permission.
  19. *
  20. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  21. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  22. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  23. * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  24. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  25. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  26. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  27. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  28. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  29. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  30. *
  31. * vim: ts=4 sw=4
  32. */
  33. `default_nettype none
  34. module sysmgr (
  35. input wire clk_in,
  36. input wire rst_in,
  37. output wire clk_out,
  38. output wire rst_out
  39. );
  40. // Signals
  41. wire pll_lock;
  42. wire pll_reset_n;
  43. wire clk_i;
  44. wire rst_i;
  45. reg [3:0] rst_cnt;
  46. // PLL instance
  47. `ifdef SIM
  48. assign clk_i = clk_in;
  49. assign pll_lock = pll_reset_n;
  50. `else
  51. SB_PLL40_PAD #(
  52. .DIVR(4'b0000),
  53. .DIVF(7'b1001111),
  54. .DIVQ(3'b101),
  55. .FILTER_RANGE(3'b001),
  56. .FEEDBACK_PATH("SIMPLE"),
  57. .DELAY_ADJUSTMENT_MODE_FEEDBACK("FIXED"),
  58. .FDA_FEEDBACK(4'b0000),
  59. .SHIFTREG_DIV_MODE(2'b00),
  60. .PLLOUT_SELECT("GENCLK"),
  61. .ENABLE_ICEGATE(1'b0)
  62. ) pll_I (
  63. .PACKAGEPIN(clk_in),
  64. .PLLOUTCORE(),
  65. .PLLOUTGLOBAL(clk_i),
  66. .EXTFEEDBACK(1'b0),
  67. .DYNAMICDELAY(8'h00),
  68. .RESETB(pll_reset_n),
  69. .BYPASS(1'b0),
  70. .LATCHINPUTVALUE(1'b0),
  71. .LOCK(pll_lock),
  72. .SDI(1'b0),
  73. .SDO(),
  74. .SCLK(1'b0)
  75. );
  76. `endif
  77. assign clk_out = clk_i;
  78. // PLL reset generation
  79. assign pll_reset_n = ~rst_in;
  80. // Logic reset generation
  81. always @(posedge clk_i or negedge pll_lock)
  82. if (!pll_lock)
  83. rst_cnt <= 4'h8;
  84. else if (rst_cnt[3])
  85. rst_cnt <= rst_cnt + 1;
  86. assign rst_i = rst_cnt[3];
  87. SB_GB rst_gbuf_I (
  88. .USER_SIGNAL_TO_GLOBAL_BUFFER(rst_i),
  89. .GLOBAL_BUFFER_OUTPUT(rst_out)
  90. );
  91. endmodule // sysmgr