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doom_riscv
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Sylvain Munaut f33e481214 build: When creating verilog define for board name, replace - with _ il y a 5 ans
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core-magic.mk b90e522d72 build: Allow 'simulation sources' in cores and projects il y a 6 ans
core-rules.mk 4812ab7b22 build: Add explicit include directory for the rtl/ & sim/ dir of each core il y a 6 ans
project-rules.mk f33e481214 build: When creating verilog define for board name, replace - with _ il y a 5 ans