jduchniewicz/doom_riscv @ 1f58e62045d1a0aea44954c4b828b02d7ad2f8ce

Sylvain Munaut f33e481214 build: When creating verilog define for board name, replace - with _		5 anni fa
..
core-magic.mk	b90e522d72 build: Allow 'simulation sources' in cores and projects	6 anni fa
core-rules.mk	4812ab7b22 build: Add explicit include directory for the rtl/ & sim/ dir of each core	6 anni fa
project-rules.mk	f33e481214 build: When creating verilog define for board name, replace - with _	5 anni fa