jduchniewicz/doom_riscv @ 1f58e62045d1a0aea44954c4b828b02d7ad2f8ce

Sylvain Munaut f33e481214 build: When creating verilog define for board name, replace - with _		пре 5 година
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core-magic.mk	b90e522d72 build: Allow 'simulation sources' in cores and projects	пре 6 година
core-rules.mk	4812ab7b22 build: Add explicit include directory for the rtl/ & sim/ dir of each core	пре 6 година
project-rules.mk	f33e481214 build: When creating verilog define for board name, replace - with _	пре 5 година