Jakub Duchniewicz 20b5151657 Increase the internal registers to 32 bits for WB compatibility.		před 3 týdny
..
data	bc60e00b90 Port 3signal code and integrate to the top module.	před 3 týdny
fw	888981826f Transition to riscv_usb as base for out project.	před 3 týdny
rtl	20b5151657 Increase the internal registers to 32 bits for WB compatibility.	před 3 týdny
sim	f560755b26 projects/riscv_usb: Add support for the user button	před 4 roky
Makefile	c44a5464d7 Add mailbox for RTL/SW communication.	před 3 týdny
README.md	fd6a09e0c2 projects/riscv_usb: Fixup the README	před 1 rokem

RISC-V + USB core demo

For the icebreaker, the hardware connections are :

To run :

Build and flash the bitstream
- This will build fw/boot.hex and include it as the BRAM initial data
Flash the main application code in SPI at offset 1M
- make -C fw prog
Connect to the iCEBreaker uart console (ttyUSB1) with a 1M baudrate
- and then at the Command> prompt, press c for 'connect'. This will start the USB detection and device should enumerate