1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889 |
- `default_nettype none
- module hdb3_dec (
-
- input wire in_pos,
- input wire in_neg,
- input wire in_valid,
-
- output wire out_data,
- output reg out_valid,
-
- input wire clk,
- input wire rst
- );
-
- wire violation;
- reg [3:0] data;
- reg pstate;
-
- assign out_data = data[3];
- always @(posedge clk)
- out_valid <= in_valid;
-
- assign violation = (in_pos & pstate) | (in_neg & ~pstate);
- always @(posedge clk)
- begin
- if (rst) begin
-
- data <= 4'h0;
- pstate <= 1'b0;
- end else if (in_valid) begin
- if (in_pos ^ in_neg) begin
-
- if (violation) begin
-
- data <= 4'h0;
- pstate <= pstate;
- end else begin
-
-
- data <= { data[2:0], 1'b1 };
- pstate <= pstate ^ 1;
- end
- end else begin
-
- data <= { data[2:0], 1'b0 };
- pstate <= pstate;
- end
- end
- end
- endmodule
|