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- commit e98ef3e8a325418d4c5ab9e07d14faa960b87adb
- Author: Jakub Duchniewicz <j.duchniewicz@gmail.com>
- Date: Wed Jan 8 13:49:49 2025 +0100
- Port 3signal code and integrate to the top module.
-
- Signed-off-by: Jakub Duchniewicz <j.duchniewicz@gmail.com>
- diff --git a/project-rules.mk b/project-rules.mk
- index 3ddbaa7..b430486 100644
- --- a/project-rules.mk
- +++ b/project-rules.mk
- @@ -79,7 +79,7 @@ PROJ_SIM_INCLUDES := -I$(abspath sim/) $(addsuffix /sim/, $(addprefix -I$(NO2C
- # Synthesis & Place-n-route rules
-
- $(BUILD_TMP)/$(PROJ).ys: $(PROJ_TOP_SRC) $(PROJ_ALL_RTL_SRCS)
- - @echo "read_verilog $(YOSYS_READ_ARGS) $(PROJ_SYNTH_INCLUDES) $(PROJ_TOP_SRC) $(PROJ_ALL_RTL_SRCS)" > $@
- + @echo "read_verilog -sv $(YOSYS_READ_ARGS) $(PROJ_SYNTH_INCLUDES) $(PROJ_TOP_SRC) $(PROJ_ALL_RTL_SRCS)" > $@
- @echo "synth_ice40 $(YOSYS_SYNTH_ARGS) -top $(PROJ_TOP_MOD) -json $(PROJ).json" >> $@
-
- $(BUILD_TMP)/$(PROJ).synth.rpt $(BUILD_TMP)/$(PROJ).json: $(PROJ_ALL_PREREQ) $(BUILD_TMP)/$(PROJ).ys $(PROJ_ALL_RTL_SRCS)
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