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- `default_nettype none
- module uart2wb #(
- parameter integer WB_N = 3,
-
- parameter integer DL = (32*WB_N)-1,
- parameter integer CL = WB_N-1
- )(
-
- input wire uart_rx,
- output wire uart_tx,
- input wire [ 7:0] uart_div,
-
- output reg [31:0] wb_wdata,
- input wire [DL:0] wb_rdata,
- output reg [15:0] wb_addr,
- output reg wb_we,
- output reg [CL:0] wb_cyc,
- input wire [CL:0] wb_ack,
-
- output reg [31:0] aux_csr,
-
- input wire clk,
- input wire rst
- );
- localparam
- CMD_SYNC = 4'h0,
- CMD_REG_ACCESS = 4'h1,
- CMD_DATA_SET = 4'h2,
- CMD_DATA_GET = 4'h3,
- CMD_AUX_CSR = 4'h4;
-
-
-
- wire [7:0] rx_data;
- wire rx_stb;
- wire [7:0] tx_data;
- wire tx_ack;
- wire tx_valid;
-
- reg [39:0] rx_reg;
- reg [ 2:0] rx_cnt;
- wire [ 3:0] cmd_code;
- wire [31:0] cmd_data;
- reg cmd_stb;
-
- reg [31:0] tx_reg;
- reg [ 2:0] tx_cnt;
- reg [31:0] resp_data;
- reg resp_ld;
-
- reg [31:0] wb_rdata_i;
- wire wb_ack_i;
-
-
-
- uart_rx #(
- .DIV_WIDTH(8),
- .GLITCH_FILTER(0)
- ) rx_I (
- .rx(uart_rx),
- .data(rx_data),
- .stb(rx_stb),
- .div(uart_div),
- .clk(clk),
- .rst(rst)
- );
- uart_tx #(
- .DIV_WIDTH(8)
- ) tx_I (
- .tx(uart_tx),
- .data(tx_data),
- .valid(tx_valid),
- .ack(tx_ack),
- .div(uart_div),
- .clk(clk),
- .rst(rst)
- );
-
- always @(posedge clk or posedge rst)
- if (rst)
- rx_cnt <= 3'd0;
- else if (rx_stb)
- rx_cnt <= rx_cnt[2] ? 3'd0 : (rx_cnt + 1);
- always @(posedge clk)
- if (rx_stb)
- rx_reg <= { rx_reg[31:0], rx_data };
- assign cmd_code = rx_reg[39:36];
- assign cmd_data = rx_reg[31: 0];
- always @(posedge clk)
- cmd_stb <= rx_cnt[2] & rx_stb;
-
- always @(posedge clk or posedge rst)
- if (rst)
- tx_cnt <= 3'd0;
- else begin
- if (resp_ld)
- tx_cnt <= 3'd4;
- else if (tx_ack)
- tx_cnt <= tx_cnt - 1;
- end
- always @(posedge clk)
- if (resp_ld)
- tx_reg <= resp_data;
- else if (tx_ack)
- tx_reg <= { tx_reg[23:0], 8'h00 };
- assign tx_data = tx_reg[31:24];
- assign tx_valid = |tx_cnt;
-
- always @(posedge clk)
- begin
-
- resp_ld <= 1'b0;
- resp_data <= 40'hxxxxxxxxxx;
-
- if (cmd_stb) begin
- case (cmd_code)
- CMD_SYNC: begin
- resp_data <= 432'hcafebabe;
- resp_ld <= 1'b1;
- end
- CMD_REG_ACCESS: begin
- wb_addr <= cmd_data[15:0];
- wb_we <= ~cmd_data[20];
- wb_cyc <= (1 << cmd_data[19:16]);
- end
- CMD_DATA_SET: begin
- wb_wdata <= cmd_data;
- end
- CMD_DATA_GET: begin
- resp_ld <= 1'b1;
- resp_data <= wb_wdata;
- end
- CMD_AUX_CSR: begin
- aux_csr <= cmd_data;
- end
- endcase
- end
- if (wb_ack_i) begin
-
- wb_cyc <= 0;
-
- if (~wb_we)
- wb_wdata <= wb_rdata_i;
- end
- if (rst) begin
- wb_cyc <= 0;
- aux_csr <= 32'h00000000;
- end
- end
-
- assign wb_ack_i = |wb_ack;
- always @(*)
- begin : rdata
- integer i;
- wb_rdata_i = 32'h00000000;
- for (i=0; i<WB_N; i=i+1)
- wb_rdata_i = wb_rdata_i | wb_rdata[32*i+:32];
- end
- endmodule
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