usb.v 13 KB

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  1. /*
  2. * usb.v
  3. *
  4. * vim: ts=4 sw=4
  5. *
  6. * Copyright (C) 2019 Sylvain Munaut
  7. * All rights reserved.
  8. *
  9. * LGPL v3+, see LICENSE.lgpl3
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU Lesser General Public
  13. * License as published by the Free Software Foundation; either
  14. * version 3 of the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * Lesser General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU Lesser General Public License
  22. * along with this program; if not, write to the Free Software Foundation,
  23. * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  24. */
  25. `default_nettype none
  26. module usb #(
  27. parameter TARGET = "ICE40",
  28. parameter integer EPDW = 16,
  29. parameter integer EVT_DEPTH = 0,
  30. /* Auto-set */
  31. parameter integer EPAW = 11 - $clog2(EPDW / 8)
  32. )(
  33. // Pads
  34. inout wire pad_dp,
  35. inout wire pad_dn,
  36. output reg pad_pu,
  37. // EP buffer interface
  38. input wire [EPAW-1:0] ep_tx_addr_0,
  39. input wire [EPDW-1:0] ep_tx_data_0,
  40. input wire ep_tx_we_0,
  41. input wire [EPAW-1:0] ep_rx_addr_0,
  42. output wire [EPDW-1:0] ep_rx_data_1,
  43. input wire ep_rx_re_0,
  44. input wire ep_clk,
  45. // Bus interface
  46. input wire [11:0] bus_addr,
  47. input wire [15:0] bus_din,
  48. output wire [15:0] bus_dout,
  49. input wire bus_cyc,
  50. input wire bus_we,
  51. output wire bus_ack,
  52. // IRQ
  53. output wire irq,
  54. // SOF indication
  55. output wire sof,
  56. // Common
  57. input wire clk,
  58. input wire rst
  59. );
  60. // Signals
  61. // -------
  62. // PHY
  63. wire phy_rx_dp;
  64. wire phy_rx_dn;
  65. wire phy_rx_chg;
  66. wire phy_tx_dp;
  67. wire phy_tx_dn;
  68. wire phy_tx_en;
  69. // TX Low-Level
  70. wire txll_start;
  71. wire txll_bit;
  72. wire txll_last;
  73. wire txll_ack;
  74. // TX Packet
  75. wire txpkt_start;
  76. wire txpkt_done;
  77. wire [3:0] txpkt_pid;
  78. wire [9:0] txpkt_len;
  79. wire [7:0] txpkt_data;
  80. wire txpkt_data_ack;
  81. // RX Low-Level
  82. wire [1:0] rxll_sym;
  83. wire rxll_bit;
  84. wire rxll_valid;
  85. wire rxll_eop;
  86. wire rxll_sync;
  87. wire rxll_bs_skip;
  88. wire rxll_bs_err;
  89. // RX Packet
  90. wire rxpkt_start;
  91. wire rxpkt_done_ok;
  92. wire rxpkt_done_err;
  93. wire [ 3:0] rxpkt_pid;
  94. wire rxpkt_is_sof;
  95. wire rxpkt_is_token;
  96. wire rxpkt_is_data;
  97. wire rxpkt_is_handshake;
  98. wire [10:0] rxpkt_frameno;
  99. wire [ 6:0] rxpkt_addr;
  100. wire [ 3:0] rxpkt_endp;
  101. wire [ 7:0] rxpkt_data;
  102. wire rxpkt_data_stb;
  103. // EP Buffers
  104. wire [10:0] buf_tx_addr_0;
  105. wire [ 7:0] buf_tx_data_1;
  106. wire buf_tx_rden_0;
  107. wire [10:0] buf_rx_addr_0;
  108. wire [ 7:0] buf_rx_data_0;
  109. wire buf_rx_wren_0;
  110. // EP Status
  111. wire eps_read_0;
  112. wire eps_zero_0;
  113. wire eps_write_0;
  114. wire [ 7:0] eps_addr_0;
  115. wire [15:0] eps_wrdata_0;
  116. wire [15:0] eps_rddata_3;
  117. wire eps_bus_ready;
  118. reg eps_bus_read;
  119. wire eps_bus_zero;
  120. reg eps_bus_write;
  121. wire [15:0] eps_bus_dout;
  122. // Config / Status registers
  123. reg cr_pu_ena;
  124. reg cr_cel_ena;
  125. reg [ 6:0] cr_addr;
  126. wire cel_state;
  127. reg cel_rel;
  128. // Bus interface
  129. // Events
  130. wire [11:0] evt_data;
  131. wire evt_stb;
  132. // Out-of-band conditions
  133. wire oob_se0;
  134. wire oob_sof;
  135. reg [19:0] timeout_suspend; // 3 ms with no activity
  136. reg [19:0] timeout_reset; // 10 ms SE0
  137. reg rst_usb_l;
  138. reg suspend;
  139. // Start-Of-Frame indication
  140. reg sof_ind;
  141. // USB core logic reset
  142. wire rst_usb;
  143. // PHY
  144. // ---
  145. usb_phy #(
  146. .TARGET(TARGET)
  147. ) phy_I (
  148. .pad_dp(pad_dp),
  149. .pad_dn(pad_dn),
  150. .rx_dp(phy_rx_dp),
  151. .rx_dn(phy_rx_dn),
  152. .rx_chg(phy_rx_chg),
  153. .tx_dp(phy_tx_dp),
  154. .tx_dn(phy_tx_dn),
  155. `ifdef SIM
  156. .tx_en(1'b0),
  157. `else
  158. .tx_en(phy_tx_en),
  159. `endif
  160. .clk(clk),
  161. .rst(rst)
  162. );
  163. // TX
  164. // --
  165. usb_tx_ll tx_ll_I (
  166. .phy_tx_dp(phy_tx_dp),
  167. .phy_tx_dn(phy_tx_dn),
  168. .phy_tx_en(phy_tx_en),
  169. .ll_start(txll_start),
  170. .ll_bit(txll_bit),
  171. .ll_last(txll_last),
  172. .ll_ack(txll_ack),
  173. .clk(clk),
  174. .rst(rst)
  175. );
  176. usb_tx_pkt tx_pkt_I (
  177. .ll_start(txll_start),
  178. .ll_bit(txll_bit),
  179. .ll_last(txll_last),
  180. .ll_ack(txll_ack),
  181. .pkt_start(txpkt_start),
  182. .pkt_done(txpkt_done),
  183. .pkt_pid(txpkt_pid),
  184. .pkt_len(txpkt_len),
  185. .pkt_data(txpkt_data),
  186. .pkt_data_ack(txpkt_data_ack),
  187. .clk(clk),
  188. .rst(rst)
  189. );
  190. // RX
  191. // --
  192. usb_rx_ll rx_ll_I (
  193. .phy_rx_dp(phy_rx_dp),
  194. .phy_rx_dn(phy_rx_dn),
  195. .phy_rx_chg(phy_rx_chg),
  196. .ll_sym(rxll_sym),
  197. .ll_bit(rxll_bit),
  198. .ll_valid(rxll_valid),
  199. .ll_eop(rxll_eop),
  200. .ll_sync(rxll_sync),
  201. .ll_bs_skip(rxll_bs_skip),
  202. .ll_bs_err(rxll_bs_err),
  203. .clk(clk),
  204. .rst(rst)
  205. );
  206. usb_rx_pkt rx_pkt_I (
  207. .ll_sym(rxll_sym),
  208. .ll_bit(rxll_bit),
  209. .ll_valid(rxll_valid),
  210. .ll_eop(rxll_eop),
  211. .ll_sync(rxll_sync),
  212. .ll_bs_skip(rxll_bs_skip),
  213. .ll_bs_err(rxll_bs_err),
  214. .pkt_start(rxpkt_start),
  215. .pkt_done_ok(rxpkt_done_ok),
  216. .pkt_done_err(rxpkt_done_err),
  217. .pkt_pid(rxpkt_pid),
  218. .pkt_is_sof(rxpkt_is_sof),
  219. .pkt_is_token(rxpkt_is_token),
  220. .pkt_is_data(rxpkt_is_data),
  221. .pkt_is_handshake(rxpkt_is_handshake),
  222. .pkt_frameno(rxpkt_frameno),
  223. .pkt_addr(rxpkt_addr),
  224. .pkt_endp(rxpkt_endp),
  225. .pkt_data(rxpkt_data),
  226. .pkt_data_stb(rxpkt_data_stb),
  227. .inhibit(phy_tx_en),
  228. .clk(clk),
  229. .rst(rst)
  230. );
  231. // Transaction control
  232. // -------------------
  233. usb_trans trans_I (
  234. .txpkt_start(txpkt_start),
  235. .txpkt_done(txpkt_done),
  236. .txpkt_pid(txpkt_pid),
  237. .txpkt_len(txpkt_len),
  238. .txpkt_data(txpkt_data),
  239. .txpkt_data_ack(txpkt_data_ack),
  240. .rxpkt_start(rxpkt_start),
  241. .rxpkt_done_ok(rxpkt_done_ok),
  242. .rxpkt_done_err(rxpkt_done_err),
  243. .rxpkt_pid(rxpkt_pid),
  244. .rxpkt_is_sof(rxpkt_is_sof),
  245. .rxpkt_is_token(rxpkt_is_token),
  246. .rxpkt_is_data(rxpkt_is_data),
  247. .rxpkt_is_handshake(rxpkt_is_handshake),
  248. .rxpkt_frameno(rxpkt_frameno),
  249. .rxpkt_addr(rxpkt_addr),
  250. .rxpkt_endp(rxpkt_endp),
  251. .rxpkt_data(rxpkt_data),
  252. .rxpkt_data_stb(rxpkt_data_stb),
  253. .buf_tx_addr_0(buf_tx_addr_0),
  254. .buf_tx_data_1(buf_tx_data_1),
  255. .buf_tx_rden_0(buf_tx_rden_0),
  256. .buf_rx_addr_0(buf_rx_addr_0),
  257. .buf_rx_data_0(buf_rx_data_0),
  258. .buf_rx_wren_0(buf_rx_wren_0),
  259. .eps_read_0(eps_read_0),
  260. .eps_zero_0(eps_zero_0),
  261. .eps_write_0(eps_write_0),
  262. .eps_addr_0(eps_addr_0),
  263. .eps_wrdata_0(eps_wrdata_0),
  264. .eps_rddata_3(eps_rddata_3),
  265. .cr_addr(cr_addr),
  266. .evt_data(evt_data),
  267. .evt_stb(evt_stb),
  268. .cel_state(cel_state),
  269. .cel_rel(cel_rel),
  270. .cel_ena(cr_cel_ena),
  271. .clk(clk),
  272. .rst(rst)
  273. );
  274. // EP buffers
  275. // ----------
  276. usb_ep_buf #(
  277. .TARGET(TARGET),
  278. .RWIDTH(8),
  279. .WWIDTH(EPDW)
  280. ) tx_buf_I (
  281. .rd_addr_0(buf_tx_addr_0),
  282. .rd_data_1(buf_tx_data_1),
  283. .rd_en_0(buf_tx_rden_0),
  284. .rd_clk(clk),
  285. .wr_addr_0(ep_tx_addr_0),
  286. .wr_data_0(ep_tx_data_0),
  287. .wr_en_0(ep_tx_we_0),
  288. .wr_clk(ep_clk)
  289. );
  290. usb_ep_buf #(
  291. .TARGET(TARGET),
  292. .RWIDTH(EPDW),
  293. .WWIDTH(8)
  294. ) rx_buf_I (
  295. .rd_addr_0(ep_rx_addr_0),
  296. .rd_data_1(ep_rx_data_1),
  297. .rd_en_0(ep_rx_re_0),
  298. .rd_clk(ep_clk),
  299. .wr_addr_0(buf_rx_addr_0),
  300. .wr_data_0(buf_rx_data_0),
  301. .wr_en_0(buf_rx_wren_0),
  302. .wr_clk(clk)
  303. );
  304. // EP Status / Buffer Descriptors
  305. // ------------------------------
  306. usb_ep_status ep_status_I (
  307. .p_addr_0(eps_addr_0),
  308. .p_read_0(eps_read_0),
  309. .p_zero_0(eps_zero_0),
  310. .p_write_0(eps_write_0),
  311. .p_din_0(eps_wrdata_0),
  312. .p_dout_3(eps_rddata_3),
  313. .s_addr_0(bus_addr[7:0]),
  314. .s_read_0(eps_bus_ready),
  315. .s_zero_0(eps_bus_zero),
  316. .s_write_0(eps_bus_write),
  317. .s_din_0(bus_din),
  318. .s_dout_3(eps_bus_dout),
  319. .s_ready_0(eps_bus_ready),
  320. .clk(clk),
  321. .rst(rst)
  322. );
  323. // CSR & Bus Interface
  324. // -------------------
  325. reg csr_bus_req;
  326. wire csr_bus_clear;
  327. wire csr_bus_ack;
  328. reg [15:0] csr_bus_dout;
  329. reg cr_bus_we;
  330. reg eps_bus_req;
  331. wire eps_bus_clear;
  332. reg eps_bus_ack_wait;
  333. wire eps_bus_req_ok;
  334. reg [2:0] eps_bus_req_ok_dly;
  335. wire [15:0] evt_rd_data;
  336. wire evt_rd_rdy;
  337. reg evt_rd_ack;
  338. // Request lines for registers and strobes for actions
  339. always @(posedge clk)
  340. if (csr_bus_clear) begin
  341. csr_bus_req <= 1'b0;
  342. cr_bus_we <= 1'b0;
  343. cel_rel <= 1'b0;
  344. evt_rd_ack <= 1'b0;
  345. end else begin
  346. csr_bus_req <= 1'b1;
  347. cr_bus_we <= (bus_addr[1:0] == 2'b00) & bus_we;
  348. cel_rel <= (bus_addr[1:0] == 2'b01) & bus_we & bus_din[13];
  349. evt_rd_ack <= (bus_addr[1:0] == 2'b10) & ~bus_we & evt_rd_rdy;
  350. end
  351. // Read mux for CSR
  352. always @(posedge clk)
  353. if (csr_bus_clear)
  354. csr_bus_dout <= 16'h0000;
  355. else
  356. case (bus_addr[1:0])
  357. 2'b00: csr_bus_dout <= { cr_pu_ena, 1'b0, cel_state, cr_cel_ena, 5'b00000, cr_addr } ;
  358. 2'b10: csr_bus_dout <= evt_rd_data;
  359. default: csr_bus_dout <= 16'h0000;
  360. endcase
  361. // CSR Clear/Ack
  362. assign csr_bus_ack = csr_bus_req;
  363. assign csr_bus_clear = ~bus_cyc | csr_bus_ack | bus_addr[11];
  364. // Write regs
  365. always @(posedge clk)
  366. if (cr_bus_we) begin
  367. cr_pu_ena <= bus_din[15];
  368. cr_cel_ena <= bus_din[12];
  369. cr_addr <= bus_din[5:0];
  370. end
  371. // Request lines for EP Status access
  372. always @(posedge clk)
  373. if (eps_bus_clear) begin
  374. eps_bus_read <= 1'b0;
  375. eps_bus_write <= 1'b0;
  376. eps_bus_req <= 1'b0;
  377. end else begin
  378. eps_bus_read <= bus_addr[11] & ~bus_we;
  379. eps_bus_write <= bus_addr[11] & bus_we;
  380. eps_bus_req <= bus_addr[11];
  381. end
  382. assign eps_bus_zero = ~eps_bus_read;
  383. // EPS Clear
  384. assign eps_bus_clear = ~bus_cyc | eps_bus_ack_wait | (eps_bus_req & eps_bus_ready);
  385. // Track when request are accepted by the RAM
  386. assign eps_bus_req_ok = (eps_bus_req & eps_bus_ready);
  387. always @(posedge clk)
  388. eps_bus_req_ok_dly <= { eps_bus_req_ok_dly[1:0], eps_bus_req_ok & ~bus_we };
  389. // ACK wait state tracking
  390. always @(posedge clk or posedge rst)
  391. if (rst)
  392. eps_bus_ack_wait <= 1'b0;
  393. else
  394. eps_bus_ack_wait <= ((eps_bus_ack_wait & ~bus_we) | eps_bus_req_ok) & ~eps_bus_req_ok_dly[2];
  395. // Bus Ack
  396. assign bus_ack = csr_bus_ack | (eps_bus_ack_wait & (bus_we | eps_bus_req_ok_dly[2]));
  397. // Output is simply the OR of all local units since we force them to zero if
  398. // they're not accessed
  399. assign bus_dout = csr_bus_dout | eps_bus_dout;
  400. // Event handling
  401. // --------------
  402. generate
  403. if (EVT_DEPTH == 0) begin
  404. // We just save the # of notify since last read
  405. reg [3:0] evt_cnt;
  406. always @(posedge clk or posedge rst)
  407. if (rst)
  408. evt_cnt <= 4'h0;
  409. else
  410. evt_cnt <= evt_rd_ack ? { 3'b000, evt_stb } : (evt_cnt + evt_stb);
  411. assign evt_rd_rdy = 1'b1;
  412. assign evt_rd_data = { evt_cnt, 12'h000 };
  413. assign irq = (evt_cnt != 4'h0);
  414. end else if (EVT_DEPTH == 1) begin
  415. // Save the latest value and # of notify since last read
  416. reg [11:0] evt_last;
  417. reg [ 3:0] evt_cnt;
  418. always @(posedge clk or posedge rst)
  419. if (rst)
  420. evt_cnt <= 4'h0;
  421. else
  422. evt_cnt <= evt_rd_ack ? { 3'b000, evt_stb } : (evt_cnt + evt_stb);
  423. always @(posedge clk)
  424. if (evt_stb)
  425. evt_last <= evt_data;
  426. assign evt_rd_rdy = 1'b1;
  427. assign evt_rd_data = { evt_cnt, evt_last };
  428. assign irq = (evt_cnt != 4'h0);
  429. end else if (EVT_DEPTH > 1) begin
  430. // Small shift-reg FIFO
  431. wire [11:0] ef_wdata;
  432. wire [11:0] ef_rdata;
  433. wire ef_wren;
  434. wire ef_full;
  435. wire ef_rden;
  436. wire ef_empty;
  437. reg ef_overflow;
  438. assign ef_wdata = evt_data;
  439. assign ef_wren = evt_stb & ~ef_full;
  440. always @(posedge clk or posedge rst)
  441. if (rst)
  442. ef_overflow <= 1'b0;
  443. else
  444. ef_overflow <= (ef_overflow & ~evt_rd_ack) | (evt_stb & ef_full);
  445. assign evt_rd_rdy = ~ef_empty;
  446. assign evt_rd_data = { ~ef_empty, ef_overflow, 2'b00, ef_rdata };
  447. assign ef_rden = evt_rd_ack;
  448. assign irq = ~ef_rden;
  449. fifo_sync_shift #(
  450. .DEPTH(EVT_DEPTH),
  451. .WIDTH(12)
  452. ) evt_fifo_I (
  453. .wr_data(ef_wdata),
  454. .wr_ena(ef_wren),
  455. .wr_full(ef_full),
  456. .rd_data(ef_rdata),
  457. .rd_ena(ef_rden),
  458. .rd_empty(ef_empty),
  459. .clk(clk),
  460. .rst(rst)
  461. );
  462. end
  463. endgenerate
  464. // USB reset/suspend
  465. // -----------------
  466. // Detect some conditions for triggers
  467. assign oob_se0 = !phy_rx_dp && !phy_rx_dn;
  468. assign oob_sof = rxpkt_start & rxpkt_is_sof;
  469. // Suspend timeout counter
  470. always @(posedge clk)
  471. if (rst_usb)
  472. timeout_suspend <= 20'ha3280;
  473. else
  474. timeout_suspend <= oob_sof ? 20'ha3280 : (timeout_suspend - timeout_suspend[19]);
  475. always @(posedge clk)
  476. if (rst_usb)
  477. suspend <= 1'b0;
  478. else
  479. suspend <= ~timeout_suspend[19];
  480. // Reset timeout counter
  481. always @(posedge clk)
  482. if (rst)
  483. timeout_reset <= 20'hf5300;
  484. else
  485. timeout_reset <= oob_se0 ? (timeout_reset - timeout_reset[19]) : 20'hf5300;
  486. always @(posedge clk)
  487. if (rst)
  488. rst_usb_l <= 1'b1;
  489. else
  490. rst_usb_l <= ~timeout_reset[19];
  491. // Global reset driver
  492. generate
  493. if (TARGET == "GENERIC")
  494. assign rst_usb = rst_usb_l;
  495. else if (TARGET == "ICE40")
  496. SB_GB usb_rst_gb_I (
  497. .USER_SIGNAL_TO_GLOBAL_BUFFER(rst_usb_l),
  498. .GLOBAL_BUFFER_OUTPUT(rst_usb)
  499. );
  500. endgenerate
  501. // Detection pin
  502. always @(posedge clk)
  503. if (rst)
  504. pad_pu <= 1'b0;
  505. else
  506. pad_pu <= cr_pu_ena;
  507. // Misc
  508. // ----
  509. always @(posedge clk)
  510. sof_ind <= rxpkt_start & rxpkt_is_sof;
  511. assign sof = sof_ind;
  512. endmodule // usb