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- `default_nettype none
- module usb_crc #(
- parameter integer WIDTH = 5,
- parameter POLY = 5'b00011,
- parameter MATCH = 5'b00000
- )(
-
- input wire in_bit,
- input wire in_first,
- input wire in_valid,
-
- output wire [WIDTH-1:0] crc,
- output wire crc_match,
-
- input wire clk,
- input wire rst
- );
- wire [WIDTH-1:0] state;
- wire [WIDTH-1:0] state_fb_mux;
- wire [WIDTH-1:0] state_upd_mux;
- wire [WIDTH-1:0] state_nxt;
- assign state_fb_mux = in_first ? { WIDTH{1'b1} } : state;
- assign state_upd_mux = (state_fb_mux[WIDTH-1] != in_bit) ? POLY : 0;
- assign state_nxt = { state_fb_mux[WIDTH-2:0], 1'b0 } ^ state_upd_mux;
- dffe_n #(
- .WIDTH(WIDTH)
- ) state_reg_I (
- .d(state_nxt),
- .q(state),
- .ce(in_valid),
- .clk(clk)
- );
- assign crc_match = (state == MATCH);
- genvar i;
- generate
- for (i=0; i<WIDTH; i=i+1)
- assign crc[i] = ~state[WIDTH-1-i];
- endgenerate
- endmodule
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