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- `default_nettype none
- module usb_tx_ll (
-
- output wire phy_tx_dp,
- output wire phy_tx_dn,
- output wire phy_tx_en,
-
- input wire ll_start,
- input wire ll_bit,
- input wire ll_last,
- output reg ll_ack,
-
- input wire clk,
- input wire rst
- );
- `include "usb_defs.vh"
-
-
-
- reg [2:0] state;
- wire active;
- reg [2:0] br_cnt;
- wire br_now;
-
- reg [2:0] bs_cnt;
- reg bs_now;
- wire bs_bit;
-
- reg lvl_prev;
-
- reg out_active;
- reg [1:0] out_sym;
-
-
- always @(posedge clk or posedge rst)
- if (rst)
- state <= 3'b000;
- else begin
- if (ll_start)
- state <= 3'b100;
- else if (br_now) begin
- if (ll_last)
- state <= 3'b101;
- else
- case (state[1:0])
- 2'b00: state <= state;
- 2'b01: state <= 3'b110;
- 2'b10: state <= 3'b111;
- default: state <= 3'b000;
- endcase
- end
- end
- assign active = state[2];
- always @(posedge clk)
- br_cnt <= { 1'b0, active ? br_cnt[1:0] : 2'b10 } + 1;
- assign br_now = br_cnt[2];
-
-
-
- always @(posedge clk or posedge ll_start)
- if (ll_start) begin
- bs_cnt <= 3'b000;
- bs_now <= 1'b0;
- end else if (br_now) begin
- bs_cnt <= (ll_bit & ~bs_now) ? (bs_cnt + 1) : 3'b000;
- bs_now <= ll_bit & (bs_cnt == 3'b101);
- end
-
- assign bs_bit = ~bs_now & ll_bit;
-
- always @(posedge clk)
- lvl_prev <= active ? (lvl_prev ^ (~bs_bit & br_now)) : 1'b1;
-
-
-
- always @(posedge clk)
- ll_ack <= br_now & ~bs_now & (state[1:0] == 2'b00);
-
-
- always @(posedge clk or posedge rst)
- begin
- if (rst)
- out_sym <= SYM_J;
- else if (br_now) begin
- case (state[1:0])
- 2'b00: out_sym <= (bs_bit ^ lvl_prev) ? SYM_K : SYM_J;
- 2'b01: out_sym <= SYM_SE0;
- 2'b10: out_sym <= SYM_SE0;
- 2'b11: out_sym <= SYM_J;
- default: out_sym <= 2'bxx;
- endcase
- end
- end
-
-
- always @(posedge clk)
- out_active <= active;
-
- assign phy_tx_dp = out_sym[1];
- assign phy_tx_dn = out_sym[0];
- assign phy_tx_en = out_active;
- endmodule
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