top.v 11 KB

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  1. /*
  2. * top.v
  3. *
  4. * vim: ts=4 sw=4
  5. *
  6. * Copyright (C) 2019 Sylvain Munaut <tnt@246tNt.com>
  7. * All rights reserved.
  8. *
  9. * BSD 3-clause, see LICENSE.bsd
  10. *
  11. * Redistribution and use in source and binary forms, with or without
  12. * modification, are permitted provided that the following conditions are met:
  13. * * Redistributions of source code must retain the above copyright
  14. * notice, this list of conditions and the following disclaimer.
  15. * * Redistributions in binary form must reproduce the above copyright
  16. * notice, this list of conditions and the following disclaimer in the
  17. * documentation and/or other materials provided with the distribution.
  18. * * Neither the name of the <organization> nor the
  19. * names of its contributors may be used to endorse or promote products
  20. * derived from this software without specific prior written permission.
  21. *
  22. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
  23. * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
  24. * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25. * DISCLAIMED. IN NO EVENT SHALL <COPYRIGHT HOLDER> BE LIABLE FOR ANY
  26. * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
  27. * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
  28. * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
  29. * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  30. * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  31. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32. */
  33. `default_nettype none
  34. `include "boards.vh"
  35. module top (
  36. // SPI
  37. inout wire spi_mosi,
  38. inout wire spi_miso,
  39. inout wire spi_clk,
  40. inout wire spi_flash_cs_n,
  41. `ifdef HAS_PSRAM
  42. inout wire spi_ram_cs_n,
  43. `endif
  44. // USB
  45. inout wire usb_dp,
  46. inout wire usb_dn,
  47. output wire usb_pu,
  48. // Debug UART
  49. input wire uart_rx,
  50. output wire uart_tx,
  51. // Button
  52. input wire btn,
  53. // LED
  54. output wire [2:0] rgb,
  55. // Clock
  56. input wire clk_in
  57. );
  58. localparam WB_N = 6;
  59. localparam WB_DW = 32;
  60. localparam WB_AW = 16;
  61. localparam WB_AI = 2;
  62. localparam SPRAM_AW = 14; /* 14 => 64k, 15 => 128k */
  63. genvar i;
  64. // Signals
  65. // -------
  66. // Memory bus
  67. wire mem_valid;
  68. wire mem_instr;
  69. wire mem_ready;
  70. wire [31:0] mem_addr;
  71. wire [31:0] mem_rdata;
  72. wire [31:0] mem_wdata;
  73. wire [ 3:0] mem_wstrb;
  74. // RAM
  75. // BRAM
  76. wire [ 7:0] bram_addr;
  77. wire [31:0] bram_rdata;
  78. wire [31:0] bram_wdata;
  79. wire [ 3:0] bram_wmsk;
  80. wire bram_we;
  81. // SPRAM
  82. wire [14:0] spram_addr;
  83. wire [31:0] spram_rdata;
  84. wire [31:0] spram_wdata;
  85. wire [ 3:0] spram_wmsk;
  86. wire spram_we;
  87. // Wishbone
  88. wire [WB_AW-1:0] wb_addr;
  89. wire [WB_DW-1:0] wb_wdata;
  90. wire [(WB_DW/8)-1:0] wb_wmsk;
  91. wire [WB_DW-1:0] wb_rdata [0:WB_N-1];
  92. wire [(WB_DW*WB_N)-1:0] wb_rdata_flat;
  93. wire [WB_N-1:0] wb_cyc;
  94. wire wb_we;
  95. wire [WB_N-1:0] wb_ack;
  96. // UART
  97. // USB Core
  98. // EP Buffer
  99. wire [ 8:0] ep_tx_addr_0;
  100. wire [31:0] ep_tx_data_0;
  101. wire ep_tx_we_0;
  102. wire [ 8:0] ep_rx_addr_0;
  103. wire [31:0] ep_rx_data_1;
  104. wire ep_rx_re_0;
  105. // Bus interface
  106. wire [11:0] ub_addr;
  107. wire [15:0] ub_wdata;
  108. wire [15:0] ub_rdata;
  109. wire ub_cyc;
  110. wire ub_we;
  111. wire ub_ack;
  112. // SPI
  113. wire [7:0] sb_addr;
  114. wire [7:0] sb_di;
  115. wire [7:0] sb_do;
  116. wire sb_rw;
  117. wire sb_stb;
  118. wire sb_ack;
  119. wire sb_irq;
  120. wire sb_wkup;
  121. wire sio_miso_o, sio_miso_oe, sio_miso_i;
  122. wire sio_mosi_o, sio_mosi_oe, sio_mosi_i;
  123. wire sio_clk_o, sio_clk_oe, sio_clk_i;
  124. wire [3:0] sio_csn_o, sio_csn_oe;
  125. // LEDs
  126. reg [4:0] led_ctrl;
  127. wire [2:0] rgb_pwm;
  128. // WarmBoot
  129. reg boot_now;
  130. reg [1:0] boot_sel;
  131. // Clock / Reset logic
  132. wire clk_24m;
  133. wire clk_48m;
  134. wire rst;
  135. // SoC
  136. // ---
  137. // CPU
  138. picorv32 #(
  139. .PROGADDR_RESET(32'h 0000_0000),
  140. .STACKADDR(32'h 0000_0400),
  141. .BARREL_SHIFTER(0),
  142. .COMPRESSED_ISA(0),
  143. .ENABLE_COUNTERS(0),
  144. .ENABLE_MUL(0),
  145. .ENABLE_DIV(0),
  146. .ENABLE_IRQ(0),
  147. .ENABLE_IRQ_QREGS(0),
  148. .CATCH_MISALIGN(0),
  149. .CATCH_ILLINSN(0)
  150. ) cpu_I (
  151. .clk (clk_24m),
  152. .resetn (~rst),
  153. .mem_valid (mem_valid),
  154. .mem_instr (mem_instr),
  155. .mem_ready (mem_ready),
  156. .mem_addr (mem_addr),
  157. .mem_wdata (mem_wdata),
  158. .mem_wstrb (mem_wstrb),
  159. .mem_rdata (mem_rdata)
  160. );
  161. // Bus interface
  162. bridge #(
  163. .WB_N(WB_N),
  164. .WB_DW(WB_DW),
  165. .WB_AW(WB_AW),
  166. .WB_AI(WB_AI)
  167. ) pb_I (
  168. .pb_addr(mem_addr),
  169. .pb_rdata(mem_rdata),
  170. .pb_wdata(mem_wdata),
  171. .pb_wstrb(mem_wstrb),
  172. .pb_valid(mem_valid),
  173. .pb_ready(mem_ready),
  174. .bram_addr(bram_addr),
  175. .bram_rdata(bram_rdata),
  176. .bram_wdata(bram_wdata),
  177. .bram_wmsk(bram_wmsk),
  178. .bram_we(bram_we),
  179. .spram_addr(spram_addr),
  180. .spram_rdata(spram_rdata),
  181. .spram_wdata(spram_wdata),
  182. .spram_wmsk(spram_wmsk),
  183. .spram_we(spram_we),
  184. .wb_addr(wb_addr),
  185. .wb_wdata(wb_wdata),
  186. .wb_wmsk(wb_wmsk),
  187. .wb_rdata(wb_rdata_flat),
  188. .wb_cyc(wb_cyc),
  189. .wb_we(wb_we),
  190. .wb_ack(wb_ack),
  191. .clk(clk_24m),
  192. .rst(rst)
  193. );
  194. for (i=0; i<WB_N; i=i+1)
  195. assign wb_rdata_flat[i*WB_DW+:WB_DW] = wb_rdata[i];
  196. assign wb_rdata[0] = 0;
  197. assign wb_ack[0] = wb_cyc[0];
  198. // Boot memory
  199. soc_bram #(
  200. .INIT_FILE("boot.hex")
  201. ) bram_I (
  202. .addr(bram_addr),
  203. .rdata(bram_rdata),
  204. .wdata(bram_wdata),
  205. .wmsk(bram_wmsk),
  206. .we(bram_we),
  207. .clk(clk_24m)
  208. );
  209. // Main memory
  210. soc_spram #(
  211. .AW(SPRAM_AW)
  212. ) spram_I (
  213. .addr(spram_addr[SPRAM_AW-1:0]),
  214. .rdata(spram_rdata),
  215. .wdata(spram_wdata),
  216. .wmsk(spram_wmsk),
  217. .we(spram_we),
  218. .clk(clk_24m)
  219. );
  220. // UART
  221. // ----
  222. uart_wb #(
  223. .DIV_WIDTH(12),
  224. .DW(WB_DW)
  225. ) uart_I (
  226. .uart_tx(uart_tx),
  227. .uart_rx(uart_rx),
  228. .wb_addr(wb_addr[1:0]),
  229. .wb_rdata(wb_rdata[1]),
  230. .wb_we(wb_we),
  231. .wb_wdata(wb_wdata),
  232. .wb_cyc(wb_cyc[1]),
  233. .wb_ack(wb_ack[1]),
  234. .clk(clk_24m),
  235. .rst(rst)
  236. );
  237. // SPI
  238. // ---
  239. // Hard-IP
  240. `ifndef SIM
  241. SB_SPI #(
  242. .BUS_ADDR74("0b0000")
  243. ) spi_I (
  244. .SBCLKI(clk_24m),
  245. .SBRWI(sb_rw),
  246. .SBSTBI(sb_stb),
  247. .SBADRI7(sb_addr[7]),
  248. .SBADRI6(sb_addr[6]),
  249. .SBADRI5(sb_addr[5]),
  250. .SBADRI4(sb_addr[4]),
  251. .SBADRI3(sb_addr[3]),
  252. .SBADRI2(sb_addr[2]),
  253. .SBADRI1(sb_addr[1]),
  254. .SBADRI0(sb_addr[0]),
  255. .SBDATI7(sb_di[7]),
  256. .SBDATI6(sb_di[6]),
  257. .SBDATI5(sb_di[5]),
  258. .SBDATI4(sb_di[4]),
  259. .SBDATI3(sb_di[3]),
  260. .SBDATI2(sb_di[2]),
  261. .SBDATI1(sb_di[1]),
  262. .SBDATI0(sb_di[0]),
  263. .MI(sio_miso_i),
  264. .SI(sio_mosi_i),
  265. .SCKI(sio_clk_i),
  266. .SCSNI(1'b1),
  267. .SBDATO7(sb_do[7]),
  268. .SBDATO6(sb_do[6]),
  269. .SBDATO5(sb_do[5]),
  270. .SBDATO4(sb_do[4]),
  271. .SBDATO3(sb_do[3]),
  272. .SBDATO2(sb_do[2]),
  273. .SBDATO1(sb_do[1]),
  274. .SBDATO0(sb_do[0]),
  275. .SBACKO(sb_ack),
  276. .SPIIRQ(sb_irq),
  277. .SPIWKUP(sb_wkup),
  278. .SO(sio_miso_o),
  279. .SOE(sio_miso_oe),
  280. .MO(sio_mosi_o),
  281. .MOE(sio_mosi_oe),
  282. .SCKO(sio_clk_o),
  283. .SCKOE(sio_clk_oe),
  284. .MCSNO3(sio_csn_o[3]),
  285. .MCSNO2(sio_csn_o[2]),
  286. .MCSNO1(sio_csn_o[1]),
  287. .MCSNO0(sio_csn_o[0]),
  288. .MCSNOE3(sio_csn_oe[3]),
  289. .MCSNOE2(sio_csn_oe[2]),
  290. .MCSNOE1(sio_csn_oe[1]),
  291. .MCSNOE0(sio_csn_oe[0])
  292. );
  293. `else
  294. reg [3:0] sim;
  295. assign sb_ack = sb_stb;
  296. assign sb_do = { sim, 4'h8 };
  297. always @(posedge clk_24m)
  298. if (rst)
  299. sim <= 0;
  300. else if (sb_ack & sb_rw)
  301. sim <= sim + 1;
  302. `endif
  303. // IO pads
  304. SB_IO #(
  305. .PIN_TYPE(6'b101001),
  306. .PULLUP(1'b1)
  307. ) spi_io_I[2:0] (
  308. .PACKAGE_PIN ({spi_mosi, spi_miso, spi_clk }),
  309. .OUTPUT_ENABLE({sio_mosi_oe, sio_miso_oe, sio_clk_oe}),
  310. .D_OUT_0 ({sio_mosi_o, sio_miso_o, sio_clk_o }),
  311. .D_IN_0 ({sio_mosi_i, sio_miso_i, sio_clk_i })
  312. );
  313. // Bypass OE for CS_n lines
  314. assign spi_flash_cs_n = sio_csn_o[0];
  315. `ifdef HAS_PSRAM
  316. assign spi_ram_cs_n = sio_csn_o[1];
  317. `endif
  318. // Bus interface
  319. assign sb_addr = { 4'h0, wb_addr[3:0] };
  320. assign sb_di = wb_wdata[7:0];
  321. assign sb_rw = wb_we;
  322. assign sb_stb = wb_cyc[2];
  323. assign wb_rdata[2] = { {(WB_DW-8){1'b0}}, wb_cyc[2] ? sb_do : 8'h00 };
  324. assign wb_ack[2] = sb_ack;
  325. // LEDs
  326. // ----
  327. SB_LEDDA_IP led_I (
  328. .LEDDCS(wb_addr[4] & wb_we),
  329. .LEDDCLK(clk_24m),
  330. .LEDDDAT7(wb_wdata[7]),
  331. .LEDDDAT6(wb_wdata[6]),
  332. .LEDDDAT5(wb_wdata[5]),
  333. .LEDDDAT4(wb_wdata[4]),
  334. .LEDDDAT3(wb_wdata[3]),
  335. .LEDDDAT2(wb_wdata[2]),
  336. .LEDDDAT1(wb_wdata[1]),
  337. .LEDDDAT0(wb_wdata[0]),
  338. .LEDDADDR3(wb_addr[3]),
  339. .LEDDADDR2(wb_addr[2]),
  340. .LEDDADDR1(wb_addr[1]),
  341. .LEDDADDR0(wb_addr[0]),
  342. .LEDDDEN(wb_cyc[3]),
  343. .LEDDEXE(led_ctrl[1]),
  344. .PWMOUT0(rgb_pwm[0]),
  345. .PWMOUT1(rgb_pwm[1]),
  346. .PWMOUT2(rgb_pwm[2]),
  347. .LEDDON()
  348. );
  349. SB_RGBA_DRV #(
  350. .CURRENT_MODE("0b1"),
  351. .RGB0_CURRENT("0b000001"),
  352. .RGB1_CURRENT("0b000001"),
  353. .RGB2_CURRENT("0b000001")
  354. ) rgb_drv_I (
  355. .RGBLEDEN(led_ctrl[2]),
  356. .RGB0PWM(rgb_pwm[0]),
  357. .RGB1PWM(rgb_pwm[1]),
  358. .RGB2PWM(rgb_pwm[2]),
  359. .CURREN(led_ctrl[3]),
  360. .RGB0(rgb[0]),
  361. .RGB1(rgb[1]),
  362. .RGB2(rgb[2])
  363. );
  364. always @(posedge clk_24m or posedge rst)
  365. if (rst)
  366. led_ctrl <= 0;
  367. else if (wb_cyc[3] & ~wb_addr[4] & wb_we)
  368. led_ctrl <= wb_wdata[4:0];
  369. assign wb_rdata[3] = { WB_DW{1'b0} };
  370. assign wb_ack[3] = wb_cyc[3];
  371. // USB Core
  372. // --------
  373. // Core
  374. usb #(
  375. .EPDW(32)
  376. ) usb_I (
  377. .pad_dp(usb_dp),
  378. .pad_dn(usb_dn),
  379. .pad_pu(usb_pu),
  380. .ep_tx_addr_0(ep_tx_addr_0),
  381. .ep_tx_data_0(ep_tx_data_0),
  382. .ep_tx_we_0(ep_tx_we_0),
  383. .ep_rx_addr_0(ep_rx_addr_0),
  384. .ep_rx_data_1(ep_rx_data_1),
  385. .ep_rx_re_0(ep_rx_re_0),
  386. .ep_clk(clk_24m),
  387. .wb_addr(ub_addr),
  388. .wb_rdata(ub_rdata),
  389. .wb_wdata(ub_wdata),
  390. .wb_we(ub_we),
  391. .wb_cyc(ub_cyc),
  392. .wb_ack(ub_ack),
  393. .clk(clk_48m),
  394. .rst(rst)
  395. );
  396. // Cross clock bridge
  397. xclk_wb #(
  398. .DW(16),
  399. .AW(12)
  400. ) wb_48m_xclk_I (
  401. .s_addr(wb_addr[11:0]),
  402. .s_wdata(wb_wdata[15:0]),
  403. .s_rdata(wb_rdata[4][15:0]),
  404. .s_cyc(wb_cyc[4]),
  405. .s_ack(wb_ack[4]),
  406. .s_we(wb_we),
  407. .s_clk(clk_24m),
  408. .m_addr(ub_addr),
  409. .m_wdata(ub_wdata),
  410. .m_rdata(ub_rdata),
  411. .m_cyc(ub_cyc),
  412. .m_ack(ub_ack),
  413. .m_we(ub_we),
  414. .m_clk(clk_48m),
  415. .rst(rst)
  416. );
  417. assign wb_rdata[4][31:16] = 16'h0000;
  418. // EP buffer interface
  419. reg wb_ack_ep;
  420. always @(posedge clk_24m)
  421. wb_ack_ep <= wb_cyc[5] & ~wb_ack_ep;
  422. assign wb_ack[5] = wb_ack_ep;
  423. assign ep_tx_addr_0 = wb_addr[8:0];
  424. assign ep_tx_data_0 = wb_wdata;
  425. assign ep_tx_we_0 = wb_cyc[5] & ~wb_ack[5] & wb_we;
  426. assign ep_rx_addr_0 = wb_addr[8:0];
  427. assign ep_rx_re_0 = 1'b1;
  428. assign wb_rdata[5] = wb_cyc[5] ? ep_rx_data_1 : 32'h00000000;
  429. // Warm Boot
  430. // ---------
  431. // Bus interface
  432. always @(posedge clk_24m or posedge rst)
  433. if (rst) begin
  434. boot_now <= 1'b0;
  435. boot_sel <= 2'b00;
  436. end else if (wb_cyc[0] & wb_we & (wb_addr[2:0] == 3'b000)) begin
  437. boot_now <= wb_wdata[2];
  438. boot_sel <= wb_wdata[1:0];
  439. end
  440. // Helper
  441. dfu_helper #(
  442. .TIMER_WIDTH(24),
  443. .BTN_MODE(3),
  444. .DFU_MODE(0)
  445. ) dfu_helper_I (
  446. .boot_now(boot_now),
  447. .boot_sel(boot_sel),
  448. .btn_pad(btn),
  449. .btn_val(),
  450. .rst_req(),
  451. .clk(clk_24m),
  452. .rst(rst)
  453. );
  454. // Clock / Reset
  455. // -------------
  456. `ifdef SIM
  457. reg clk_48m_s = 1'b0;
  458. reg clk_24m_s = 1'b0;
  459. reg rst_s = 1'b1;
  460. always #10.42 clk_48m_s <= !clk_48m_s;
  461. always #20.84 clk_24m_s <= !clk_24m_s;
  462. initial begin
  463. #200 rst_s = 0;
  464. end
  465. assign clk_48m = clk_48m_s;
  466. assign clk_24m = clk_24m_s;
  467. assign rst = rst_s;
  468. `else
  469. sysmgr sys_mgr_I (
  470. .clk_in(clk_in),
  471. .rst_in(1'b0),
  472. .clk_48m(clk_48m),
  473. .clk_24m(clk_24m),
  474. .rst_out(rst)
  475. );
  476. `endif
  477. endmodule // top