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- `timescale 1ns / 1ps
- module top(
- input CLK,
- input BTN1,
- input BTN2,
- input BTN3,
- input BTN_N,
-
- output [4:0] led
-
-
- );
- reg [4:0]desired_led;
- assign led=desired_led;
- always @(posedge CLK) begin
- desired_led[0] = BTN1 & BTN2 & BTN3;
- desired_led[1] = BTN1;
- desired_led[2] = BTN2;
- desired_led[3] = BTN3;
- desired_led[4] = !BTN_N;
- end
-
- endmodule
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