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- `default_nettype none
- module top (
-
- output wire hdmi_clk,
- output wire hdmi_hsync,
- output wire hdmi_vsync,
- output wire hdmi_de,
- output wire hdmi_r,
- output wire hdmi_g,
- output wire hdmi_b,
- output wire hdmi_i,
-
- input wire slave_mosi,
- output wire slave_miso,
- input wire slave_cs_n,
- input wire slave_clk,
-
- input wire clk12m_in
- );
-
-
-
- wire [15:0] fbus_addr;
- wire [15:0] fbus_din;
- wire [15:0] fbus_dout;
- wire fbus_cyc;
- wire fbus_we;
- wire fbus_ack;
-
- wire [7:0] sb_addr;
- wire [7:0] sb_data;
- wire sb_first;
- wire sb_last;
- wire sb_stb;
- wire [7:0] sb_out;
-
- reg [31:0] data;
- reg pending;
-
- wire clk_2x;
- wire clk_1x;
- wire rst;
-
-
- spi_fast spi_I (
- .spi_mosi(slave_mosi),
- .spi_miso(slave_miso),
- .spi_cs_n(slave_cs_n),
- .spi_clk(slave_clk),
- .addr(sb_addr),
- .data(sb_data),
- .first(sb_first),
- .last(sb_last),
- .strobe(sb_stb),
- .out(sb_out),
- .clk(clk_1x),
- .rst(rst)
- );
-
-
- assign fbus_din = data[15:0];
- assign fbus_addr = data[31:16];
- assign fbus_cyc = pending;
- assign fbus_we = 1'b1;
- always @(posedge clk_1x)
- if (rst)
- pending <= 1'b0;
- else
- pending <= (pending & ~fbus_ack) | (sb_last & sb_stb & |(data[24:22]));
- always @(posedge clk_1x)
- if (sb_stb & ~pending)
- data <= { data[24:0], sb_data };
-
-
- hdmi_text_2x #(
- .DW(4)
- ) text_I (
- .hdmi_data({hdmi_i, hdmi_b, hdmi_g, hdmi_r}),
- .hdmi_hsync(hdmi_hsync),
- .hdmi_vsync(hdmi_vsync),
- .hdmi_de(hdmi_de),
- .hdmi_clk(hdmi_clk),
- .bus_addr(fbus_addr),
- .bus_din(fbus_din),
- .bus_dout(fbus_dout),
- .bus_cyc(fbus_cyc),
- .bus_we(fbus_we),
- .bus_ack(fbus_ack),
- .clk_1x(clk_1x),
- .clk_2x(clk_2x),
- .rst(rst)
- );
-
-
- sysmgr sysmgr_I (
- .clk_in(clk12m_in),
- .rst_in(1'b0),
- .clk_2x_out(clk_2x),
- .clk_1x_out(clk_1x),
- .rst_out(rst)
- );
- endmodule
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