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- `default_nettype none
- module pkt_mux #(
- parameter integer N = 3
- )(
-
- input wire [8*N-1:0] pkt_data,
- input wire [ N-1:0] pkt_last,
- input wire [ N-1:0] pkt_valid,
- output wire [ N-1:0] pkt_ack,
-
- output wire [7:0] hs_data,
- output wire hs_start,
- output wire hs_last,
- output wire hs_clk_req,
- input wire hs_clk_rdy,
-
- input wire clk,
- input wire rst
- );
-
-
-
- localparam
- ST_CLK_OFF = 0,
- ST_CLK_BOOT = 1,
- ST_CLK_RUN = 2,
- ST_STREAM = 3,
- ST_EOTP = 4;
- reg [2:0] fsm_state;
- reg [2:0] fsm_state_next;
-
- reg [7:0] eotp_data;
- reg [1:0] eotp_cnt;
- reg eotp_last;
-
-
-
-
- always @(posedge clk)
- if (rst)
- fsm_state <= ST_CLK_OFF;
- else
- fsm_state <= fsm_state_next;
-
- always @(*)
- begin
-
- fsm_state_next = fsm_state;
-
- case (fsm_state)
- ST_CLK_OFF:
- if ( )
- fsm_state_next = ST_STREAM;
- ST_CLK_BOOT:
- if (hs_clk_rdy)
- fsm_state_next = ST_CLK_RUN;
- ST_CLK_RUN:
- if (hs_clk_timeout)
- fsm_state_next = ST_CLK_OFF;
- else if ( )
- fsm_state_next = ST_STREAM;
- ST_STREAM:
- if ( )
- fsm_state_next = ST_EOTP;
- ST_EOTP:
- if (hs_ack & eotp_last)
- fsm_state_next = ST_CLK_RUN;
- endcase
- end
-
-
- always @(posedge clk)
- if (fsm_state != ST_EOTP) begin
- eotp_cnt <= 2'b00;
- eotp_last <= 1'b0;
- end else if (hs_ack) begin
- eotp_cnt <= eotp_cnt + 1;
- eotp_last <= (eotp_cnt == 2'b10);
- end
- always @(eotp_cnt)
- case (eotp_cnt)
- 2'b00: eotp_data = 8'h08;
- 2'b01: eotp_data = 8'h0f;
- 2'b10: eotp_data = 8'h0f;
- 2'b11: eotp_data = 8'h01;
- endcase
-
-
- reg [15:0] hs_clk_timer;
- wire hs_clk_timeout;
-
- assign hs_clk_req = (fsm_state != ST_CLK_OFF);
-
- always @(posedge clk)
- if (fsm_state != ST_CLK_RUN)
- hs_clk_timer <= 0;
- else if (~hs_clk_timeout)
- hs_clk_timer <= hs_clk_timer + 1
- assign hs_clk_timeout <= hs_clk_timer[15];
-
-
-
-
- input wire [8*N-1:0] pkt_data,
- input wire [ N-1:0] pkt_last,
- input wire [ N-1:0] pkt_valid,
- output wire [ N-1:0] pkt_ack,
-
-
- endmodule
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