123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116 |
- `default_nettype none
- module pkt_spi_write #(
- parameter BASE = 8'h20
- )(
-
- input wire [7:0] sb_addr,
- input wire [7:0] sb_data,
- input wire sb_first,
- input wire sb_last,
- input wire sb_strobe,
-
- output reg [7:0] fifo_data,
- output reg fifo_last,
- output reg fifo_wren,
- input wire fifo_full,
-
- input wire clk,
- input wire rst
- );
-
- reg [7:0] data;
- reg first;
- reg last;
- reg [2:0] cnt;
- reg [7:0] data_mux;
- reg hit_ena;
- reg hit_type;
- reg hit_ext;
-
- always @(posedge clk)
- begin
- hit_ena <= sb_strobe & (sb_addr[7:1] == (BASE >> 1));
- hit_type <= sb_addr[0] & cnt[2] & ~sb_first;
- hit_ext <= hit_ena & hit_type;
- end
-
- always @(posedge clk)
- if (sb_strobe) begin
- data <= sb_data;
- first <= sb_first;
- last <= sb_last;
- end
-
- always @(posedge clk)
- if (sb_strobe) begin
- if (sb_first)
- cnt <= 0;
- else
- cnt <= cnt + { 3'b000, ~cnt[2] };
- end
-
- always @(*)
- if (~hit_type)
-
- data_mux = data;
- else if (~hit_ext)
-
- data_mux = { data[5:3], data[2:0], data[2:1] };
- else
-
- data_mux = { data[7:6], data[7:6], data[7], data[5:3] };
-
- always @(posedge clk)
- begin
- fifo_data <= data_mux;
- fifo_last <= last & (~hit_type | hit_ext);
- fifo_wren <= hit_ena | hit_ext;
- end
- endmodule
|