| .. |
|
3signal.v
|
2ba5998af1
freq increase voodoo
|
hace 21 horas |
|
boards.vh
|
67143eeaae
projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0
|
hace 4 años |
|
button.v
|
a310b26df0
add initial version of button logic + dummy usage
|
hace 6 días |
|
dfu_helper.v
|
b5c7b7ef93
projects/riscv_usb: Update to latest dfu_helper
|
hace 4 años |
|
mailbox_wb_rtl2sw.v
|
506cdd9e8d
Fix mailboxes to support overwrites and precedence over SW to RTL writes. Add more control code to SW.
|
hace 19 horas |
|
mailbox_wb_sw2rtl.v
|
506cdd9e8d
Fix mailboxes to support overwrites and precedence over SW to RTL writes. Add more control code to SW.
|
hace 19 horas |
|
picorv32.v
|
345435957f
projects/riscv_usb: Add iCE40 specific implementation of register file
|
hace 4 años |
|
picorv32_ice40_regs.v
|
345435957f
projects/riscv_usb: Add iCE40 specific implementation of register file
|
hace 4 años |
|
soc_bram.v
|
637d035474
projects: Add no_rw_checks on the soc_bram instances
|
hace 1 año |
|
soc_picorv32_base.v
|
30e995fcc2
Add timer expiring in SW.
|
hace 4 días |
|
soc_picorv32_bridge.v
|
b7d87eaa5a
Fix bridging logic. Hangups are gone. Wrong offset in register map still persits.
|
hace 2 semanas |
|
soc_spram.v
|
14597759d5
projects/riscv_usb: Whitespace fixes for soc_{bram,spram}
|
hace 4 años |
|
soc_usb.v
|
fc12f0de48
projects/riscv_usb: Move the USB stuff to a separate module
|
hace 4 años |
|
sysmgr.v
|
67143eeaae
projects/riscv_usb: Relicense RTL under CERN-OHL-P-2.0
|
hace 4 años |
|
top.v
|
506cdd9e8d
Fix mailboxes to support overwrites and precedence over SW to RTL writes. Add more control code to SW.
|
hace 19 horas |
Jakub Duchniewicz
506cdd9e8d
Fix mailboxes to support overwrites and precedence over SW to RTL writes. Add more control code to SW.