Jakub Duchniewicz 506cdd9e8d Fix mailboxes to support overwrites and precedence over SW to RTL writes. Add more control code to SW.		пре 15 часа
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data	773483ddac faster clocks for synthesis (not changing actual freq)	пре 1 недеља
fw	506cdd9e8d Fix mailboxes to support overwrites and precedence over SW to RTL writes. Add more control code to SW.	пре 15 часа
rtl	506cdd9e8d Fix mailboxes to support overwrites and precedence over SW to RTL writes. Add more control code to SW.	пре 15 часа
sim	f560755b26 projects/riscv_usb: Add support for the user button	пре 4 година
Makefile	827f19c8b2 Distinguish between two kinds of mailboxes RTL2SW and SW2RTL.	пре 1 дан
README.md	fd6a09e0c2 projects/riscv_usb: Fixup the README	пре 1 година

RISC-V + USB core demo

For the icebreaker, the hardware connections are :

To run :

Build and flash the bitstream
- This will build fw/boot.hex and include it as the BRAM initial data
Flash the main application code in SPI at offset 1M
- make -C fw prog
Connect to the iCEBreaker uart console (ttyUSB1) with a 1M baudrate
- and then at the Command> prompt, press c for 'connect'. This will start the USB detection and device should enumerate