| .. |
|
bridge.v
|
b9622164c0
projects/riscv_usb: Add optional register stages in PicoRV -> WB bridge
|
%!s(int64=5) %!d(string=hai) anos |
|
picorv32.v
|
9cf400b9ad
projects/riscv_usb: Import RISCV + USB prototype
|
%!s(int64=6) %!d(string=hai) anos |
|
soc_bram.v
|
9cf400b9ad
projects/riscv_usb: Import RISCV + USB prototype
|
%!s(int64=6) %!d(string=hai) anos |
|
soc_spram.v
|
9cf400b9ad
projects/riscv_usb: Import RISCV + USB prototype
|
%!s(int64=6) %!d(string=hai) anos |
|
sysmgr.v
|
9cf400b9ad
projects/riscv_usb: Import RISCV + USB prototype
|
%!s(int64=6) %!d(string=hai) anos |
|
top.v
|
4fe4a453e8
projects/riscv_usb: Add WARMBOOT support
|
%!s(int64=5) %!d(string=hai) anos |
Sylvain Munaut
4fe4a453e8
projects/riscv_usb: Add WARMBOOT support