hdb3_dec.v 2.0 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889
  1. /*
  2. * hdb3_dec.v
  3. *
  4. * vim: ts=4 sw=4
  5. *
  6. * HDB3 symbols -> bit decoding as described in G.703
  7. *
  8. *
  9. * Copyright (C) 2019 Sylvain Munaut <tnt@246tNt.com>
  10. * All rights reserved.
  11. *
  12. * LGPL v3+, see LICENSE.lgpl3
  13. *
  14. * This program is free software; you can redistribute it and/or
  15. * modify it under the terms of the GNU Lesser General Public
  16. * License as published by the Free Software Foundation; either
  17. * version 3 of the License, or (at your option) any later version.
  18. *
  19. * This program is distributed in the hope that it will be useful,
  20. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  21. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  22. * Lesser General Public License for more details.
  23. *
  24. * You should have received a copy of the GNU Lesser General Public License
  25. * along with this program; if not, write to the Free Software Foundation,
  26. * Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
  27. */
  28. `default_nettype none
  29. module hdb3_dec (
  30. // Input
  31. input wire in_pos,
  32. input wire in_neg,
  33. input wire in_valid,
  34. // Output
  35. output wire out_data,
  36. output reg out_valid,
  37. // Common
  38. input wire clk,
  39. input wire rst
  40. );
  41. // Signals
  42. wire violation;
  43. reg [3:0] data;
  44. reg pstate; // Pulse state
  45. // Output
  46. assign out_data = data[3];
  47. always @(posedge clk)
  48. out_valid <= in_valid;
  49. // Main logic
  50. assign violation = (in_pos & pstate) | (in_neg & ~pstate);
  51. always @(posedge clk)
  52. begin
  53. if (rst) begin
  54. // Reset state
  55. data <= 4'h0;
  56. pstate <= 1'b0;
  57. end else if (in_valid) begin
  58. if (in_pos ^ in_neg) begin
  59. // Is it a violation ?
  60. if (violation) begin
  61. // Violation
  62. data <= 4'h0;
  63. pstate <= pstate;
  64. end else begin
  65. // Normal data (or possibly balancing pulse that will be
  66. // post-corrected)
  67. data <= { data[2:0], 1'b1 };
  68. pstate <= pstate ^ 1;
  69. end
  70. end else begin
  71. // Zero (or error, we map to 0)
  72. data <= { data[2:0], 1'b0 };
  73. pstate <= pstate;
  74. end
  75. end
  76. end
  77. endmodule // hdb3_dec