boards.vh 1.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657
  1. /*
  2. * boards.vh
  3. *
  4. * vim: ts=4 sw=4 syntax=verilog
  5. *
  6. * Copyright (C) 2021 Sylvain Munaut <tnt@246tNt.com>
  7. * SPDX-License-Identifier: CERN-OHL-P-2.0
  8. */
  9. `ifdef BOARD_BITSY_V0
  10. // 1bitsquared iCEbreaker bitsy prototypes (v0.x)
  11. `define HAS_USB
  12. `elsif BOARD_BITSY_V1
  13. // 1bitsquared iCEbreaker bitsy prod (v1.x)
  14. `define HAS_USB
  15. `elsif BOARD_REDIP_SID
  16. // reDIP-SID
  17. `define HAS_USB
  18. `define PLL_CORE
  19. `define PLL_CUSTOM
  20. `define PLL_FILTER_RANGE 3'b010
  21. `define PLL_DIVR 4'b0000
  22. `define PLL_DIVF 7'b0010111
  23. `define PLL_DIVQ 3'b010
  24. `endif
  25. // Defaults
  26. // If no USB, use UART
  27. `ifndef HAS_USB
  28. `define HAS_UART
  29. `endif
  30. // PLL params
  31. `ifndef PLL_CUSTOM
  32. `define PLL_FILTER_RANGE 3'b001
  33. `define PLL_DIVR 4'b0000
  34. // 48
  35. // `define PLL_DIVF 7'b0111111
  36. // `define PLL_DIVQ 3'b100
  37. // 96
  38. // `define PLL_DIVF 7'b0111111
  39. // `define PLL_DIVQ 3'b011
  40. // 144
  41. // `define PLL_DIVF 7'b0101111
  42. // `define PLL_DIVQ 3'b010
  43. // 147
  44. `define PLL_DIVF 7'b0110000
  45. `define PLL_DIVQ 3'b010
  46. // 200
  47. // `define PLL_DIVF 7'b1000010
  48. // `define PLL_DIVQ 3'b010
  49. `endif