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bridge.v
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b9622164c0
projects/riscv_usb: Add optional register stages in PicoRV -> WB bridge
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%!s(int64=5) %!d(string=hai) anos |
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picorv32.v
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9cf400b9ad
projects/riscv_usb: Import RISCV + USB prototype
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%!s(int64=6) %!d(string=hai) anos |
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soc_bram.v
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9cf400b9ad
projects/riscv_usb: Import RISCV + USB prototype
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%!s(int64=6) %!d(string=hai) anos |
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soc_spram.v
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9cf400b9ad
projects/riscv_usb: Import RISCV + USB prototype
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%!s(int64=6) %!d(string=hai) anos |
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sysmgr.v
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9cf400b9ad
projects/riscv_usb: Import RISCV + USB prototype
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%!s(int64=6) %!d(string=hai) anos |
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top.v
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6f6311c8fb
projects/riscv_usb: Add support for write mask to WB bus
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%!s(int64=5) %!d(string=hai) anos |
Sylvain Munaut
b9622164c0
projects/riscv_usb: Add optional register stages in PicoRV -> WB bridge