top.v 8.4 KB

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  1. /*
  2. * top.v
  3. *
  4. * vim: ts=4 sw=4
  5. *
  6. * Copyright (C) 2019-2020 Sylvain Munaut <tnt@246tNt.com>
  7. * SPDX-License-Identifier: CERN-OHL-P-2.0
  8. */
  9. `default_nettype none
  10. `include "boards.vh"
  11. module top (
  12. // SPI
  13. inout wire spi_mosi,
  14. inout wire spi_miso,
  15. inout wire spi_clk,
  16. output wire spi_flash_cs_n,
  17. `ifdef HAS_PSRAM
  18. output wire spi_ram_cs_n,
  19. `endif
  20. // USB TODO: remove later
  21. inout wire usb_dp,
  22. inout wire usb_dn,
  23. output wire usb_pu,
  24. // Debug UART
  25. input wire uart_rx,
  26. output wire uart_tx,
  27. // Buttons (2 for now to test up and down)
  28. input wire btn_n,
  29. input wire btn_1,
  30. input wire btn_2,
  31. // LEDs to blink to show that a value change has been registered?
  32. output wire[4:0] led,
  33. // GPIOs for out signal
  34. output wire out1,
  35. output wire out2,
  36. output wire out3,
  37. // LED TODO: remove later
  38. output wire [2:0] rgb,
  39. // Clock
  40. input wire clk_in
  41. );
  42. localparam integer SPRAM_AW = 14; /* 14 => 64k, 15 => 128k */
  43. localparam integer WB_N = 7; // TODO: Reduce
  44. localparam integer WB_DW = 32;
  45. localparam integer WB_AW = 16;
  46. localparam integer WB_RW = WB_DW * WB_N;
  47. localparam integer WB_MW = WB_DW / 8;
  48. localparam integer FAST_PWM_WIDTH = 8;
  49. localparam integer PULSE_COUNTER_WIDTH = 8;
  50. localparam integer SLOW_PWM_WIDTH = 14;
  51. genvar i;
  52. // Signals
  53. // -------
  54. // Wishbone
  55. wire [WB_AW-1:0] wb_addr;
  56. wire [WB_DW-1:0] wb_rdata [0:WB_N-1];
  57. wire [WB_RW-1:0] wb_rdata_flat;
  58. wire [WB_DW-1:0] wb_wdata;
  59. wire [WB_MW-1:0] wb_wmsk;
  60. wire [WB_N -1:0] wb_cyc;
  61. wire wb_we;
  62. wire [WB_N -1:0] wb_ack;
  63. // WarmBoot
  64. reg boot_now;
  65. reg [1:0] boot_sel;
  66. // Clock / Reset logic
  67. wire clk_24m;
  68. wire clk_48m;
  69. wire rst;
  70. // 3 signal
  71. wire [SLOW_PWM_WIDTH-1:0] period1;
  72. wire [SLOW_PWM_WIDTH-1:0] delay1;
  73. wire [SLOW_PWM_WIDTH-1:0] duty2;
  74. wire [SLOW_PWM_WIDTH-1:0] delay2;
  75. wire [FAST_PWM_WIDTH-1:0] period3;
  76. wire [FAST_PWM_WIDTH-1:0] duty3;
  77. wire [SLOW_PWM_WIDTH-1:0] delay3;
  78. wire [PULSE_COUNTER_WIDTH-1:0] npuls3;
  79. wire [1:0] odd_train_flag;
  80. wire ena_odd_out3;
  81. // Mailbox signal wires
  82. wire [16*16-1:0] mailbox_regs_flat; // Flattened register array (16 registers of 16 bits each)
  83. // SoC
  84. // ---
  85. soc_picorv32_base #(
  86. .WB_N (WB_N),
  87. .WB_DW (WB_DW),
  88. .WB_AW (WB_AW),
  89. .SPRAM_AW(SPRAM_AW)
  90. ) base_I (
  91. .wb_addr (wb_addr),
  92. .wb_rdata(wb_rdata_flat),
  93. .wb_wdata(wb_wdata),
  94. .wb_wmsk (wb_wmsk),
  95. .wb_we (wb_we),
  96. .wb_cyc (wb_cyc),
  97. .wb_ack (wb_ack),
  98. .clk (clk_24m),
  99. .rst (rst)
  100. );
  101. for (i=0; i<WB_N; i=i+1)
  102. assign wb_rdata_flat[i*WB_DW+:WB_DW] = wb_rdata[i];
  103. // UART [1]
  104. // ----
  105. uart_wb #(
  106. .DIV_WIDTH(12),
  107. .DW(WB_DW)
  108. ) uart_I (
  109. .uart_tx (uart_tx),
  110. .uart_rx (uart_rx),
  111. .wb_addr (wb_addr[1:0]),
  112. .wb_rdata (wb_rdata[1]),
  113. .wb_we (wb_we),
  114. .wb_wdata (wb_wdata),
  115. .wb_cyc (wb_cyc[1]),
  116. .wb_ack (wb_ack[1]),
  117. .clk (clk_24m),
  118. .rst (rst)
  119. );
  120. // SPI [2]
  121. // ---
  122. ice40_spi_wb #(
  123. `ifdef HAS_PSRAM
  124. .N_CS(2),
  125. `else
  126. .N_CS(1),
  127. `endif
  128. .WITH_IOB(1),
  129. .UNIT(0)
  130. ) spi_I (
  131. .pad_mosi (spi_mosi),
  132. .pad_miso (spi_miso),
  133. .pad_clk (spi_clk),
  134. `ifdef HAS_PSRAM
  135. .pad_csn ({spi_ram_cs_n, spi_flash_cs_n}),
  136. `else
  137. .pad_csn (spi_flash_cs_n),
  138. `endif
  139. .wb_addr (wb_addr[3:0]),
  140. .wb_rdata (wb_rdata[2]),
  141. .wb_wdata (wb_wdata),
  142. .wb_we (wb_we),
  143. .wb_cyc (wb_cyc[2]),
  144. .wb_ack (wb_ack[2]),
  145. .clk (clk_24m),
  146. .rst (rst)
  147. );
  148. // RGB LEDs [3]
  149. // --------
  150. ice40_rgb_wb #(
  151. .CURRENT_MODE("0b1"),
  152. .RGB0_CURRENT("0b000001"),
  153. .RGB1_CURRENT("0b000001"),
  154. .RGB2_CURRENT("0b000001")
  155. ) rgb_I (
  156. .pad_rgb (rgb),
  157. .wb_addr (wb_addr[4:0]),
  158. .wb_rdata (wb_rdata[3]),
  159. .wb_wdata (wb_wdata),
  160. .wb_we (wb_we),
  161. .wb_cyc (wb_cyc[3]),
  162. .wb_ack (wb_ack[3]),
  163. .clk (clk_24m),
  164. .rst (rst)
  165. );
  166. // USB [4 & 5]
  167. // ---
  168. /*soc_usb #(
  169. .DW(WB_DW)
  170. ) usb_I (
  171. .usb_dp (usb_dp),
  172. .usb_dn (usb_dn),
  173. .usb_pu (usb_pu),
  174. .wb_addr (wb_addr[11:0]),
  175. .wb_rdata (wb_rdata[4]),
  176. .wb_wdata (wb_wdata),
  177. .wb_we (wb_we),
  178. .wb_cyc (wb_cyc[5:4]),
  179. .wb_ack (wb_ack[5:4]),
  180. .clk_sys (clk_24m),
  181. .clk_48m (clk_48m),
  182. .rst (rst)
  183. );*/
  184. assign wb_rdata[4] = 0;
  185. assign wb_ack[5:4] = wb_cyc[5:4];
  186. assign wb_rdata[5] = 0;
  187. // WB Mailbox [6] TODO: this will move to lower addresses
  188. // ----------
  189. mailbox_wb #(
  190. .AW(4),
  191. .DW(WB_DW)
  192. ) mailbox_I (
  193. .clk(clk_24m),
  194. .rst(rst),
  195. .wb_addr(wb_addr[3:0]),
  196. .wb_wdata(wb_wdata),
  197. .wb_rdata(wb_rdata[6]),
  198. .wb_we(wb_we),
  199. .wb_cyc(wb_cyc[6]),
  200. .wb_ack(wb_ack[6]),
  201. .registers_flat(mailbox_regs_flat)
  202. );
  203. // 3 Signal
  204. // --------
  205. assign period1 = mailbox_regs_flat[15:0]; // First 16 bits for period1
  206. assign delay1 = mailbox_regs_flat[31:16]; // Next 16 bits for delay1
  207. assign duty2 = mailbox_regs_flat[47:32]; // Next 16 bits for duty2
  208. assign delay2 = mailbox_regs_flat[63:48]; // Next 16 bits for delay2
  209. assign period3 = mailbox_regs_flat[79:64]; // Next 16 bits for period3
  210. assign duty3 = mailbox_regs_flat[95:80]; // Next 16 bits for duty3
  211. assign delay3 = mailbox_regs_flat[111:96]; // Next 16 bits for delay3
  212. assign npuls3 = mailbox_regs_flat[127:112]; // Next 16 bits for npuls3
  213. assign odd_train_flag = mailbox_regs_flat[143:128]; // Next 16 bits for odd_train_flag
  214. assign ena_odd_out3 = mailbox_regs_flat[159:144]; // Next 16 bits for ena_odd_out3
  215. three_signal #(
  216. .FAST_PWM_WIDTH(FAST_PWM_WIDTH),
  217. .PULSE_COUNTER_WIDTH(PULSE_COUNTER_WIDTH),
  218. .SLOW_PWM_WIDTH(SLOW_PWM_WIDTH)
  219. ) three_signal_I(
  220. .nrst(~rst),
  221. .clk(clk_24m), // TODO: fix later we have CDC problem here
  222. .period1(period1),
  223. .delay1(delay1),
  224. .duty2(duty2),
  225. .delay2(delay2),
  226. .period3(period3),
  227. .duty3(duty3),
  228. .delay3(delay3),
  229. .npuls3(npuls3),
  230. .odd_train_flag(odd_train_flag),
  231. .ena_odd_out3(ena_odd_out3),
  232. .Out1(out1),
  233. .Out2(out2),
  234. .Out3(out3)
  235. );
  236. // TODO: dummy led onoff when value has been written
  237. always @(posedge clk_24m or posedge rst)
  238. if (rst) begin
  239. led[0] = 1'b0;
  240. led[1] = 1'b0;
  241. led[2] = 1'b0;
  242. end else if (period1 == 1) begin
  243. led[0] = 1'b1;
  244. led[1] = 1'b0;
  245. led[2] = 1'b0;
  246. end else if (period1 == 2) begin
  247. led[0] = 1'b0;
  248. led[1] = 1'b1;
  249. led[2] = 1'b0;
  250. end else if (period1 == 4) begin
  251. led[0] = 1'b0;
  252. led[1] = 1'b0;
  253. led[2] = 1'b1;
  254. end else if (period1 != 0) begin
  255. led[0] = 1'b1;
  256. led[1] = 1'b1;
  257. led[2] = 1'b1;
  258. end else begin
  259. led[0] = 1'b0;
  260. led[1] = 1'b0;
  261. led[2] = 1'b0;
  262. end
  263. always @(posedge clk_24m or posedge rst)
  264. if (rst) begin
  265. led[3] = 1'b0;
  266. end else if (btn_2) begin
  267. led[3] = 1'b1;
  268. end else begin
  269. led[3] = 1'b0;
  270. end
  271. //// TODO: dummy driving from delay1
  272. always @(posedge clk_24m or posedge rst)
  273. if (rst) begin
  274. led[4] = 1'b0;
  275. end else if (delay1 != 0) begin
  276. led[4] = 1'b1;
  277. end else begin
  278. led[4] = 1'b0;
  279. end
  280. //always @(posedge clk_48m or posedge rst)
  281. // if (rst) begin
  282. // led[3] = 1'b0;
  283. // end else if (delay2 != 0) begin
  284. // led[3] = 1'b1;
  285. // end else begin
  286. // led[3] = 1'b0;
  287. // end
  288. // Warm Boot
  289. // ---------
  290. // Bus interface
  291. always @(posedge clk_24m or posedge rst)
  292. if (rst) begin
  293. boot_now <= 1'b0;
  294. boot_sel <= 2'b00;
  295. end else if (wb_cyc[0] & wb_we & (wb_addr[2:0] == 3'b000)) begin
  296. boot_now <= wb_wdata[2];
  297. boot_sel <= wb_wdata[1:0];
  298. end
  299. assign wb_rdata[0] = 0;
  300. assign wb_ack[0] = wb_cyc[0];
  301. // Helper
  302. dfu_helper #(
  303. .TIMER_WIDTH(24),
  304. .BTN_MODE(3),
  305. .DFU_MODE(0)
  306. ) dfu_helper_I (
  307. .boot_now(boot_now),
  308. .boot_sel(boot_sel),
  309. .btn_pad(btn_n),
  310. .btn_val(),
  311. .rst_req(),
  312. .clk(clk_24m),
  313. .rst(rst)
  314. );
  315. // Clock / Reset
  316. // -------------
  317. `ifdef SIM
  318. reg clk_48m_s = 1'b0;
  319. reg clk_24m_s = 1'b0;
  320. reg rst_s = 1'b1;
  321. always #10.42 clk_48m_s <= !clk_48m_s;
  322. always #20.84 clk_24m_s <= !clk_24m_s;
  323. initial begin
  324. #200 rst_s = 0;
  325. end
  326. assign clk_48m = clk_48m_s;
  327. assign clk_24m = clk_24m_s;
  328. assign rst = rst_s;
  329. `else
  330. sysmgr sys_mgr_I (
  331. .clk_in(clk_in),
  332. .rst_in(1'b0),
  333. .clk_48m(clk_48m),
  334. .clk_24m(clk_24m),
  335. .rst_out(rst)
  336. );
  337. `endif
  338. endmodule // top